UNIT 4

PART A MCQ
1. An ASM chart consists of
a) Only state boxes
b) Only decision boxes
c) Only decision and conditional output boxes
d) State, decision, and conditional output boxes
2. An ASM chart can be
a) Converted into a state diagram
b) Converted into a state table
c) Implemented using gates and flip flops.
d) Converted as (a) and (b) and can be implemented as (c)
3. In as ASM chart, Mealy type of outputs
a) Cannot be represented
b) Can be represented by conditional output boxes
c) Can be represented by writing output state variables inside state box
d) Can be represented inside the decision boxes
4. An ASM chart can be implemented using flip-flops and
a) Gates
b) Multiplexers
c) Programmable logic devices
d) Any of the above
5. Mealy type of outputs are
a) Independent of the inputs
b) Dependent only on inputs
c) Dependent only on present state
d) Dependent on the present state and inputs
6. Moore type of outputs are
a) Independent of the inputs
b) Dependent only on the inputs
c) Dependent on present state and inputs
d) Dependent on type of hardware used for implementation

7. A synchronous sequential circuit can be described by

a) A state diagram only
b) A state table only
c) An ASM chart only
d) Any one of the above
8. An ASM chart of the Mealy model
a) Contains conditional output box
b) Does not contain conditional output box
c) Is represented by writing output state variable inside the state box
d) Contains only state and decision boxes
9. A decision box in an ASM chart
a) Does not have exit paths
b) Has only one exit paths
c) Has two exit paths
d) Has one entry and one exit path
10.A state box in an ASM chart
a) Is included only in one ASM block
b) Is not included in any ASM block
c) May be included in any number of ASM blocks
d) May be shared by two ASM blocks
11. ASM chart represents
a) Gates
b) Multiplexers
c) Synchronous sequential circuits
d) PLAs
12.An algorithmic state machine consists of
a) Only gates
b) Only multiplexers
c) Combinational circuits and flip-flops
d) Only flip-flops
13. An algorithmic state machine is the same as
a) Synchronous sequential circuit
b) Clocked sequential circuit
c) Finite state machine
d) All of the above
14.The types of asynchronous circuits are
i) fundamental mode circuits
ii) Pulse mode circuits.
a)i only b)ii only c) i and ii
15. The circuits in which the change in input signals can affect memory
element at any instant of time are called
a) Asynchronous sequential circuits.
b) Synchronous sequential circuits
16. In _________sequential circuits, memory elements are either unclocked
flip-flops or time delay elements.
a) Asynchronous sequential circuits.
b) Synchronous sequential circuits
17. In _________sequential circuits, memory elements are clocked flip-
flops.
a) Asynchronous sequential circuits.
b) Synchronous sequential circuits
18. Inputs are levels and not pulses for Fundamental mode circuit
a) True
b) False
19. Inputs are levels and not pulses for Pulse mode circuit
a) True
b) False
20. When an asynchronous circuit makes a transition through a series of
unstable states.
a) Cycles
b) Races
21. The unwanted switching transients (glitches) that may appear at the
output of a circuit.
a) Hazards
b) Cycles
22.The different techniques used in state assignment
i) Share row state assignment
ii) One hot state assignment
a)i only b)ii only c) i and ii
23. In a combinational circuit, if output goes momentarily 0 when it should
remain a 1, the hazard is known
a) Static 0
b) Static 1
24.In a combinational circuit, if output goes momentarily 1 when it should
remain a 0, the hazard is known
a) Static 0
b) Static 1
25. If output changes three or more times when it should change from 1 to 0
or from 0 to 1.
a) Static-1 hazard
b) Static-0 hazard
c) Dynamic hazard
26. An __________ hazard is caused by unequal delays along two or more
paths that originate from the same input. Such hazard can be eliminated
by adjusting the amount of delays in the affected path.
a) Static-1 hazard
b) Static-0 hazard
c) Essential hazard
27. Give hazard-free realization for the following Boolean functions.
f ( A , B ,C , D )=∑ M (0,1,5,6,7,9,11)
a) F= ᾹB̄C̄ + AB̄D + B̄C̄D + ᾹC̄D + ᾹBD + ᾹBC
b) F= ABC + ᾹB̄D + B̄C̄D + ᾹC̄D
c) F= ᾹBD + AB̄C
d) F= B̄C̄D + ᾹC̄D + ᾹBD + ᾹBC
28. Unequal delays means in the signal path of the circuit.
a) Glitch
b) Race
29. The procedure to analyze fundamental mode circuits is as follows
a) Construct the state table.
b) Construct the transition table.
c) Construct output map.
d) All the above
30. In synchronous circuits, the ________ are made with the objective of
circuit reduction.
a) State assignment
b) State reduction
31. In asynchronous circuits, the objective of ___________ is to avoid
critical races.
a) State assignment
b) State reduction
32. When two or more binary state variables change their value in response
to a change in an input variable, _________occurs in an asynchronous
sequential
a) Race condition
b) Cycle condition

33. If the final stable state that the circuit reaches does not depend on the
order in which the state variable changes, the race condition is not
harmful and it is called a ____________.
a) Noncritical race.
b) Critical race
34. The final stable state depends on the order in which the state variable
changes, the race condition is harmful and it is called a ___________.
a) Critical race
b) Noncritical race
35. If a cycle does not contain a________ the circuit will go from one
__________ .
a) Unstable state and stable state
b) Stable state and stable state
c) Stable state and unstable state
d) All the above
36. _________ can be avoided by making a proper binary assignment to the
state variables.
a) Cycle
b) Hazard
c) Races
37. The ________________ is an method for finding a race free state
Assignment.
a) one hot state assignment
b) Shared row state assignment
38. Asynchronous circuits are useful in application where the input signals
may
a) change at any time
b) never change
c) both a and b
d) None
39. The SR latch consists of
a) 1 input
b) 2 input
c) 3 input
d) 4 input

40. Table that is not a part of asynchronous analysis procedure is

a) transition table
b) state table
 c) flow table
d) excitation table
41. The making of transition table consists of
a) 2 steps
b) 4 steps
c) 5 steps
d) 6 steps
42. The output of SR latch is
a) x and y
b) q and q'
c) a and b
d) s and r
43. In asynchronous circuit, the changes occur with the change of
a) Input
b) Output
c) Clock pulse
d) Time
44. In synchronous circuits, present state is determined by
a) Unclocked flip-flops
b) Clocked flip-flops
c) Flip-flops
d) Latches

45. The present states and next state of asynchronous circuits are also called
a) secondary variables
b) primary variables
c) excitation variables
d) Short term memory
46. The race in which stable state depends on order is called
a) critical race
b) identical race
c) non critical race
d) defined race

47. Unclocked flip-flops are called

a) Latches
b) Register
c) Transition tables
 d) None

48. In all the cases final stable state is

a) Changed
b) Same
c) Inverted
d) Undefined
49. The complexity of asynchronous circuit is involved in timing problems
of
a) Inputs
b) Outputs
c) Clock pluses
d) feedback path

50. Each logic gate gives delay of

a) 1 to 5 ns
b) 2 to 10 ns
c) 3 to 10 ns
d) 3 to 5 ns
SOLUTION:
1. D 21. A 41. D
2. D 22. C 42. D
3. B 23. A 43. A
4. D 24. B 44. C
5. D 25. C 45. A
6. A 26. C 46. A
7. D 27. A 47. A
8. C 28. A 48. B
9. C 29. D 49. D
10.C 30. A 50. B
11.C 31. A
12.C 32. A
13.D 33. A
14.C 34. A
15.B 35. C
16. A 36. C
17. B 37. A
18. B 38. C
19. A 39. B
20. B 40. B
 UNIT 4
PART B MCQ
1. The characteristics equation of the below circuit is Q+a=W+X+YA;
QB+=Y+Z’B

a)True b)False C)only qa correct d) C)only qb correct

2. The characteristics equation of the below circuit is Q+a=W+X+YA;

QB+=Y+Z’B, what is c?

a) C=(w+sa)B b) C=(w+sb)B c) C=(w+rb’)B d) C=(w+x)B

3. Does the state flow table is shown in below figure shows any critical race:

a)Yes b)No
4. How many stable states are there for S2

a)1 b)2 c)3 d)4

5. The row and column in the below figure refers to

a)both b) a) Pulse inputs c) State variable inputs

6. Analyse the following ciricut:

i) ii)

a) i only b) ii only c) both correct

7. Analyse the following ciricut Output map:

i) ii)

a) i correct b) ii correct c)both

8. Identify the type of circuit

a) Static 1 b) static 0 c) dynamic hazard

9. Identify the type of circuit

a) Static 1 b) static 0 c) dynamic hazard

10. Identify the type of circuit

a)Static 1 b) static 0 c) dynamic hazard

11. Asynchronous sequential logic circuits usually perform operations in
a. Identical mode b. fundamental mode c. reserved mode. d. reset mode
12. In fundamental mode the circuit is assumed to be in
a. Unstable state b. stable state c. reset state d. clear state
13. The circuit removing series of pulses is called
a. Defined circuit b. bounce circuit c. DE-bounce circuit d. undefined circuit
14. The fourth step of making a transistion table
a. Determining feedback loop
b. Designating output of loops
c. Deriving functions of Y
d. Plotting Y
15. Which of the following sequential cicuit generate the feedback pathb due to the cross coupled
connection from the output of one gate to the input of another gate?
a. Synchronous
b. B. asynchronous
c. Excitation variables
d. Continuously change
16. In primitive flow table for the gated latch, each state has
a. 1 row
b. 2 row
c. 3 row
d. 4 row
17. In all cases the final stable state
a. Changed
b. Same
c. Inverted
d. undefined
18. The complexity of the synchronous circuit is involved in timing problems of
a. Inputs
b. Outputs
c. Clock pulses
d. Feedback path
19. Instability condition can be determind from
a. Table
b. Map
c. Graph
d. Logic diagram
20. Transition table consists of
a. Squares
b. Rectangles
c. Circles
d. Oval
21. Asynchronous sequential logic circuits are used when a primary need is
a. Time
b. Pressure
c. Speed
 d. Accuracy

22. Internal states and input values together are called

a. Full state
b. Total state
c. Initial state
d. Output state
23. The behaviour of synchronous sequential circuit can be predicted by defining the signals at
______.
a. discrete instants of time b. continuous instants of time
c. sampling instants of time d. at any instant of time

24. Which memory elements are utilized in an asynchronous & clocked sequential circuits
respectively?

a. Time- delay devices & registers

b. Time- delay devices & flip-flops
c. Time- delay devices & counters
d. Time-delay devices & latches
25. Match the following sequential Circuits with associated functions

1. Counter -------- A. Storage of Program & data in a digital computer

2. Register -------- B. Generation of timing variables to sequence the digital system operations
3. Memory --------- C. Design of Sequential Circuits

Codes:
a. 1-A , 2-B , 3-C
b. 1-C , 2-B , 3-A
c. 1-C , 2-A , 3-B
d. 1-B , 2-C , 3-A
 UNIT4
PART B
SOLUTIONS
1. A
2. D
3. B
4. B
5. A
6. A
7. B
8. A
9. B
10.C
11.B
12.B
13.C
14.D
15.B
16.A
17.B
18.D
19.D
20.A
21.C
22.B
23.A
24.B
25.D