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Chris Basso APEC Seminar 2021
Chris Basso APEC Seminar 2021
Public Information
Public Information
Feb 2021 – Rev. 0.3
Agenda
Introduction to Control Systems
Compensation Strategies with an Operational Amplifier
The TL431 at Work in Compensators
Building a PID
Continuous-Time to Discrete-Time Domains
Mapping and Compression
Digital Compensation
Practical Implementation of Filters
Conclusion
Public Information
Agenda
Introduction to Control Systems
Compensation Strategies with an Operational Amplifier
The TL431 at Work in Compensators
Building a PID
Continuous-Time to Discrete-Time Domains
Mapping and Compression
Digital Compensation
Practical Implementation of Filters
Conclusion
Public Information
What is a Control System?
An open-loop system links the output to the control variable
H s
U s control output
Y s U s H s
Plant
s Verr s
+
U s Y s Verr s H s
-
Plant
G s U s Y s G s
H s
input output
Public Information
Shaping the Loop with the Compensator
The compensator builds the error variable and ensures stability
Insert poles and zeros to build the compensation strategy
Choose how to cross over at fc with phase and gain margins
Compensator dynamic response
G s G f
s Error
Vref Verr s
0 processing
k Vout s Verr s
G s G f
Scaling factor Vout s
1 10 100 1k 10k 100k
The block amplifies and shapes the error between Vref and Vout
Minimize the error between the setpoint and the output
Public Information
For a comprehensive analysis see APEC 2012 seminar: The Dark Side of Loop Control Theory
Building the Compensator the Analog Way
Associate active and passive components to form the compensation chain
6 Public Information
How do you Build a Compensator?
The compensator can be implemented with analog components
Vout Vout Vout
verr
verr
Op amp TL431 OTA
7 Public Information
Compensating the Digital Way
A digitally-controlled system is a discrete-time system
It contains continuous- and discrete-time components
Digital comparator
Vc D
Vref Vout
Digital controller Digital modulator plant
000
N bits N-bit scaling factor
001
010 kD
011
100
quantizer
Quantization Sampling
(ADC)
v n
00101 v n 1 v n 1 v t
10011
10111 Ts
t t
n 1 Ts nTs n 1 Ts
Binary values Discrete time Continuous time
8 Public Information
* designates a discrete variable M. Jovanović, Introduction to Digital Control of Switch-Mode Converters, in-house course, PHX 2014
Why do we Need to Close the Loop?
We want to compensate the power stage deficiencies to obtain:
vout t
0V vref t 0V
speed
Stimulus Response
What compensation strategy?
9 Public Information
Choosing the Crossover Frequency fc
Selecting fc depends on the topology and its control mode
F * F *
Buck 3 f 0 f c sw f c sw
2 2
Boost 3 f 0 f c 0.3 f RHPZ f c 0.3 f RHPZ
10 Public Information
f0 is the LC network resonant frequency
Crossover Frequency Impacts Response Speed
Adjust fc to meet the transient response you want
(V) 5.00
45 mV f c 20 kHz
67 mV
4.90 I out 1
fc
130 mV Vout 2 Cout
4.80 CCM buck
Depends on Cout and fc
converter
990u 1.17m 1.35m 1.53m 1.71m
5.05
vout t m 30 Crossover is constant to 5
m 45
kHz
m 60
5.00
Step
m 90 load
(V) 4.95
10 A
4.90
m 80 7A iout t
m 70
4.85
Iout = 3 A in 3 µs
Marginally depends on PM
990u 1.17m 1.35m 1.53m 1.71m
12 Public Information
Open-Loop Phase Margin Affects Closed-Loop Response
cos m m Open-loop phase margin It is an approximation
Qc Qc Closed-loop quality factor for a 2nd-order system!
sin m
20
m 10
Qc 10 m 20
8 Qc
m 30
6 m 45
Q m m (dB) 0
-3 dB
4
10
2
T s
1 T s m 90
0.5
0 20
0 20 40 60 80 100 10 100 1 kHz 10 kHz 100 kHz
m
360
76° Closed-loop response
2
13 Public Information
C. Basso, “The Dark Side of Loop Control Theory”, APEC 2012 Professional Seminar
Agenda
Introduction to Control Systems
Compensation Strategies with an Operational Amplifier
The TL431 at Work in Compensators
Building a PID
Continuous-Time to Discrete-Time Domains
Mapping and Compression
Digital Compensation
Practical Implementation of Filters
Conclusion
Public Information
Meeting the Selected Crossover Frequency
Extract magnitude and phase of the power stage transfer function at fc
° dB
180 40.0
Vout f Attenuation at 10 kHz
VFB f
90.0 20.0
G fc 12 dB
0 0
Vout f
VFB f
-90.0 -20.0
-180 -40.0
PS 140
10 100 1k 10k 100k 1Meg
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Shift the Magnitude Curve Up or Down to Meet Crossover
Tailor the compensator to offer a 12-dB gain at the selected crossover
° dB
180 40.0 Vout f Shift up by 12 dB
VFB f
90.0 20.0 f c 10 kHz
0 0
-90.0 -20.0
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Stay Away from the 360° Limit: Build Phase Margin
Add up plant and compensator phase responses to total less than -360°
Compensator: integrator Compensator fc
Log f Log f
G f G f
-145°
Phase boost
Decrease compensator 125
-270° lag near crossover -270°
+ +
Plant Plant
Log f Log f
H f 90
H f H f c 145
145
-180° -180°
H f c 270 boost 360 m
Loop phase
= Loop phase
=
Log f Log f
-180° -180°
f c1 f c2 m 70
boost m H f c 90
-360° -360° 0°
0° PM <0 PM
T f signal returns T f
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in phase
How to Create and Adjust Phase Boost
Combining a zero and a pole lets you adjust the boost from 0° to 90°
z fc
1 peaks at Apply k factor fz
s fz f
G s G0 G f c tan 1 tan 1 c fc fz f p k
s fc fp
1 f p k fc
Mid-band p
gain magnitude phase
180°
k 1 k 25
G f G f
20 dB f c 1 kHz
0 dB
k 25
G0
-20 dB boost
f c 1 kHz
k 1, 2, 5, 10, 25
k 1
90°
10 Hz 100 kHz 10 Hz 100 kHz
19 Public Information
D. Venable, The k-Factor: a New Mathematical Tool for Stability Analysis and Synthesis, Proceedings of Powercon 10, 1983
Boosting the Phase up to 180°
By placing a double zero and a double pole, the boost increases up to 180°
z1 s
1 1
s z2 f z1 fc f f
G s G0 G f c tan 1 tan 1 tan 1 c tan 1 c
s s fc f z2 f p1 f p2
1 1
p p
magnitude 1 2 phase
270°
k 1 f z1 f z2 k 25
G f G f
k 25 f p1 f p2
20 dB f c 1 kHz
0 dB 1 k2 1 Boost up
G0 to 180°
1 k G fc
G fc k 2 1
k2
-20 dB
f c 1 kHz
k 1, 2, 5, 10, 25
k 1
90°
10 Hz 100 kHz Public Information
10 Hz 100 kHz
20
There are Three Compensator Types
Gain
z
z1 s
1 Inverted zero 1 1
1 s s z2
G s G s G0 G s G0
s s s s
1 1 1
po p p p
1 2
G f G f G f
0 to 90 0 to 180
G f G f G f
0° phase boost Up to 90° phase boost Up to 180° phase boost
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Switching Topologies and Compensators
Select the adequate compensator based on the plant phase lag
clock VCC
FB FB
+
-
CS
-
+ LEB kdiv LEB
vCS t CS verr t vCS t
+
- VCS ,max
Vref Vp Vref
VCS ,max
vsaw t
PWM block
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Provide Gain or Attenuation at fc: no Boost
Type 1 is a simple integrator without phase boost
20
Vout s G fc 20 dB @ f c 10 Hz G fc 10 20
0.1
C1 fc
R1 f po 100 Hz
G fc
60 0
V s 0
Virtual ground fc
VFB s 40 G f
20
(dB) (°)
Vref Rlower 0
G f -270°
1 1
G s po -20
s R1C1
-40
po No role 0.1 100
23
in ac Public Information
The Finite Open-Loop Gain Limits the dc Gain
The op-amp characteristics affect the frequency response
Virtual ground is lost in dc AOL kdiv
G s
s AOL kdiv s
Vout s 1 1
C1 po p AOL
kdiv AOL
100
R1 38 kΩ
80 dB – 30 Hz 66.4 fc G f
Rlower 50
kdiv
V 0 kdiv Vout Rlower R1
VFB s -13.6 dB
(dB) 0
AOL
Rlower 10 kΩ
-50 G f
p
1st pole 2nd pole
-100
Voltage divider enters the picture at dc 1 mHz 1 Hz 100 Hz 100 kHz
24 Public Information
Simulating Large-Open-Loop-Gain Compensators?
If you use an op-amp model, use another E-source to fix the operating point
E1
LoL -100 dB °
G f
1G
ok 12.0V
5
12.0V
4
40 270
C1
R1 2.50V
0.1uF Rdum
2.62V 38k 8
3
Vcc
2.50V 12.0V 0 180
1 6
12.0V CoL
1G
VCC
VFB
VEE 2.50V 0V V3
-40 90
-12.0V
Vee
2
7
V2
AC = 1
Vcc Vee 2.5
G f
Vref
X2 2.5
R2 V4 V5 -80 0
10k 12 12
TL081M
GAIN
8
XPWM C4 {RL}
{C1} {R2}
GAIN
K = 0.36 LoL
1k
695mV 695mV
C2
6 17 2.50V 180u
parameters CoL 2.50V
1k 5
0V 10
19 X3 R5
Vin=9 AMP384X Vref
V5 2.5 10k
RL=5 AC = 1
boost=pm-(pfc)-90
-90 -40
Vout f G=10^(-Gfc/20) BOOST = 4.10e+001
Hf H f c 61 boost=pm-(pfc)-90 G = 1.58e+001
-180 -60 Vc f pi=3.14159 PI = 3.14e+000
K=tan((boost/2+45)*pi/180) K = 2.19e+000
10 100 1k 10k 100k
C2=1/(2*pi*fc*G*k*Rupper) C2 = 4.58e-011
C1=C2*(K^2-1) C1 = 1.75e-010
R2=k/(2*pi*fc*C1) R2 = 2.00e+005
m = 63°
40 90 5.04 f c 10 kHz, m 63
T f
0 0 5.00
G f
fz fp k1=20% f z1 f p1
f f x y
tan 1 c tan 1 c k1 boost tan 1 x tan 1 y tan 1
fz fp 1 xy
f z1 f z
tan boost k1
2
4 f p fz f p fz f p fz
2
fc 2 f p f z 2
fc
2 fz tan boost k1 f c fc fp
f p1
31 4/1/2021 Public Information
Increase the Boost by 20%
Spread pole and zero while keeping mid-band gain untouched
0 0
fc G f fc G f
40 40
20 k1=20% 20
(dB) (°) (dB) (°)
0 0
boost boost
-20 -20
fz fp f z1 f p1
G f G f
-40 -360 -40 -360
10 100 1k 10k 100k 10 100 1k 10k 100k
50
20 dB
(dB) GBW
Ideal type 2
0
fc
20fc
-50
1 10 100 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz
34 Public Information
Design Example with a Type 3 Compensator
A voltage-mode-controlled buck converter is a typical usage for a type 3
PWMVM
L = 47u Vout
Fs = 100k rL L1
100m 5.00V 47u 5.00V
a c 5.01V
3 14 1
444mV d
9
PWM sw itch VM p Verr
C4
{C2} R3
592mV {R3} rC
2 R6
4
C1 R4 10k 5.00V 50m
Vin {C1} {R2} 15 C3
{Vin} Rload
{C3} 8 5.00V
GAIN
7
XPWM 2.50V {RL}
GAIN
K = 0.75 LoL
1k
592mV
10.0V 592mV
C2
5 17
2.50V 190u
CoL 10 2.50V
parameters 1k 16
0V X2
19 AMPSIMP Vref R5
Vin=10 V5 2.5 10k
RL=5 AC = 1
35 Public Information
Extract Data from the Control-to-Output Transfer Function
Choose fc beyond f0 but watch for the op-amp gain-bandwidth product
parameters
dB ° Control-to-output transfer function Poles and zeroes can
Rupper=10k
40 180 fc=10k be placed
H f c 12 dB Gfc=-12
Hf pfc=-144 independently unlike
pm=60
20 90 boost=pm-(pfc)-90
with k-factor
G=10^(-Gfc/20)
H f pi=3.14159
0 0 fz1=1k
fz2=1k
fp1=fc/tan((2*atan(fc/fz1)-tan(fc/fp2))-boost*pi/180)
-20 -90 fp2=50k
C1=1/(2*pi*fz1*R2)
Vout f C2=C1/(C1*R2*2*pi*fp1-1)
C1 = 2.63e-008
Hf C3=(fp2-fz2)/(2*pi*Rupper*fp2*fz2)
C2 = 2.70e-009
-40-180 Vc f H f c 144 R3=Rupper*fz2/(fp2-fz2)
C3 = 1.56e-008
R3 = 2.04e+002
a=sqrt((fc^2/fp1^2)+1) A = 1.37e+000
10 100 1k 10k 100k b=sqrt((fc^2/fp2^2)+1) B = 1.02e+000
c=sqrt((fz1^2/fc^2)+1) C = 1.00e+000
d=sqrt((fc^2/fz2^2)+1) D = 1.00e+001
R2=((a*b/(c*d))/(fp1-fz1))*Rupper*G*fp1 R2 = 6.06e+003
36 Public Information
Assess Compensation Effects with Transient Steps
The buck transitions from a 2nd- to 1st-order model when going to DCM
m = 60°
20 90 5.04 CCM
T f
0 0 5.00
fc = 10 kHz
-20 -90 4.96 DCM DCM CCM
0.1 A 1A
0.05 A 0.5 A
-40 -180 4.92 vout t 1 µs 1 µs
10 100 1k 10k 100k 1.20m 3.60m 6.00m 8.40m 10.8m
One of the zeroes could go to a lower frequency and improve DCM response
37 Public Information
Agenda
Introduction to Control Systems
Compensation Strategies with an Operational Amplifier
The TL431 at Work in Compensators
Building a PID
Continuous-Time to Discrete-Time Domains
Mapping and Compression
Digital Compensation
Practical Implementation of Filters
Conclusion
Public Information
The TL431 in Compensators
The TL431 is the most popular choice in adapters designs
It associates an open-collector op amp and a reference voltage
The internal circuitry is self-supplied from the cathode current
When the R node exceeds 2.5 V, it sinks current from its cathode
K
R
K
TL431A R
A R
A
2.5V K
A
39 Public Information
Many Different Variations Around the Part
Part number Max voltage (V) Min operating Reference voltage Packages
current (µA) (V)
40 Public Information
The TL431 Type 2 is Associated with the Optocoupler
A type 2 based on the TL431 requires a single capacitor C1
Vout Vdd Type 2 TL431
pole Vout
C2
R pullup RLED R1
R1
C1 Fast Slow
lane lane
VFB zero
R2
Rbias
VFB pole
C2 C1 zero
Rlower
Vref
TL431 Rlower
Type 2 op amp
41 Public Information
The Optocoupler Adds its Own Dynamics
The optocoupler hosts a low-frequency pole: characterize it
Reproduce the controller internals where the opto connects
Vdd 5 V Frequency
Response
Tweak to the same bias Analyzer
R pullup
2.8 V VB VA Req
FB
PWM
R1 reset 20 kΩ 100 kΩ 4.7 µF
c a
Req
R2
5V
GND vCS t e k
10-100 kHz
Adjust
bias
42 Public Information
The Original Pole is Modified by the Optocoupler
A simple 1st-order model includes an output capacitor
1
Copto 2 nF
2 f p R pullup
c a
Ic CTR Vf
Copto If
Ic
e CTR k
If
Simplified 1st-order model
43 Public Information
The LED Resistance Influences Bias Point and Gain
Select RLED so that the optocoupler always pulls VFB low in worst-case
Vout
dB ° R pullup
G0 CTR
Vdd
40.0 180
Not ok RLED
RLED
Requires
Minimum less
f c 500 Hz
gain!
20.0 90.0 H s than 17 dB
R pullup I bias of gain
VFB 0 0
Vf
-17 dB
VCE , sat -20.0 -90.0
VTL 431,min arg H s
-40.0 -180
ok
Vout V f VTL 431,min
RLED ,max R pullup CTR min
Vdd VCE , sat I bias CTR min R pullup 10 100 500 1k 10k 100k
Public Information
Apply the Compensation to a CM-LLC Converter
The current mode LLC can be stabilized with a type 2 compensator
45 Public Information
A Current-Mode LLC Converter Operates in Free-Running
The on-time duration is precisely memorized and mirrored for the off-time
Next cycle
Counter
reset
Hi-frequency + vCS t
clock stop
- verr t
D0 Dn
Digitized ton
duration
46 Public Information
Simplified ton Replication with SIMPLIS®
Using digital counters with SIMPLIS® is not an option if small-signal analysis is wanted
A simple capacitor-based circuit does the job well and remains compatible with POP
Capacitor Ct is charged by a
constant 1-µA current.
When the CS comparator sends the (V) vCt t
reset signal, capacitor stops
charging: end of ton.
The Ct capacitor is now discharged
with the same 1-µA source.
When its voltage touches ground,
this is the end of toff. (µA) iCt t
(V) Q
47 Public Information
No Change in Plant Response at Different Inputs
Hf H f
Vin 400 V
Vin 400 V
H fc V 15 dB
in 370 V
Fsw 74 kHz
H f c V 370 V
85
in
49 Public Information
CM-LLC Compensated Loop Gain
Plot the loop gain to check crossover frequency and phase margin at this point
(dB) (°)
m 70
f c 1 kHz
Tf T f
You can now assess parasitics impacts by sweeping these terms in Monte Carlo runs
50 Public Information
Compensated Transient Response
CM makes transient response stable and immune to input voltage variations
vout t
Vin 400 V
I out 10 to 20 A in 1µs
OUT / V
Vin 385 V
I out 10 to 20 A in 1µs
51 Public Information
Agenda
Introduction to Control Systems
Compensation Strategies with an Operational Amplifier
The TL431 at Work in Compensators
Building a PID
Continuous-Time to Discrete-Time Domains
Mapping and Compression
Digital Compensation
Practical Implementation of Filters
Conclusion
Public Information
The PID Controller in the Parallel Form
The block combines three actions: proportional, integral and derivative
P k p t
+ t vc t
vref t I ki t vout t
- Plant
d t
D kd
dt
Compensator
Minor Improve if
kd s Decrease Decrease No effect
change small kd
ki kp
G s kp skd Parallel form i s
1 s ki
H s 2
Factor kp
s s Tune k p ki kd
1 1 k
0 0 G s k p 1 s d Standard form d d s
s i kp
The plant The compensator
54 4/1/2021 Public Information
https://en.wikipedia.org/wiki/PID_controller
Each Coefficient Affects the Transient Response
G s H s 1
Calculate the closed-loop response to a 1-V step input: invlaplace vout t
1 G s H s s
k p 1 ki 1µ kd 0 k p 10 ki 1k kd 0 k p 10 ki 1k kd 1m
1.5 1.5 1.5
1.0
target 1.0 1.0
kp k p k p 2 4 k d ki
(dB) 60 +1 0 (°)
The derivative term cannot
z
1
kd 2kd be physically implemented
2
40
-1
G f 100
k p k p 4 k d ki ki 0
z G0
2
2k d z 1
20
10 100 1k 10k 100k 1Meg
z1 s
1 1
k skd s
GFPID s k p i 1 GT3 s G0
z2
s 1 s
1
s s s
1 1 1
p p1
N kd gain
p1
1
p2
Filtering Extra p2
pole hi-frequency pole
Identical responses
Assume the following specifications: 40
f c 3 kHz kd
z2 p1 k G 510 µs
i 0 p1
30
G f 100
2
p z1 2
G fc 20 dB f
2
f
2
(dB) (°)
1 c 1 c 20 0
f z1 200 Hz fp fp ki G0z1 2.51 ks 1
1 2
G0 2
f z2 600 Hz fz
1 1
2
f
1 c
2
z z2 z1
10 G f -100
f p1 21 kHz fz
fc 2 k p G0 1
z
2.643
2
p1
f p2 21 kHz 100 1k 3k 10k 100k
fc=10k d Resr
Gfc=-20
3
PWM switch VM p 70m Large Integral C6
0.1u
Vin
Vin=10
Vpeak=2
{Vin}
AC = 0
X7
PWMVM 16
I1 current voltage 10 9
I
L = 75u
Fs = 100k
Cout
220u step X5
R10
IntFilt AMPSIMP
{Ti/0.1u}
G=10^(-Gfc/20)
pi=3.14159
13
fz1=1.2k
fz2=1.2k
5
vint t DeriveFilt
XPWM R9 vout
GA IN
Wp1=2*pi*fp1 SUM3 K2
K
K2
+
19 17 S +A 20
K
K3 Vref
S +A 18 8 X3
i=(1+fc^2/fp1^2)*(1+fc^2/fp2^2) B2 R8 SUM2 5
err2 X4
Voltage 10k K1 = 1
j =(1+fz1^2/fc^2)*(1+fc^2/fz2^2) SUM3 X1 K2 = -1
V(err2)>1.99 ? X8 K1 = 1 POLE
Wpi=sqrt(i/j )*G*fz1*2*pi 1.99 : AMPSIMP K2 = 1 FP = (N/Td)/(2*pi) R7
V(err2)<10m ? 10m : V(err2) VHIGH = 5 K3 = 1
10k
VLOW = -5
e=(Wp1-Wz1)*(Wp1-Wz2) Control voltage 25
f=Wp1*Wz1+Wp1*Wz2-Wz1*Wz2
vc t
Vdirect
Td=e/(f*Wp1)
N=((Wp1^2)/f)-1
Ti=((Wz1+Wz2)/(Wz1*Wz2))-(1/Wp1)
X10
AMPSIMP P
kpf=(Wpi/Wz1)-(Wpi/Wp1)+(Wpi/Wz2)
The transient response shows overshoot due to saturation and recovery time
60 Public Information
Anti-Windup Methods
Insert a clamping circuit at the PID output
P k p t
vc t
2V
+ t +
vref t I ki t vout t
- - Plant
d t
D kd
dt + -
Compensator
kb
62 Public Information
Transient Response with Back Calculation Anti-Windup
C6
X5
AMPSIMP R10
kb 0 6
5.50
SUM2
X12
SUM2
R9 K1 = 1 vout
K2
K1
(V) 4.50 {Td/0.1u} K2 = 1
3.50
kb 1 11
X9
28
INTIN
-
AMPSIMP
vout t
K1
K1 SUM2
5
2.50 SUM3 K2
17
K
S+A
C7 K2
+
8
K3
0.1uF
13 X3 Vref
R8 SUM2 5
X4
1.20 kb 0 SUM3
K1 = 1
X1
POLE
10k K1 = 1
K2 = -1
K2 = 1 FP = (N/Td)/(2*pi) R7
K3 = 1 10k
800m 25
(V) 400m
0 kb 1 X6
vint t
15
POLE R100
S+A 18
B2
Voltage
X11 X8
SUM2 AMPSIMP
X13
GAIN
63 Public Information K=1
Transient Response with Integral Reset Anti-Windup SW
C6
0.1u
10 9
X5
R10
6.50 Without reset AMPSIMP
{Ti/0.1u}
6
5.50
SUM2
X12
(V) 1
2
R9
SUM2
K1 = 1 vout
K2
K1
4.50 {Td/0.1u} K2 = 1
11 28
K2
17
K
S+A
C7
0.1uF
5
SUM2
K2
+
8
K3 Vref
13 X3
R8 SUM2 5
X4
SUM3 10k K1 = 1
X1
1.00 Without reset K1 = 1
K2 = 1
K3 = 1
POLE
FP = (N/Td)/(2*pi) R7
10k
K2 = -1
(V) 700m
25
400m
X6 15
vint t K = -1 R12
{10k/kpf}
D err2 2
-200m S+A
K
18
B2
Voltage
300u 900u 1.50m 2.10m 2.70m X11
SUM2
X8
AMPSIMP
K1 = 1 VHIGH = 5
K2 = -1 VLOW = -5
K1
V(err2)>1.99 ?
1.99 : SUM2
12 + SW
V(err2)<10m ? 10m : V(err2) K2
14 -
Sat
V7
64 Public Information 1 X14
COMPARHYS
Turn off the Pole at the Origin in a Type 2
The added current source can be turned on or off, removing the pole at the origin
C2 Z f s
1 1 1
Z f s R2 || R2 p
sC2 s R2C2
1
p
R2
R1
G s g m k1 s
R2
G0
1 G0 R2
Vin s s s R1
Vout s 1 1
p p
R2
1 g m k1 s 1 z
g m k1 s 1 G0 s
k1 s G0 G0
s s s
z 1 1
po po p p
g m R1
New equation Type 2
65 Public Information
Example with the Pole at the Origin Toggling Circuit
The added current source can be turned on or off, removing the pole at the origin
R3 C4
{R1} {C2}
parameters R7 R5
10k {R2}
R4
R1=38k
fc=1k
{R1} C3
{Ck}
2
Pole/zero
Vout1
Gfc=-20
pfc=-90
gm 5
on demand
pm=70
4 8
E2
G=10^(-Gfc/20) 100k
boost=pm-(pfc)-90
pi=3.14159
E3 G2 C2
K=tan((boost/2+45)*pi/180) {C2}
100k {gm}
fz=fc/k integrator C1 R2
fp=k*fc {C1} {R2}
gm=10u
R1
{R1}
6
Classical type 2
R2=G*R1 vin Vout2
C2=1/(2*pi*fp*R2) 1
3
compensator
C1=1/(2*pi*R2*fz) Vin
R6
Ck=gm/(2*pi*fz) AC = 1
10k
E1
Approximate formulas 100k
for C2 << C1
66 Public Information
On-Demand Pole at the Origin and Zero
By setting the transconductance gm to zero, the pole and zero are removed
(dB °) (dB °)
40.0 170
G f 40.0 170
gm 0 G f
0 90.0 0 90.0
G f g m 10 µS G f
10 100 1k 10k 100k 10 100 1k 10k 100k
Turn the current source off to improve overshoot and recovery time
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Application in a High-Current Dc-Dc Converter
The output current changes from 61 A to 1 A in 1 µs: undershoot and ringing are gone
Pole at the origin is active Pole at the origin is disconnected and back in place
vout t vout t
4 µs
verr t verr t
NCP81111
68 Public Information
Agenda
Introduction to Control Systems
Compensation Strategies with an Operational Amplifier
The TL431 at Work in Compensators
Building a PID
Continuous-Time to Discrete-Time Domains
Mapping and Compression
Digital Compensation
Practical Implementation of Filters
Conclusion
Public Information
Continuous-Time and Discrete-Time Signals
The switch samples the input signal at a Ts switching interval
u t u t v n 1 Sample
v n
Sampler
v n 1
0 t 0 t
Time-continuous waveform
Ts n 1 Ts nTs n 1 Ts no u n 1.5
Sampling period
Sampling clock Ts
n 1 Ts n 2 Ts
There is no discontinuity in u along the time axis There is no in-between sample value
u can take on any value: u t U sin t n is an integer: u n U sin nTsw
70 Public Information
B. White, Digital Control for Power Supply Engineers, APEC 2013, Professional Seminars
Fourier, Laplace and z-Transforms
Laplace and Fourier transforms map continuous-time functions
U Two-dimensions U
Fourier transform
frequency domain
Time-continuous j t
U u t e dt
bilateral U U
Laplace transform
s-domain
u t U s u t e dt st
0
s j
unilateral
j j
Third dimension
The z-transform maps discrete-time functions Im z
z-domain
U z u n z n
U z 1 z 1 z 2 z 3 ... Re z
n0 1
Discrete-time
Im z
Discrete-time
U ( z ) {u[ n]} y n 1
H z U z
Re z H z 1 z 1
Inverse-Z
Z-transform
z e sTs transform
Digital compensator y t
u t
Map to the z-plane
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Step-Response via Laplace- and z-Transforms Approaches t
y t u t 1 e
The stimulus is continuous in time 1
0.8
step
1 0.6 63%
1 1 1 1
H s y t 1
0 1 s 1 0.4
s s 1 s
u t
s-domain Transfer function in s 0.2
Time-continuous
Continuous time
y t
0
0 10 ms
n n
The stimulus is a discretized signal y n a 1 a u n 1 a u n u n
1
0.8
step 0.6
1
z a z a
y 20
H z y n 1 1
0.4
0 z 1 1 1 a z 1 z 11 1 a z
u t 0.2
Discrete time
z-domain Transfer function in z y n
Discrete time
0
0 20 40 60 80 100
73 Public Information
From Laplace to z-Transform
Take the Laplace transform of the sampled signal
U
s u t u nTs e snT
s
u 0 u Ts e sTs u 2Ts e 2 sTs ... u nTs e nsTs
n 0
This is
z e sTs or z 1 e sTs a delay
U z u nTs z n u 0 u Ts z 1 u 2Ts z 2 ... u nTs z n
n0
74 Public Information
Z-Transform of a Time Delay
The signal y*(t) is u*(t) shifted by 3 clock cycles y n u n k k 3
u n 3 u t
n2 n3
Y z u n k u n k z n
n 0
n 3 n 2 n 1 n n 1
3 clock cycles Y z U z z k
y n y t
n 3 n 2 n 1 u n z 3 u n 3
n n 1 n 2 n 3
u n z 1 z 1 z 1 u n 3
75 Public Information
B. White, Digital Control for Power Supply Engineers, APEC 2013, Professional Seminars
Assemble Blocks to Form a Transfer Function
Assume the following difference equation
y[n] u n u n 1 y n k Y z z k
Involve the delay operator to z-transform the expression y[n] Y z
1 y n k Y z z k
Y z U z U z z
Y z
Factor and rearrange: 1 z 1
U z
u n y n
This is a simple 1 G0 2
z 1
+ low-pass filter
G s G0
s p
2
1 Ts
u n 1 p
76 Public Information
How do you Practically Build a Delay?
A register delays the information by one clock cycle
One cycle
/ No delay
vclk t 8
output
8
delay 1 1 1
data z z z / Three cycles
vQ t
77 Public Information
Modeling the Delay with SPICE
A delay line in SPICE can be used to model a delay
u t UTD
y t G s e sTs Ae j
Ts = 1 µs G 1
5
90.0 2.00
G f G f
0 0 0 0
-90.0 -2.00 G f -5 G f
78 Public Information
S. Ben-Yaakov, D. Adar, Generic Average Modeling and Simulation of Discrete Controllers, APEC 2001
Approximating the Delay (1)
A delay can be defined by associating a RHP zero and a LHP pole (all-pass filter)
s Gd 1 Pole/zero cancel
1 each other
Gd s
s 1 1
1 Gd tan 1 tan 2 tan
What value of satisfies this equality?
1 s
arg e sTs
arg Ts 2 tan 1
1 s
0
Use the arctangent Taylor series equivalent: 3 5
x3 x5
1
tan x x ... 2
3 5 3 5
Public Information
79
Approximating the Delay (2)
Solving for gives us the 1st-order Padé approximant of the exponential
Ts 1 s
1 s
sT 2 z 2
e s
with z p
Ts s Ts
1 s 1
2 p
180
e sTs
-180
1k 10k 100k
Public Information
Agenda
Introduction to Control Systems
Compensation Strategies with an Operational Amplifier
The TL431 at Work in Compensators
Building a PID
Continuous-Time to Discrete-Time Domains
Mapping and Compression
Digital Compensation
Practical Implementation of Filters
Conclusion
Public Information
Discretizing Continuous-Time Transfer Functions
How to move from one domain (continuous time) to the other one (discrete time)?
Rf Cf
00101
10011
10111
Ri
Vout s ?
Verr s
Vref s f z
Digital control
Rf 1
sVerr s s Vout s Vout s b0Verr z b1 z 1Verr z a0Vout z a1 z 1Verr z
Ri Ri C f
z e sTs
A A1 A2 A3
A1 A2 A3
t
0
n 2 Ts n 1 Ts nTs
83 Public Information
Three Integration Options x nTs
The area can be approximated in three ways x n 1 Ts x nTs
Forward x n 1 Ts 2
x n 1 Ts
x nTs A2 x n 1 Ts Ts
Ai A2 x n 1Ts Ai
x n 1 Ts
0
Ai ? n 1 Ts nTs n 1 Ts nTs
x nTs Backward x n 1 Ts x nTs
A2 Ts
2
0 A2 x nTs Ts
n 1 Ts nTs x n 1 x n
Ai A2 x n Ts A2 Ts
2
Trapezoidal integration
Flat-top approximation
0 Public Information
84
n 1 Ts nTs
Discretizing in Different Ways
Forward-Euler method
Y z Y z z 1 X z z 1Ts
y n y n 1 x n 1Ts Y z z 1Ts z Ts Y s 1
X z 1 z 1 z z 1 X s s
Integral value Integral value at Approximate integral
z 1
at sample n previous sample between samples H z H s s z 1 s
Ts Ts
Backward-Euler method
Y z Y z z 1 X z Ts
y n y n 1 x n Ts Y z Ts z zTs Y s 1
X z 1 z 1 z z 1 X s s
Integral value Integral value at Approximate integral
z 1
at sample n previous sample between samples H z H s s z 1 s
zTs zTs
85 Public Information
Tustin and Backward/Forward Euler Methods
Tustin method
2Y z 2Y z z 1 X z z 1Ts X z Ts
x n 1 x n
y n y n 1 Ts 2Y z 1 z 1 X z Ts 1 z 1
2
Ts 1 z z
1
Y s 1
Integral value Integral value at Approximate integral Y z X z
at sample n previous sample between samples 2 1 z 1 z X s s
2 z 1
H z H s s 2 z 1 s
Other approaches Ts z 1 Ts z 1
Discretization Method What is Important?
Zero-Order Hold (ZOH) Transient response with a staircase input
Tustin brings a good
First-Order Hold (FOH) Transient response with a PWL input
matching between frequency-
Transient response with impulse train
Impulse-Invariant Mapping
input and discrete-domains
Good matching between frequency- and
Pole-Zero Matching
discrete domains
86 Public Information
https://www.mathworks.com/help/control/ug/continuous-discrete-conversion-methods.html
Viewing Tustin, Backward- and Direct-Euler Differently
It is possible to approximate the exponential using Taylor’s series expansion
1
e x 1 x x 2 ... x n 1 ex 1 x
n 1!
Neglecting
high-order terms
10 10
Fs 40 kHz Fs 40 kHz
f p fd
f p 1 kHz f p 10 kHz f p 10 kHz
0 0
-3 dB -3 dB
(dB) (dB)
Ga f
-10 -10
1 e j
f d 8.5 kHz
G2 G0
1 b1e j
fd is the discrete pole
Gd f
10 100 1k 10k 100k 10 100 1k 10k 100k
f p fd f p fd
0.2% 15.2%
88 fp Public Information fp
From the s-Plane to the z-Plane – Exact Mapping
The stable pole region – left half-plane – entirely maps inside the unit circle
j z z Im z
s magnitude angle
unstable
j
Ts region
z e
j Ts
j
0 e Ts e jTs k 2
2Ts 0
Ts Ts 1
stable Re z
-10 -1 k 2 region k 2
j
2Ts s0 z 1 Ts Ts Ts
0 z 1
Left half-plane Right half-plane z 0
z 1
Ts 1 s 0
Imaginary
The imaginary part defines the angle
The real part defines the radius
The stable poles (LHPP) in s are confined inside the unit circle
Unstable poles (RHPP) in s lie outside the unit circle
89 4/1/2021 Public Information
Watch Brian Douglas’s videos at https://www.youtube.com/channel/UCq0imsn84ShAe9PBOFnoIrg
The Bilinear Transform
Tustin’s approximation maps the entire j axis on the unit circle in the z-plane
j Im z
T
1 s s unstable
j 2
Ts z region
Ts d
Ts
j
2Ts
0 1 s
2 a stable 0
region
1
Re z
-10 -1
s0 z 1 a
0 z 1 d
Ts
Left half-plane Right half-plane z 1
z 1
Ts 1 s 0
Imaginary
The stable poles (LHPP) in s are confined inside the unit circle
Unstable poles (RHPP) in s lie outside the unit circle
Stable in the Stable in the
s-domain z-domain
a analog world
90 Public Information
d discrete world
Compression in the Frequency Response
Map the s-domain transfer function in the z-domain with bilinear transform
1 Map to z 1
Ha s Ha z
1 s 2 z 1
In general:
1 Euler
j T T s z 1
ze d s
2 z 1 2 e j T 1 d s
2 d Ts
d a T e j T 1 a T 2
j T
Hd z Ha H e
d s
H H j tan
T
s z 1 s
d s
s
discrete analogue
2 T 0.9 1
d tan 1 a s fd fd tan 1 f a Ts
Ts 2 0.8 Ts
fa
discrete
0.7 f a 1 kHz f d 0.997 kHz
discretized
0.6
0 0.1 0.2 0.3 0.4 0.5 f a 10 kHz f d 8.5 kHz
Frequency warping f a Fs
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Fs 40 kHz
Magnitude and Phase Distortion of Mappings
Fs
Tustin offers the best magnitude tracking while phase diverges as you approach
2
4
reference e sTs
Exact
z 3 Forward Euler z1( s ) e
s T s
z 150
180
z 1( 2 i F)
Ts
arg z 1( i 2 F)
8 Tustin
Tustin 1 s 2 180
z 2( 2 i F) reference
z2( s ) arg z 2( i 2 F) 100
z 3( 2 i F)
2 Ts
180
8
1 s arg z 3( i 2 F)
z 4( 2 i F) 2
e sTs Forward
z3( s ) 1 s Ts
arg z 4( i 2 F)
180
Tustin
50
1
Backward
1
Backward and
z4( s )
1 s Ts forward Euler
0
Backward Euler 0
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
F 0.13 F
Fs Fs
Ts 2 f p 10 kHz
(dB) G2 f (°)
0 0 0 0
-3 dB
2 2 10k Ts 1
f p' tan 2 12.7 kHz -5 5
G2 f -45
25u 2
-10 10 -90
2 Ts p ' 2 10 100
G0 1 b1 1 kHz 10 kHz 100 kHz
Ts p ' 2 Ts p ' 2 Public Information
Agenda
Introduction to Control Systems
Compensation Strategies with an Operational Amplifier
The TL431 at Work in Compensators
Building a PID
Continuous-Time to Discrete-Time Domains
Mapping and Compression
Digital Compensation
Practical Implementation of Filters
Conclusion
Public Information
From the z-Equation to Practical Implementation
Start with the z-transform expression
Y z 1 z 1 Expand
G0 Y z Y z b1 z 1 U z G0 U z G0 z 1
U z 1 b1 z 1
Rearrange
Y z U z G0 U z G0 z 1 Y z b1 z 1
y n u n G0 u n 1 G0 y n 1 b1
2
1
How can we
u n G0 z 1
+ y n test this
3
configuration?
z 1 b1
95 Public Information
SPICE Simulates Delays Efficiently
We know z 1 can be modeled by a delay line in SIMextrix®
By reproducing the flow-graph blocks, you can build the transfer function
ba_z^-1
U1
*
u n u n 1 G0
y n .param Fs=40k
.param Ts={1/Fs}
.param fp=10k
u n G0 .param wp={2*pi*fp}
.param wpw={(2/Ts)*tan(wp*Ts/2)}
y n 1 b1 y n 1 .param G0={1-2/(Ts*wpw+2)}
.param b1={(Ts*wpw-2)/(Ts*wpw+2)}
*
Continuous-time
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Laplace TF
Plot the Continuous-Time Response
Pole frequency pre-warping offers an excellent matching
-3 dB
Phase / degrees
Gain / dB
-45°
Tustin
Tustin
G f G f
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SIMPLIS® Include 1st -Order Filters Blocks
A pole-zero equation implemented in SIMPLIS® is the following:
N 0 1
1 z Expand
N1 N 0 z 1 N1
T z N1 Y z Y z D0 z 1 U z N1 U z N 0 z 1
1 D0 z 1 1 D0 z 1
Rearrange
Y z U z N1 U z N 0 z 1 Y z D0 z 1
y n u n N1 u n 1 N 0 y n 1 D0
u n N0 z 1 + y n
? ?
z 1 D0
98 Public Information
Determining Coefficients Values
Replace z by its value in the s-domain: z 1 e sT s
Tsw
1 s
e sTsw 2
N1 N 0 z 1 N1 N 0 e sTsw
H z H s T
1 D0 z 1 1 D0 e sTsw 1 s sw
2
If we plug this expression into the original transfer function, we have:
Tsw 2 N1 N 0 H 0 p Ts z 2
1 s z N0
2 Tsw N1 N 0
N1 N 0
T s z Ts p 2
1 s sw 1
2 rearrange z 2 1 D0 H 0 p Ts z 2
H s H s H0 p N1
T s
1 s sw 1 Tsw 1 D0 z Ts p 2
1 D0 2 p
T N N1 4
1 s sw H0 0 D0 1
2 1 D0 Ts p 2
99 Public Information
The Implementation Requires a Clock Generator
This is a transient simulation with a POP block
G f G f
(dB) 10 (dB) 10
1
s
z
G s H0
s
f z 1 kHz 1
Fs 100 kHz 0 p
0 f p 10 kHz
90 90
G f Fs 1 MHz G f
45 45
(°) 0 (°) 0
-45 -45
-90 -90
10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
101 Public Information
Agenda
Introduction to Control Systems
Compensation Strategies with an Operational Amplifier
The TL431 at Work in Compensators
Building a PID
Continuous-Time to Discrete-Time Domains
Mapping and Compression
Digital Compensation
Practical Implementation of Filters
Conclusion
Public Information
Implementing a Type 2 Compensator
You start from the low-entropy form Laplace transfer function Divide by z2
z
1 G0Ts p 1 z 2 z Ts z Ts z z 2
s 2 1 z 1
G s G0 s G z
1
s Ts 1 z 1 4 z 2 8 z 2Ts p 2Ts p z 2 4
p Divide by z2
Biquad
filter
a0 a1 z 1 a2 z 2 Specifications:
G z
1 b1 z 1 b2 z 2 a0 0.0857
G fc 20 dB f c 1 kHz
G0Ts p Ts z 2 a1 1.957 10 4
a0 Boost 50
2 2 Ts p
boost a2 -0.0855
k tan 2.74
2 4
G0Ts 2 p z 2 b1 -1.9829
a1 b1 f z 364 Hz
2 Ts p 1 0.5Ts p
f p 2.74 kHz b2 0.9829
G0Ts p Ts z 2 2
a2 b2 1 Fs 1 MHz
2Ts p 4 1 0.5Ts p
103 Public Information
The Biquad Filter is a Recursive Digital Structure
A part of the output is fed back to form the transfer function
Feedforward
coefficients
Feedback
coefficients
Reduce to 1st
order filter
y[n] a0 x[n] a1 x[n 1] a2 x[n 2] b1 y[n 1] b2 y[n 2]
a2 b2 0
x n + y n
a0 a0
z 1 z 1 x n + y n
a1
+
1 b1 1
z 1
z z
a2 a1 b1
+ +
2nd-order b2
This configuration is called Direct Implementation I
Can be transposed in different forms (DI II) so as to minimize calculation errors
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Where are Poles and Zeroes?
If you read coefficients from the code or a circuit: where are poles and zeroes?
Tsw
1 s
e sTsw 2 Double zero
T G0 a0 a2
2
1 s sw T a0 a1 a2
2 1 sTs s2 s a a a
a0 a1 z 1 a2 z 2 a a a a0 a1 a2 2 0 1 2
Gz G s 0 1 2 2
1 b1 z 1 b2 z 2 b1 b2 1 1 b2 T b2 b1 1
1 sTs s2 s b b 1
b1 b2 1 2 1 2
Numerator and denominator follow the form: Double pole
2
T 2
N s a0 a1 a2 sTsw a0 a2 s s a0 a1 a2
2
2
N s 1 s z1 z 2 s z1 z 2 1 s z1 z 2 s 2 z1 z 2
T
2 G s G0
D s 1 b1 b2 sTs 1 b2 s 2 s b2 b1 1 1 s p1 p 2 s 2 p1 p 2
2 Normalized low-entropy form
D s 1 s p1 p 2 s p1 p 2
2
The second zero does not have a physical meaning in a type 2 compensator
1 1
f z1 fz2
2
T a a a 2 4a a
sw 0 2 1 0 2 Infinite value
2
sw
T a a a 2 4a a
2 0 1 0 2
2 a0 a1 a2 2 a0 a1 a2
a a a
G0 0 1 2
1 1 b11 b2 1 1
f p1 f p2
T
2
sw
b112 4b2 b2 1
b11 b1 1 p 2
sw
T b 1 b 2 4b
2 11 2
2 1 b11 b2 2 1 b11 b2
106 Public Information
Testing Coefficients with Mathcad®
Back-calculate poles and zero values: s
1
f p1 G0 z
f z 363.9 Hz f p1 1µHz f p2 2.74 kHz H 0 4 108 or 172 dB 20.008 dB G s G0
f z1 s s
Pole at the origin Infinite OL gain Mid-band gain
1
p1 p2
0 0
1. Reference
50
G f 2. Tustin
50 G f
3. Back-calculated 20 20
20 dB
40 40
(dB) 0 (°) (dB)0 (°)
60 60
Tustin
50
G f 80 50
G f 80
10 100 1 kHz 10 kHz 100 kHz 10 100 1 kHz 10 kHz 100 kHz
20 dB
G f Fs 1 MHz
OUT
n1
n2
n3
Fs 100 kHz
OUT
n1
n2
G f
*
.PARAM Fsw=100k .PARAM a0={G0*Tsw*wp*(Tsw*wz+2)/(2*Tsw*wp+4)}
.PARAM Tsw={1/Fsw} .PARAM a1={G0*Tsw^2*wp*wz/(Tsw*wp+2)}
.PARAM Ts=Tsw .PARAM a2={G0*Tsw*wp*(Tsw*wz-2)/(2*Tsw*wp+4)}
.PARAM fz=364 .PARAM b1={-8/(4+2*Tsw*wp)}
.PARAM fp=2.74k .PARAM b2={(4/(Tsw*wp+2))-1}
* *
.PARAM wz={2*pi*fz} { '*' } a0 = {a0}
.PARAM wp={2*pi*fp} { '*' } a1 = {a1}
.PARAM G0=10 { '*' } a2 = {a2}
* { '*' } b1 = {b1}
{ '*' } b2 = {b2}
20 dB *
108 4/1/2021 Public Information
Implementing a Type 3 Compensator
You can now repeat the exercise for a 2-zero/3-pole compensator
2 1 z 1
z1 s s
1 1 Ts 1 z 1
s z2
G s G0
s s
1 1
p1 p2
N z G0Ts p1 p2 z 1 2 z Ts z1 Ts z1 z 2 2 z Tsz2 Tsz2 z 2
Divide by z 3
D z 2 z2 z 1 2 z Ts p1 Ts p1 z 2 2 z Ts p2 Ts p2 z 2
a0
G0Ts p1 p2 Tsz1 2 Tsz2 2 a3
G0Ts p1 p2 Ts z1 2 Tsz2 2
1
a0 a1 z a2 z a3 z2 3
2 4 z2 2Ts p1 z2 2Ts p2 z2 Ts 2 p1 p2 z2
2 4 z2 2Ts p1 z2 2Ts p2 z2 Ts 2 p1 p2 z2
G z 2
G0Ts p1 p2 2Ts z1 2Ts z2 3Ts z1 z2 4 Ts p2 2 4 16
1 b1 z 1 b2 z 2 b3 z 3 a1
2 4 z2 2Ts p1 z2 2Ts p2 z2 Ts 2 p1 p2 z2
b1
Ts p2 2 Ts p1 2
b2
T
s p1
2 Ts p2 2
a2
G0Ts p1 p2 2Tsz1 2Ts z2 3Ts 2z1 z2 4
b3
T s p1
2 Ts p2 2
2
2 4z2 2Ts p1 z2 2Ts p2 z2 Ts p1 p2 z2 T s p1
2 Ts p2 2
+
Zeroes calculation Poles calculation
110 4/1/2021 Public Information
M. Jovanović, Introduction to Digital Control of Switch-Mode Converters, in-house course, PHX 2014
Going Digital – Converting Samples in Words
The analog-to-digital converter converts the sample in a binary word
Sampler u n u nTs
ADC v ADC t
N bits
u t
1 1 1 u t
Ts
ba_z^-1
* Enter Design Goals Information Here *
U7
*
discrete .PARAM fc=3k ; targeted crossover
*
V(N1)-V(N2)
ARB3
.PARAM Fsw=1Meg ; sampling frequency
.PARAM Tsw={1/Fsw} ; sampling period
.PARAM Ts=Tsw
OUT
*
*
n1
n2
n3
.PARAM fz1=200
.PARAM fz2=600
Discrete- to .PARAM fp1=21k
continuous- .PARAM fp2=21k
OUT
.PARAM Gfc=-20 ; magnitude at crossover
time *
n1
n2
n3
.PARAM wz2={2*pi*fz2}
.PARAM wp2={2*pi*fp2}
Automated calculation
Ki K d Ad z kd
G z Kp Kp kp K i kiTs Kd
Ai z K d Ad z 1 Ts Forward-Euler
1 1
0 p1 ,z 1 kd 0 Backward-Euler
Internal z transfer functions p1 kd Pole must lie
computed with forward- or
in unity circle
0.5 Tustin
backward-Euler or Tustin
f c 3 kHz G0 1.99
Ts 1 µs
G fc 20 dB K p k p 2.643
K i kiTs 2.509m
f z1 200 Hz
kd
f z2 600 Hz Kd 510
Ts
f p1 21 kHz 1 You can choose and
15m
f p2 21 kHz p1 k d combine mapping
Externally
functions
implemented
Second pole
P k p t
+ t vc t
u t I ki t
-
d t
y t D kd
dt
Vc s k k 0
k p s Vc n k p n n kp k p n
i d
kp +
n Ts + Vc n
i +
z 1
k p d +
n + Vc n
Ts -
1
z
kp Proportional
kp + Integral
n Ts + + Vc n
i -
z 1
k p d Derivative + + Filter
+ a +
Ts - +
1
z z 1 1 a
i
z z
1 2
1
N
p 2 1
1 kp
po po po
d
p1 z1 p1 z2
z z1 2
p 1
p z p z z z
1 1 1 2 1 2
z p z
1 1 2 p1 z p z z z
1 1 2 1 2
p1
ba_z^-1
U3
V(N1)-V(N2)
ARB5
V(N1)+V(N2)+V(N3)
ARB2
Zero-order hold (ZOH)
Automated
V(N1)+V(N2)
ARB3
calculation
d 193 µs
f c 3 kHz
N 26.43
G fc 20 dB
ba_z^-1
U5 i 1.053 ms
f z1 200 Hz
k p 2.64
z1 s V(N1)-V(N2)
f z2 600 Hz
V(N1)+V(N2)
ARB4
ARB1
1 1 Ai 2.51m
s z2 f p1 21 kHz
G s G0 Ap k p
s s
1 1
p f p2 21 kHz
p1 2 Ad 509.6
Reference TF type 3
120 4/1/2021 Public Information
Testing PID Responses
The SIMPLIS® PID and SIMetrix® discrete version agree well with each others
Laplace type 3
(dB) SIMPLIS
SIMextrix
G f
Fs 200 kHz
Laplace type 3
(°)
SIMPLIS
SIMextrix
G f
IL
Vref k Vout
Loop delay
FB
Anti-aliasing
filter
vFB t
iL t
iout t
vPID t
vDRV t
vout t
vSW t
f c 10 kHz
GM 11 dB
Tf
Fs 250 kHz
m 60
T f
iL t
iout t
vPID t
vDRV t
vout t
vSW t
Public Information
Conclusion
To close the loop, you need a compensator
The compensator is designed to stabilize and shape the response
This filter can be implemented using an op-amp, a TL431, an OTA…
An op-amp is not a perfect element and it impacts final results
Digital control implements a discrete-time compensator
You analyse the stability of the converter in the z-domain
Simulation tools are useful to verify architectures before coding
Going from the s-domain to the z-domain warps the response
Pre-warping poles-zeroes position is the way to go
Merci !
Thank you!
Xiè-xie!