sition description

Posting title
Validation Engineer M/F
Regular/Temporary
Regular
Job description
The position holder will be joining a key team of pre- and post-silicon validation of Microprocessors and/or RF
application chipsets for consumer/industrial and space markets, within the Hardware Design Center department
of the RF Communication (RFC) division of the Microcontrollers and Digital ICs Group (also recognized for its
STM32 Microcontrollers) at STMicroelectronics, Greater Noida.
The position holder is expected to be engaged though the various validation activities including preparing
software drivers, SOC bring-up, subsystem validation and automated characterization for the target chipset,
through test strategy definition, development of measurement automation, timely execution of test plan and
detailed report documentation.
The position holder will work jointly with architects, designers and interface with clients for whom his/her
subsystem is designed.
Looking forward to enthusiastic applicants for this exciting team!
Profile
The position requires that the candidate is very familiar with digital communication principles and experienced
with C and Python programming. He/ She should be having good communication skills, willingness to join a team
working on innovative components and show curiosity to have deeper understanding of system issues. He/ She
should also be having a knack for problem solving, for performing find root-cause analysis, to be creative and
thorough.
The candidate should have good understanding / experience of:
Emulation / Silicon environments for development and debug
Debugging low level software and hardware issues
Implementing software drivers and test content
Debug interfaces like JTAG
SOC architectures and CPU
C Programming
The candidate should have working knowledge of any one of
Digital communication principles
Data converters
High-speed serial protocols
Preferably the candidate should have experience in
Measurement techniques involving oscilloscope, pattern generators, power analyzers, logic analyzer
Power and performance parameters
Validation and debug of mixed analog and digital SOC bocks
Programming in C++ or Java or Python
Minimum qualifications:
Bachelor of Technology/Engineering (B.Tech/B.E) degree (Electronics/Electrical/Computer Science streams)
from a reputed engineering college/university and a minimum of 6 years of experience.
Preferred qualifications:
Masters of Technology/Engineering (M.Tech/M.E.) degree (Electronics/Electrical/Computer Science streams)
from a reputed college/university and a minimum of 3 years of experience.

St microelectronics
Job description
The Incumbent will be responsible for Synthesis, Constraint development and Timing SignOff of products related
to Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for
futuristic cars.
Responsibilities include guiding and reviewing work done by younger engineers along with being a strong
technical contributor. This would involve strong communication and interpersonal skills , synthesizing and
reporting data to management and customer.
The job involve interactions with RTL/DFT designers to understand system and develop constraints for Synthesis
and Implementation. Candidate will be responsible for Synthesis and Timing signoff for complete SOC while
working with Implementation engineer at every stage for getting best QOR through optimum placement , CTS
and timing closure for products involving state of the Art technologies like 7nm FINFET and 28FDSOI with high
frequency and low power challenges. These SOC involve Integration of analog IPs and are Multi-supply, Multi-
mode, Multi-corner having complex multiple clock structures. Constantly challenged to meet the automotive
standards along with closing the design requirements.
Expert in developing chip constraints working with RTL and DFT teams
Strong in Reporting to management and customer
Synthesis and STA Expertise with synopsys/Cadence tools
Capable of working independently as well as technical lead
Knowledge of full RTL to GDSII flow to take timing closure from RTL to signoff
Strong communication and interpersonal skills
Should have good understanding of verilog/VHDL
Exposure to low power techniques
Knowledge of tcl and perl scripting is a must
Should have a strong sense of urgency.