ABSTRACT

Adders are important logical building elements that can be found in almost all modern electronic
devices. For the majority of applications, processing speed is critical. The propagation delay in the carry
chain is the main issue with addition. The carry chain grows in length as the length of the input operands
grows. The most efficient adder architectures for Hardware implementation are categorized as parallel
prefix adders which address the carry propagation problem in electronic systems. We have decided to
synthesize the adders for an operand bit length of 16 bits. After implementing existing parallel prefix
adders like Han-Carlson, Brent-Kung, Kogge-Stone, we assessed various parameters of the adder like
delay, power consumption, LUTs. Our goal is design a novel parallel prefix adder to improve its
performance compared to previous adders.

INTRO

VLSI system designs are made up of a variety of systems that are divided into subsystems. The data path
is one such subsystem. The data path elements are the operational units that interact to accomplish
computational processes within a microprocessor. Reading and writing to memory, arithmetic
operations, logic operations, and numerical shift operations are among these duties. Although power
reduction can be handled at any design level, it has the greatest influence at a higher level of
abstraction/algorithmic level. The researchers are primarily interested in various arithmetic algorithms
that can be used to minimize the size, enhance speed and optimize power of a DSP device. In logical
operations, addition is a crucial component. The basic goal of any design is to reduce power
consumption while improving performance. The choice of adder topology is critical to achieve
performance and reduce power dissipation. The usage of parallel prefix adders (PPAs) boosts
performance by lowering power consumption.

Parallel Prefix Adders

The parallel prefix adder employs three

stages in pre- processing stage the
generation of Propagate and
Generate signals is carried out. The
calculation of Generate (Gi) and
Propagate (Pi) are calculated when the
inputs A, B are given. As follows
Gi indicates whether the Carry is generated from that bit. Pi indicates whether Carry is propagated from
that bit. In carry generation stage of PPA, prefix graphs can be used to describe the tree structure. In
carry generation stage when two pairs of generate and propagate signals (Gm, Pm), (Gn, Pn) are given as
inputs to the carry generation stage. It computes a pair of group generates and group propagate signals
(Gm: n, Pm: n) which are calculated as follows

The final cell present in the each bit operates gives carry. The last bit carry will help to sum of the next
bit simultaneously till the last bit. The carry generate and carry propagate are given above. This carry is
used for the next bit sum operate

BRENT KUNG

A Brent–Kung adder is a parallel adder made in a regular layout with an aim of minimizing the chip area
and ease of manufacturing. The addition of n-bit number can be performed in timeO(log n) with a chip
size of area O(n log n) thus making it a good-choice adder with constraints on area and maximizing the
performance. Its symmetry and regular build structure reduces costs of production effectively and
enable it to be used in pipeline architectures. In parallel adders the critical path is decided by
computation of the carry from least significant bit (LSB) adder to the most significant bit (MSB) adder,
therefore efforts are in reducing the critical path for the carry to reach the MSB.
The Brent-Kung adder is one of the most advanced adder designs. Its performance is lower compared to
Kogge-Stone adder, but it is way easier to implement and has very less wiring congestion. It has the
lowest wiring tracks which decreases area required to implement the architecture. Moreover the
routing becomes very easy as there are very less wires running over or overlapping each other.
However, in a 16-bit adder due to the higher number of stages (seven), the growth of delay will be
higher compared to the Kogge-Stone adder. Also the fan out of this adder goes up to 4 from one dot
operator increasing the delay furthermore.

HAN CARLSON

The Han-Carlson adder is a blend of the Brent-Kung and Kogge-Stone adders. It uses one Brent-Kung
stage at the beginning followed by Kogge-Stone stages, terminating with another Brent-Kung stage to
compute the odd numbered prefixes. It provides better performance compared to Kogge-Stone for
smaller adders. The adder can achieve decent speed with comparatively less power consumption. With
well-balanced maximum fan out and number of logic levels, it is a very easy to design.
Han-Carlson adder contains a good trade-off between fan out, number of logic levels and number of
black cells. Because of this, Han-Carlson adder can achieve equal to speed execution admiration to
Kogge-Stone adder, at lower power utilization and territory.

Kogge-Stone Adder

The Kogge-Stone adder generates carry signals in O (log n) time, and is considered to be the fastest
adder. The 16-bit adder is implemented within 4 layers and has slowest growth in delay making it the
fastest class of adders. The high speed of Kogge-Stone adder is because of its minimum logic depth and
lower fan-out. Lowest fan-out compared to other algorithms reduces delay making it best suitable for
high speed industrial applications
The Kogge-Stone adder is considered to be the quickest at an industrial level. Low fan-out compared to
other algorithms reduces delay making it best suitable for rapid industrial applications. Kogge- Stone
adders occupy large area with high wiring congestion and overlapping.The number of dot operators
increases very quickly with slight increase in the number of bits. In the carry propagation stage, the
carries corresponding to each bit are provided by the carry processing stage. These bit operations are
carried out in a parallel manner. This block differentiates KSA from other adders and is the main force
behind its high performance.

Speculative adders

Speculative adders are developed with variable latency to achieve excellent performance in terms of
reduced area overhead over traditional adders by combining speculation technique with corrective
methodology. To save space, the sum and carry generating parts of speculative adders are isolated. The
Carry Speculative Adder (CSPA) employs a carry predictor circuit to reduce power consumption and
processing time, as well as an error recognition and correction circuit to locate and repair a mistake in the
partial sum generator, resulting in accurate results.