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Comparative study of power MOSFET device structures

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Indian Journal of Pure & Applied Physics
Vol. 43, December 2005, pp. 980-988

c
Comparative study of power MOSFET device structures
Rakesh Vaid & Naresh Padha
Department of Physics & Electronics, University of Jammu, Jammu, 180006

Received 19 April 2005; revised 13 October 2005; accepted 26 October 2005

In this paper, a comprehensive comparative study of various power MOSFET device structures designed and developed
s:
durin~ the past decade has been presented. Various design issues related with power MOSFET have been studied to look C
into their on-resistance (RON) versus breakdown voltage (Bv) trade off. Some of the existing power MOSFET device M
topologies have been compared with respect to their ROIVBV. The study reveals that the low-doped n epi region which gives an
square law relationship between RON and Bv in the conventional power MOSFET is being constantly engineered for
co
optimizing RON-BV trade-off subsequently led to many structural modifications in its basic design giving rise to many new
power MOSFET device structures such as SSCFET (Silicon Semiconductor Corp. FET), JBSFET (Junction barrier sa
controlled Schottky FET), superjunction (SJ)ICOOLMOS™ transistor, semi-superjunction devices and FLlMOSFET pe
(power MOSFETs with vertical floating islands) so as to overcome the conventional silicon limit.
2'
Keywords: Power MOSFET, v-groove-MOS, Vertical double-diffused MOS, Trench power MOSFET, COOLMOS™,
Vertical Floating Islands MOS (FLIMOSFET) 2.1

IPC Code: HO IL29176

trai
typ
1 Introduction biased body-to-drain junction spreads into short sur
As the power handling capability and frequency channel, resulting in breakdown at relati vely low san
response of silicon devices has improved, new voltage. Thus, the resulting device would not be gro
applications for these devices have been created. capable of handling the high voltages typical of n+ 2
During the past decade, there has been an increasing power-transistor applications. For this reason, new the
acceptance of the usage of power MOSFETs. Their structures had to be found for fabricating short- Sidf
high input impedance and excellent safe operating channel (1 to 2 urn) MOSFETs with high breakdown to (
area make them important candidates for many voltages. The basic design principle of power met;
applications. They are being used in audio/radio MOSFETs is the same as that of classical MOS difft
frequency circuits, high-frequency inverters used in transistors. The
SMPS, lamp ballasts and motor control circuits, etc'". Power MOS transistors can be classified into five simp
The low power MOSFET structure is not suitable for families:
dime
high-power applications. To appreciate this fact; (1) Structures having co-planar drain, gate and each
recal that the drain current of an n-channel MOSFET source electrodes with aluminium gate, horizontal and curre
operating in the saturation region is given by: constant doped channels or refractory gate or with prese
field plate over gate; (2) Structures having co-planar capac
electrodes and horizontal channel fabricated by the
... (1) speed
process of double diffusion (DMOS); (3) Structures cham
having non-planar electrodes and horizontal channel
It follows that to increase the current capability of with uniform doping in the channel region; i.e., source
the MOSFET, its width W should be made large and or drain on the bottom with a meshed pattern for the 'There
its channel length L should be made as small as gate; (4) Structures having non-coplanar electrodes; everyor

possible. Unfortunately, however, reducing the source and gate on top and drain on bottom, and Internal
horizontal channel fabricated by the process of double TMOS,
channel length of the standard MOSFET structure, the SIP
results in drastic reduction in its breakdown voltage. diffusion with multi-cell source configuration;
Technol
Specifically, the depletion region of the reverse- (5) Structures fabricated by chemical etching of the process
silicon; that is isotropic etching or anisotropic etching structure
known as VMOS. Most promising among these
• Fax No. +91-191-2453079, E-mail: rakeshvaid@yahoo.co.in families are:
 VAID & PADHA: COMPARATIVE STUDY OF POWER MOSFET DEVICE STRUCTURES 981

(a) The VMOS or UMOS transistors fabricated by

anisotropic etching of the silicon around the grooves;
(b) The VDMOS (TMOS, DMOS, HEXFET,
SIPMOS, TRIMOS. . .. according to the
manufacturer* concerned) fabricated by the process
of double diffusion.
There has been a trade-off in the on-resistance
(RON) and breakdown voltage (Bv) while designing
power MOSFETs and recently many power MOSFET
configurations have been used for optimizing the RON
,- Bv relationship such as Trench power'" MOSFET,
SSCFET'O•", JBSFET10,12,13,superjunction (SJ)14,20/
ed
COOLMOS™ devices, semi-superjunction" N drift
ik
ce MOSFETs, Novel high voltage sustaining structure",
es and FLIMOSFET23'25, etc. In this paper, we present a
Dr
comparative study of various power MOSFET device
w
structures and discuss their device operation and
er
.T performance with regard to RotrBv trade-off. N + substrate.
vi 2 Various Power MOSFET Device Structures drain
2.1 VMOS transistor (V groove) Fig. 1-Schematic design of a V-groove MOSFET (VMOSFET).
Fig. 1 shows a section of the VMOS or (V groove) Structure shown represents one cell of the device
transistor. It is produced from silicon epilayer of the
type n' «: with a p-Iayer diffused throughout the mobility is lower than VDMOS. Since the V groove is
short surface. Diffusion zones n' are also carried out in the formed by chemical etching process, which leaves
.y low same window. The silicon is chemically attacked and many sodium ions on the etched surface whose
lot be grooves (V's) are opened in the middle of the diffused presence creates a lot of reliability problems, so that
cal of n: zones. This V formation is obtained by etching of the VMOS devices are not used presently'".
I, new
the silicon through windows in an oxide by hydrazine. 2.2 VDMOS transistor
short- Sides of V are thermally oxidized and then metallized At present, the most popular structure for a power
kdown to constitute the gate. The source contact is also MOSFET is the vertical double-diffused (VDMOS)
power metallized, which short-circuit in the n and p" transistor as shown in Fig. 2. It starts with a heavily
MOS diffusions. The drain is on the lower side 'bf device. doped n-type substrate in order to minimize bulk
The advantage of this type of transistor is its portion of the channel resistance. An n' epi layer is
to five simplicity and the precise control of its geometric grown on it and two successive diffusions are made, a
dimensions, in particular, the channel length. Finally, p-zone in which proper bias will generate the channel
:e and each groove produces two channels, doubling the and an n' into it defining the source. Next the thin,
tal and current capability and reducing the surface area. The high quality gate oxide is grown followed by the
r with presence of the n drift zone gives a high voltage phosphorous-doped polysilicon thus forming the gate.
planar capacity. These transistors have good switching Contact windows are opened on top defining the
by the speeds and can operate in the VHF range. In VMOS, source and the gate terminals while the whole bottom
ictures channel is formed on {Ill} plane, so, its surface of the wafer makes the drain contact. With no gate
hannel bias, the n + source and n + drain are separated by
source p-zone and no current flows (transistor is turned-off).
'or the 'There are many power MOSFET manufacturers and almost With a positive gate bias, the minority carriers in the
rodes; everyone has his own process optimization and trade name. p-zone (electrons) are attracted to the surface
1, and International Rectifier pioneered the HEXFET, Motorola builds
underneath the gate plate. As the bias increases more
louble TMOS, Lxys fabricates HiPerFETs and MegaMOS; Siemens has
the SIPMOS family of power transistors and Advanced Power electrons are being confined to this small space, the
ration; Technology, the Power MOS IV, to name a few. Whether the local minority concentration becomes larger than the
of the process is called VMOS, TMOS or DMOS it has a horizontal gate hole (P) concentration and inversion occurs. Now an n
tching structure and vertical current flow past the gate.
channel is formed in the p material right under the
these
982 INDIAN J PURE & APPL PHYS, VOL 43, DECEMBER 2005
SOlUTe
+ Pbase
P region
N buffer layer
N+substrate
Fig. 2 - Schematic design of a VDMOSFET (DMOS) transistor.
Structure shown represents half cell of the device
gate structure connecting the source to the drain and
current can now flow. The gate bias controls the flow
of current between source and the drain 1.3.
The power MOSFET is nothing but a structure
containing a multitude of cells like the one described
in Fig. 2 connected in parallel. And, like any
paralleling. f.. identical resistors, the equivalent
resistance is .L/n-th. of the single cell's RDS(ON)' The
larger the die, the lower is its on-resistance but at the
same time larger parasitic capacitances and therefore,
the poor switching performance. For example,
Intersil" power MOSFETs of 120-mif chip contains
about 5,000 cells; a 240-mie chip has more than
25,000 cells.
2.3 Trench power MOSFET
About five years ago, the power MOSFET industry
shifted to trench-gate technology'" to reduce the on-
resistance. In the trench-gate structure (see Fig. 3),
commonly referred to as the UMOSFET, the chaimel.
is formed on the vertical sidewalls of a trench etched '1
. into the silicon surface. Because the drain-source
current is directed along a vertical path, the JFET
resistance is eliminated. This allows reduction of the
on-resistance not only, b),' removal" of one of the
resistance components.lbur'also by allowing a smaller
cell" I'size, which increases the channel 'density.
Unfortunately, the trench-gate process' is, .
.o
more
<,s.:
SOlUTe
"
1
1
t
N-(hift
N substrate
drain
Fig. 3-Schematic design of a Trench gate MOSFET (UMOSFET)
transistor. Structure shown represents half cell of the device
t
s
expensive when compared to the planar DMOS t
process. The industry has also to deal with reliability r-
problems associated with high electric fields at the c
trench corners, which must be solved by rounding the
trench corners and buffering the electric field 'using
the p' regions. Further, the extension of the gate into
the drift region increases the coupling between the
drain and the gate leading to higher Miller
capacitance and gate charge, which can adversely
affect switching performance. Trench MOSFET is
like VMOS, but its groove is made perpendicular to
the surface, so that channel is formed on {1l0}
plane". The presence of sharp edges affects the device
breakdown, so it is used only for low voltage, high
current applications. The trench technology has the
advantage of higher cell density but is more difficult
to manufacture than the planar device.
2.4 SSCFET and JBSFET
The planar power MOSFET structure has been re-
engineered'? by Silicon Semiconductor Corp, USA, to
achieve performance superior to those of state-of-art
trench devices. By retaining a planar architecture, the
fabrication process remains compatible with
mainstream CMOS process lines and reliability issues
are ameliorated. In addition, this architecture has
allowed implementation of a silicided gate stack to
reduce''the internal gate resistance of the MOSFET.
 VAID & PADHA: COMPARATIVE STUDY OF POWER MOSFETDEVICE STRUCTURES 983

The SSCFETIO (Silicon Semiconductor Corp. FET)
structure (see Fig. 4) contains a deep p" region that is
self-aligned to the gate region II. Its higher doping
concentration and deeper extension in both the
vertical and lateral directions are used to create a
potential barrier in the transition region, which is
located below the gate region. The gate width and
transition region doping profile are optimized to
obtain enhanced power MOSFET performance. The
screening of the gate region at B (Fig. 4) from the
drain potential allows shortening of the channel
length, without fear of reach-through-induced
breakdown, to reduce its resistance contribution. The
channel contribution decreases to half that observed in
typical VDMOSFETs, enabling specific on-
resistances for SSCFETs to approach those obtained
in typical trench power MOSFETs.
Another new power MOSFET cell structure has
been created called JBSFETIO (Junction barrier
~T) controlled Schottky FET) (see Fig. 5) that integrates
the Schottky diode into the power MOSFET. In this
structure, the Schottky diode is formed by making a
OS break in the p-base and the p + shielding regions. The
p + shielding region located below the Schottky
lity
the contact produces a junction barrier at C (Fig. 5) that
the
.ing
into
SSCf£T stfUdurl
the
iller
Source
sely
[' is
T to
1O}
vice·
high
the
icult
protects the Schottky contact from the drain potential.
This design suppresses the well-known Schottky
barrier-lowering phenomenon that leads to a rapid
(typically 10 times) increase in leakage current with
increasing reverse bias". The junction barrier concept
was first proposed and applied to improving the
performance of Schottky rectifiers'j'". In the
JBSFET, the same v' shielding region used for
achieving the channel length reduction in the
MOSFET, is simultaneously used to shield the
Schottky contact with no additional process steps.
Due to a high level of integration, the Schottky region
has sufficient area to handle the full current rating of
the MOSFET. The JBSFETs offer on-resistances that
are competitive with trench MOSFETs in equivalent
packages while providing the added benefit of
including the Schottky diode. This has been found to
result in significantly higher efficiency (two to eight
percentage points) in the de-de converter operating at
200 kHz to more than 1 MHz.
2.5 Superjunction (SJ)I COOLMOS™ transistors
Recently, the invention of superjunction'V" (SJ
MOSFET)ICOOLMOS™ have made it possible 'to
attain higher speeds and larger breakdown voltages
simultaneously. The structure of the superjunction

1 re-
\., to
f-art
, the
with
••• trate
.sues
has
.k to
PET. Dram
Fig. 4 - SSCFET device structure
984 INDIAN J PURE & APPL PHYS, VOL 43, DECEMBER 2005

Fig. 5 - JSBFET device structure

principle of charge compensation, which has been

Source
derived from the lateral RESURF (reduced surface
field) idea. The doping level of n pillars can be greater
than that of the conventional power MOSFETs and
the excess charge in the n.pillar can be counter
balanced by the adjacent charges in the p pillar, thus
contributing to a horizontal electrical field without
affecting its vertical field distribution. Accordingly,
SJ MOSFET concept can realize very low on-
resistance by increasing the aspect ratio of nand p
pillars because the negative and positive charges in
each pillar can easily compensate each other to allow
N' sub increase in their doping concentration 14. However, in
reality, the superjunction structure has the following
Drain difficulties:
(1) The charge must be strictly controlled in the
Fig. 6 - Schematic design of COOLMOS ™ transistor based on
superjunction concept. Structure shown represents one cell of the pillars; otherwise the breakdown voltage decreases
device rapidly; (2) Deep doping into bulk to make pillars is
required to minimize the number of iteration
(SJ) COOLMOS™ shown in Fig. 6 is fairly complex processes; (3) As the total imbalanced charge
and different from the conventional MOS structure increases with pillar depth, the realization of high
because of the existence of superjunction drift layer. voltage devices becomes increasingly difficult; (4) In
In these devices!"!", a superjunction composed of p addition, it is very difficult to make deep implantation
and n pillars, which share vertical boundaries, due to crystalline damage caused by high-energy
replaces the drift layer. This modification causes a implants. Recently, a 600 V superjunction power
noticeable change in the electric field profile within MOSFET has been introduced commercially by the
the device, thereby resulting in large breakdown Infineon Technologies" SPP20N60S5 having RON
voltage. The superjunction devices are based on the equal to 0.19 Q em",
 VAID & PADHA: COMPARATIVE STUDY OF POWER MOSFET DEVICE STRUCTURES 985

2.6 Semi-superjunction MOSFET attractive23-25.These new vertical MOSFET structures

The difficulties associated with the superjunction are based on the FLI-diode concept. It has been
(SJ) MOSFET led to the design concept of the semi- shown" that conventional silicon limit can be
superjunctiorr" (SJ) MOSFET in which an optimized overcome by using this concept which states that the
n-type layer is connected to the bottom of the SJ triangular electric field distribution in the bulk is
structure as shown in Fig. 7. This n-drift layer is also divided into several sections to decrease the
known as bottom assist layer (BAL). The important magnitude of the peak electric field by inserting
design parameters in the semi -SJ structure are the electrically vertical floating p + buried layer in the n'
BAL doping concentration and thickness. It has been drift region as indicated in Fig. 8. The p' floating
shown that the semi-SJ MOSFET with the aspect layer increases the development of depletion layer due
ratio of four has the same on-resistance as the SJ- to a mechanism similar to the p-guard rings in planar
MOSFET with the aspect ratio of five thus terminations. With this mechanism, the doping
eliminating one turn of the epitaxial growth process. concentration of the n- drift region can be enhanced
The on-resistance Ron Semi.SJ and breakdown voltage Bv and hence the on-resistance can be reduced by a factor
Semi.SJ are given by: equivalent to the enhancement in doping
concentration of the drift region. The FLIMOSFET
Ron Semi·SJ =RSJ+ RBAL ... (2) structure has a distinct advantage over the SJ structure
on boron implantation dose control for the p+ floating
BVSemi.SJ= BVSJ + BVBAL ... (3) layer. As the reverse bias is increased, the space
It has been reported" that the on-resistance of the charge region extends from the p-base region towards
fabricated semi-SJ MOSFET is equal to 54 mQ-cm2 the floating island in the upper drift region. When this
at breakdown voltage of 690 V, which is 28% lower upper drift region is entirely depleted, then the space
than the conventional SJ-MOSFET of the same charge starts to extend from the bottom of the floating
~n
dimensions. island towards the drain of the FLIMOSFET in the
::e lower drift region. Thus, two electric field
er 2.7 FLIMOSFET (Power MOSFET with vertical floating distributions, each of triangular shape are formed at
ld islands)
both upper and lower drift regions, as shown in Fig.
er Another class of devices reported in the literature
8(c). In contrast, a single electric field distribution is
us for RowBv optimization are the high voltage
formed in case of conventional power MOSFET
ut sustaining structures22-25 and among these, devices
structure, also shown in Fig. 8(c). Therefore, a
ly, with vertical floating islands in the conventional
number of consecutive vertical floating islands (FLIs)
In- power MOSFET known as FLIMOSFET are very
are used to satisfy the desired device performance by
p
keeping the peak electric field below the critical
m Source source
electric field. In this way, the breakdown voltage of
)W
the device can be improved. From this, if we assume
III
that critical electric field is constant and the current
ng path (which is narrowed by inserting the floating
Electric Field
islands) does not affect the on-resistance, then the Bv
he H
and RoN,sp become (n+ 1) times larger than that of the
.es BV
SJ conventional power MOSFET, where n is the number
IS
of floating islands. In other words, RoN,sp becomes
on proportional to B», rather than B/ as in case of
'ge n-BAL conventional power MOSFET structure.
gh (Bot/om. Assist Layer)
In 3 On-resistance versus Breakdown Voltage and its
.on N' ~u••
Improvement
Depth
vs Drain
The on-resistance of a power MOSFET is the total
ver resistance between the source' and drain terminal in
the the on-state and can be expressed as a series
Fig. 7 - Schematic design of serni-superjunction transistor along
?ON with its electric field distribution. Structure shown represents one
combination of several resistance elements26-28 given
cell of the device. by:
986 INDIAN J PURE & APPL PHYS, VOL 43, DECEMBER 2005
Gate
11- Drift
Region
VDMOS Conventiona.l
(a)
Fig. 8 - Figure explaining FLI-diode concept (a) A conventional VD~OSFET structure (b) FLIMOSFET with the induction of one
floating island (c) Explanation of electric field reduction mechanism
where Rsource is the resistance of the n + source
diffusion, Rch the channel resistance, RA the
accumulation layer resistance, RJ the contribution
from the drift region between the p-base regions, Ro
the drift region resistance and RSUB is the substrate
resistance. Rwcml is equal to the sum of bond wire
resistance, the contact resistance between the source
and drain metallization, the silicon metallization and
the lead frame contribution. These are normally
negligible in high voltage devices but can become
significant in low voltage devices. Wafers with
substrate resistivities of up to 20 mfz-cm are used for
high voltage devices and less than Smn-cm for low
voltage devices.
The contribution from the channel can be
minimized by taking the channel length small and
keeping its width large. Channel resistance can also
be reduced by decreasing the gate oxide thickness
while maintaining the gate derive voltage. The
accumulation resistance can be reduced by decreasing
the length of the gate electrode between the cells. The
specific on-resistance of the power MOSFET will
then be determined mainly by the drift region. At
lower voltages, Ros (on) is dominated by the channel
resistance and the contributions from the metal to
semiconductor contact, metallization, bond wires and
lead frame. The Miller capacitance in the
Gate
n. Drift
p+ Region
Drain
FUMOS with one p+ Island x
(c)
(b)
VDMOSFET can be reduced by decreasing the space
• 10
between the p-base regIOns .
... (4) The breakdown voltage of a power MOSFET
together with its maximum current handling
capability determines its power rating. Therefore, the
structure of a power MOSFET should be designed in
such a way to maximize its power handling capacity
and breakdown voltage (Bv). The condition for carrier
generation with a uniform electric field E is given by:
w
f adx = 1 ... (S)
o
where, a = ae-blE is the impact ionization coefficient,
defined as the number of carrier pairs generated by a
single carrier traversing unit distance through electric
field E. The parameters, a and b, are constants
specific to electrons and holes. The integration is done
over the width of the region W. However, since the
major contribution to the integral comes from the
regions of highest field, an approximation that there
exists a certain field, called the critical field (Ec) at
which breakdown starts can be considered constant
for simplifying the analysis. For an abrupt p+n
junction, the depletion region extends almost fully to
the n-side. The maximum field, for a given voltage
(VA) across this junction is then given by,
EM -_~qNDV A ... (6)
Es
 VAID & PADHA: COMPARATIVE STUDY OF POWER MOSFET DEVICE STRUCTURES 987

where, q is the electron charge, and No is the doping O.-resistuu:e ""t'SUS BreakUwaV.ltqe (V)

concentration on the n-side.

Eq. (6) implies that lower the doping concentration
0.1
on the n-side, lower is the peak field in the junction.
For a given breakdown voltage Bv, to be attained by
the device, critical field Ec, taken to be constant, and 0.001

the optimum width of the drift region (W) preventing N

punch-through, one gets the optimum doping No as: e I

1.10-3

a
EE '-'
N o=~
2
... (7) =
Ill: 1·10
-4

2qBv
-5
Since the resistance of the drift region is 1·10

proportional to WMo, we get:

-6
1·10
W 100 1000
RON =-- qf.1,ND
... (8) Breakdown Voltage (V)
-- Siliconlimit(conven) • COOLMOS 600 Volt •
• <2>-. S) MOSFET d-5micron • Semi-S) MOSFET
ne By choosing the appropriate values for E; and f.1, for 8B FUMOSFET n-6

n-type silicon, we can obtain the conventional silicon Fig. 9 - On-resistance versus breakdown voltage comparison for
limit equation as: various power MOSFET devices based on analytical data
pace
RON = 8.3xl0-9 X Bv2.S Q em' ... (9) optimization. The square law relationship between
FET
RotvBv in the conventional power MOSFET led to
iling This square law is the major hurdle in designing
many structural modifications in its basic design
, the power MOSFETs for higher breakdown voltages and
giving rise to many new power MOSFET device
xl in has been shown to become linear for SJ29 MOSFET
structures such as SSCFET, JBSFET,
acity and is given by:
superjunctionlCOOLMOS™ transistor, semi-
irner 5 superjunction and FLIMOSFET.
I by:
RON-Sf = 1.98 X 10-1 x i4 x e; Q ern' ... (10)
Acknowledgement
where d is the thickness of the p or n pillar in the One of the authors (RV) gratefully acknowledges
..(5) Prof S K Khosa, Head, Department of Physics &
superjunction structure. Similarly, the relationship"
for FLIMOSFET has been given by: Electronics, University of Jammu, Jammu, for his
.ient, constant encouragement throughout this work and the
by a RON-FLI = 2.3 X 10-8 x B/5 x (n + 1)-1.5 Q em' ... (11) University Grants Commission (UGC), Govt. of
.ctric India, India, for the award of Teacher Fellowship
where n is the number of floating islands in the under the FIP scheme during the io" plan period .
.tants
device.
done References
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