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    Dice Game Controller

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    EADALADA LAVANYA
    This document describes a dice game module in Verilog. It contains: 1) A dicegame module that simulates rolling dice and determining if the player wins, loses or continues rolling based on the dice sum. 2) A gametest module that triggers rolls of the dice by calling the dicegame module and resets after each game. 3) A test_tester module that instantiates the dicegame and gametest modules and provides a clock signal to run the simulation.

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    Dice Game Controller

    Uploaded by

    EADALADA LAVANYA
    45 views8 pages
    This document describes a dice game module in Verilog. It contains: 1) A dicegame module that simulates rolling dice and determining if the player wins, loses or continues rolling based on the dice sum. 2) A gametest module that triggers rolls of the dice by calling the dicegame module and resets after each game. 3) A test_tester module that instantiates the dicegame and gametest modules and provides a clock signal to run the simulation.

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    dice game controller

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    This document describes a dice game module in Verilog. It contains: 1) A dicegame module that simulates rolling dice and determining if the player wins, loses or continues rolling based on the dice sum. 2) A gametest module that triggers rolls of the dice by calling the dicegame module and resets after each game. 3) A test_tester module that instantiates the dicegame and gametest modules and provides a clock signal to run the simulation.

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    © All Rights Reserved
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    45 views8 pages

    Dice Game Controller

    Uploaded by

    EADALADA LAVANYA
    This document describes a dice game module in Verilog. It contains: 1) A dicegame module that simulates rolling dice and determining if the player wins, loses or continues rolling based on the dice sum. 2) A gametest module that triggers rolls of the dice by calling the dicegame module and resets after each game. 3) A test_tester module that instantiates the dicegame and gametest modules and provides a clock signal to run the simulation.

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    © All Rights Reserved
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    of 8

    module dicegame(rb,reset,clk,sum,roll,win,lose);

    input rb,reset,clk;
    input [3:0]sum;
    output reg roll,win,lose;
    reg [2:0]state,nextstate;
    reg [3:0]point;
    reg sp;
    initial begin
    state=0;nextstate=0;
    point=2;
    end

    always@(rb,reset,sum,state)
    begin
    sp=1'b0;
    roll=1'b0;
    win=1'b0;
    lose=1'b0;
    nextstate=0;
    case(state)
    0: begin if(rb==1)
    nextstate=1;
    end
    1: begin
    if(rb==1) roll=1'b1;
    else if((sum==7)|(sum==11))
    nextstate=2;
    else if((sum==2)|(sum==3)|(sum==12))
    nextstate=3;
    else
    begin
    sp=1'b1;
    nextstate=4;
    end
    end
    2: begin
    win=1'b1;
    if(reset==1)
    nextstate=0;
    end
    3: begin
    lose=1'b1;
    if(reset==1)
    nextstate=0;
    end
    4: begin
    if(rb==1)
    nextstate=5;
    end
    5: begin
    if(rb==1)
    roll=1'b1;
    else if(sum==point)
    nextstate=2;
    else if(sum==7)
    nextstate=3;
    else
    nextstate=4;
    end
    endcase
    end

    always@(posedge clk)
    begin
    if(clk)
    state<=nextstate;
    if(sp==1)
    point<=sum;
    end
    initial $monitor($time, " sum=%d, win=%b,lose=%b,point=
    %d",sum,win,lose,point);
    endmodule
    `timescale 1ns / 1ps

    module gametest(rb,reset,sum,clk,roll,win,lose);

    output reg rb,reset;

    output reg [3:0] sum;

    input clk;

    input roll,win,lose;

    reg[1:0] tstate,tnext;

    reg trig1;

    integer i;

    integer sumarray[0:11];

    initial begin

    sumarray[0]=7;

    sumarray[1]=11;

    sumarray[2]=2;

    sumarray[3]=4;

    sumarray[4]=7;

    sumarray[5]=5;

    sumarray[6]=6;

    sumarray[7]=7;

    sumarray[8]=6;

    sumarray[9]=8;

    sumarray[10]=9;

    sumarray[11]=6;

    i=0;tstate=0;tnext=0;trig1=0;

    end

    always@(roll,win,lose,tstate)
    begin

    case(tstate)

    0: begin

    rb=1'b1;

    reset=1'b0;

    if(i>=12)

    tnext=3;

    else if(roll==1'b1)

    begin

    sum=sumarray[i];

    i=i+1;

    tnext=1;

    end

    end

    1: begin

    rb=1'b0;

    tnext=2;

    end

    2: begin

    tnext=0;

    trig1=~trig1;

    if((win|lose) ==1'b1) reset=1'b1;

    end

    3: begin

    end

    endcase

    end

    always@(posedge clk)
    begin

    tstate=tnext;

    end

    endmodule
    `timescale 1ns / 1ps

    module test_tester();

    wire rb1,reset1;

    reg clk1;

    wire roll1,win1,lose1;

    wire [3:0] sum1;

    initial begin

    clk1=0;

    end

    always #20 clk1<=~clk1;

    dicegame d1(rb1,reset1,clk1,sum1,roll1,win1,lose1);

    gametest g1(rb1,reset1,sum1,clk1,roll1,win1,lose1);

    endmodule

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