Reg.

No:

17750E,404

FOIJR YEAR B.TECH DEGREE EXAMINATION-AUGIJST, 2O2I

SEVENTH SEMESTER EXAMINATION
VLSI SIGNAL PROCESSING (VS)
(Scheme -2017)
OPtrN ELECTIVE

Time : 3 Hours Max. Marks : 60

Note : Answer Question Nol. and any One Question from each Unit.
All Questions Carry Equal Marks

1. Answer the following Questions (2X5:10)

a) Write equation for one dimensional discrete wavelet transform

b) Define Loop ,Path and Cycle
c) Write equation for the power consumption of pipelined filter
d) Write two basic steps in Unfolding algorithm
e) Define iteration vector , edge mapping, reduced dependence graph

TINIT - I

2. a) Design system level diagram of the LMS adaptive filter. (s)

b) Why VLSI Signal processors require Scaling in CMOS explain with (5)
lT-DRAM cell
OR
3. a) What are the noble identities for multirate systems (5)
(Note: Decimator and Expander are the references)
b) Represent DFG,SFG,DG and BD for 3tap FIR filter. (s)
LINIT - II
4. a) Find T.. for the DFG shown in Figure 4.1 (s)
(u (?)
(i r;\ ,'l\
\\--rLff,
J; '\*"/ ttl
dt

,1-
^ts"
rt r-\
- { l'<**
\r/
l)
\#

{11
f igure 4.1

b) Write an algorithm for constructing equivalent SRDFG from an MRDFG (s)

P.T.O
 OR

5. Discuss any two algorithms for computing Iteration bound for the given ( l0 )
DFG.

LNIT - III
6. a) Design fine grain pipeline architecture for FIR filter with Tm:l8 units and ( 5)
Ta:2 units.
b) Derive power consumption for Pipelining and what is the importance of ' ( s)
FVo' in the power consumption.
OR
7. a) Design feed forward cutest for FIR filter with Tm:10 units and Ta:6 ( s)
units.
b) Design High Performance 3-tap FIR filter using parallel processing ( s)
TINIT - IV
8. a) Prove i) w,(p):w(p)+r(Vr)- r(Vo) (s)
ii) retiming does not alter the iteration bound of DFG
b) Prove "unfolding preserves the number of delays in a DFG' and any 2- (5)
folding transformation properti es.
(Hint: Assume your own example)
OR
9. a) For the original DFG given in Figure 9.1 design 2-unfolded DFG with (s)
iteration bound and sample period.

Figure 9.1

b) Prove "adding the constant value j to the retiming value of each node does (s)
not change the mapping from G to G'."

LINIT -V
10. a) Design F, Design Rl for FIR systolic arrays. (5)
b) Design mapping methodology to accommodate delay elements in the space (s)
representation(Hint: [Jse single cell DG).
OR
11. a)' Design R2 and Dual R2, Design Rl for FIR systolic arrays. (s)
b) Briefly explain i) Matrix-Matrix Multiplication 1i) 2D Systolic anay design. (s)