2.

BEOL

Before moving to chapter 2, I will quickly summarize what we have seen in the first chapter.
1. We discussed about what will be covered in this course
Major focus on various processes involved in fabrication along with testing and yield of chip and, various tools used in semiconductor
industries
2. Why we use Si as a substrate in semiconductor industries
It is cheap, easily available, forms SiO2 on surface which act as a protecting layer, relatively high thermal stability, higher reverse breakdown
voltage. We have also discussed why semiconductor is being used over conductor and insulator.
3. We use Si in the form of wafers. All the components and connections are made on the top of Si wafer
4. What are the two major processing steps: Back end of the line (BEOL) and Front end of the line(FEOL). Making of active devices such as
transistors come under FEOL while connecting the active devices i.e. wiring come under BEOL
5. We have also seen the functions of transistors i.e it can act as an amplifier and switch (ON and OFF state). We will see the transistors making
and their working principle more in chapter 6
6. Also, I discussed what are the major processes being employed in FEOL and BEOL. We haven’t discuss the details of these processes yet which I
will do in the subsequent chapters.
There are few points which I missed to explain in first chapter which I will discuss now.
Firstly, I mentioned about Fab. Fab refers the industries which fabricate the chips. Sometimes it is also called foundry. On the other hand, Fabless
refers the industries which only design the chip (electrical design of the circuit) and sell the hardware part. They wont involve in fabrication
process.
Some of the major foundries ( make and sell chips on a commercial scale) in the world:
1.Intel, USA
2.Hynix, S. Korea
3.Samsung, S. Korea
4.Global foundries, Germany
5.TSMC, Taiwan
6.USJC, Japan
7.ST microelectronics, Singapore and So on
Chemical engineers are being placed in these companies with a good package.
If you see above, you may observed that India don’t have any fab. The major reason is that huge capital investment is required along with
uninterrupted power and water supply for setting up a new plant. However India has fabless industries such as semiconductor India Pvt Ltd, IBM
Global service India Pvt LTd etc. Though ISRO has small scale fab, they fabricate chips for some applications. They don’t fabricate on a larger scale
for electronic gadgets.
It is also to be noted, that the processes which we are discussing here not only used in semiconductor industries, but also in making MEMS
devices (micro-electromechanical system), fabrication of biosensor etc. MEMS devices basically consist of both mechanical and electrical
components. It has wide spread applications in automotive, electronics, medical, communications industries and in defence.

1
 Electrical Design

BEOL – connecting devices

using wires (metal)
Physical Layout

Device 1 Device 2Device 3Device

Creating Chip
Silicon Wafer

FEOL
Testing

Now, move onto chapter – 2 BEOL.

In the last chapter , we discussed ,there are four major steps in chip fabrication. The
same is also shown here. Among these, we will be focusing on creating chips.
Again in creating chips, there are two major processing steps (1) FEOL – making active
devices and then BEOL (connecting the devices by metal wire).
Although, the first step is FEOL, we will discuss BEOL first as it is relatively easy to
understand.
Regarding Picture: Blue – Si substrate ; Green – Devices such as transistors, Brown –
connecting wires, Grey- insulator such as SiO2. Insulators needs to be placed between
devices and between wires, to prevent short circuiting.

Connecting wires is referred as metal interconnects/ interconnects. So hereafter, I use

the word “interconnects”

2
  Why BEOL is important?
 Al vs Cu technology
▪ Properties of interest
▪ Why Al was used ?
▪ From Al to Cu technology
▪ Issues in Cu technology
▪ How we overcame these issues
 Process flow
▪ Al
▪ Cu
 Integration issues
3

The topics that will be discussed in this chapter.

3
  For older generation, FEOL decides the speed
of the chip and BEOL influences the yield of
chip.
▪ Transistors has to switch fast
▪ Many layers in BEOL – more likely to fail

 In new generation, BEOL also affects speed

of the chip
▪ Signal has to go through interconnect metal
4

One may think, why BEOL is important as we are having active devices such a
transistors are made during FEOL and BEOL is just about connecting the devices? In
previous generation also, people are striving towards increasing the speed of the
device. If we want to increase the device speed, the transistor has to switch ON and
switch OFF quickly i.e. the transition b/w these two states must be quick. However,
these are coming under FEOL. BEOL is important only from yield point of view. Yield
means, out of total chips made, how many chips going to perform well. For example,
if only 7 chips perform well out of 10 chips, then yield will be 70%. As many
steps/processes (most of them are very sensitive to lot of factors) are involved in
making a chip and also, the device size is continuously shrinking, the chances of
failure is more in semiconductor industries. We will be discussing Yield in detail in
chapter 11.

So, as I told , in previous generation BEOL is important only from the yield point of
view. Because, the chance of failure is more in BEOL than in FEOL. Because, active
devices are present in a single layer while connecting wires are made in many layers
(4-15 layers). So chance of failure is more in BEOL.

But why multilevel metal layers are used instead of single layer which we will see
later in this chapter.

But in new generation, as the device size shrinking continuously, transistor size also

4
becomes small and thus the speed of the device is enhanced. For example, the device
speed is increased from 100 MHz (during 90’s) to 3 GHz (currently). Speed of the
transistor is mainly depend on Gate length (we will see this in chapter 6). As
transistor size decreases, the Gate length also decreases and eventually the chip
speed increases. As manufacturing process is available for making a small transistor,
this is not an issue.

But in newer generation, BEOL is also important from speed point of view. Even
though, the transistors are working fast, the signal has to go from one transistor to
the other through interconnect metals. This is trivial when transistor speed is low.
But, now a days, as we could make high speed transistors, we have to focus on BEOL
as well to increase the device speed.

So, BEOL is also important from speed point of view in the current generation.

4
 ❑The metal layers are names as M1, M2, M3 and so on…
❑M1 thickness is smaller (200 nm)- Local interconnects –
between cells
❑M2, M3 interconnects are slightly larger (250 nm) – Global
interconnects – between blocks
❑Last one must be large (450 nm) – for power distribution
❑ Has to carry large current. To reduce the resistance, the
width has to be higher.

In this slide, we will see more about metal interconnects.

In semiconductor industry, the metal layers are named as M1, M2 and so on by

convention. Usually in integrated chips, the metal layer varies from 4 to 15. If the
circuit design is complex, then we need more metal layers so that the chip could be
fabricated in minimal area. It is must that the chip area should be smaller because it
affects the cost of chip.

Based on dimension, metal layers are classified as Local interconnects and Global
interconnects. If metal layers are more, then we may have intermediate
interconnects.

Local interconnects are connecting the nearby active devices. It runs for shorter
distance. So its thickness is also lower. On the other hand, global interconnects are
run for longer distance and its thickness are slightly higher as shown in the slide.
Because resistance increases as you increase the length. To compensate that, we
have to increase the thickness of the interconnect. Global interconnects are for
connecting the devices b/w different blocks. The last metal layer is for power
distribution so the width and thickness should be larger.

5
 Ref: http://www2.isu.edu.tw/upload/341/7/files/dept_7_lv_2_31755.pdf
6

This slide shows the local and global interconnects. As you see, the length of global
interconnects (yellow) are long compared to that of local interconnects(pink).

6
 7

The horizontal structure (named as metal 1 and metal 2 are interconnects). The
vertical structure (black color) are called as contact or via.

Contact : connection b/w FEOL and first metal layer

Via: connection b/w first layer and second layer, second layer and third layer and so
on.

7
  Resistivity – should be low
 Melting point – should be high
 Thermal expansion coefficient – mismatch
with other materials in use should be low
 Diffusivity in SiO2 – Should be low
 Adhesion to the insulator – should be better

Metal Resistivity, µ ohm - cm Melting point, °C

Cu 1.7 -2.0 660
Al 2.7-3.0 1084
W 8-15 3410
8

So far, we discussed about interconnects. what is the material used for making
interconnects? We will discuss this now.

As BEOL also affects device performance, we have to chose a right material

(conductor) for making interconnects. As the signal has to go from one end to the
other, the material should be obviously a conductor. As you know, metals are good
conductors of electricity. Thus, metals are used for making interconnects. As many
metals are available, we have to chose the suitable one. So, the resistivity value of the
metal should be lower. But, what are the other properties we are looking for in the
metal?

When we are making many metal interconnects, insulator should be deposited b/w
them to prevent short circuiting i.e. one metal line should not touch the other one.
Thus, diffusion of metal to the insulator (normally SiO2 is used) should be low. As the
concentration of metal atoms is higher in metal side while the concentration is zero in
the insulator side. Thus, the metal atoms will diffuse from metals to insulator. This
diffusion rate should be lower. Also, when we are depositing SiO2 b/w two metal
layers, metal should adhered well to the insulator. If it is peeled off, then it won’t
serve the purpose.

As we are using chips at different locations, temperature fluctuations will be there. So

materials will expand /contract depending on the temperature. As we are using many
materials in the chip (Si – semiconductor, SiO2 – insulator, Metal- conductor), the

8
mismatch of thermal expansion coefficient of metal layer with other materials should
be lower.

The values of resistivity and m.p is given for some of the metals which are explored
by semiconductor industries for interconnects is given in the slide.

8
  Cu is widely used now [in 1997, IBM
introduced chips with copper interconnects*]
 Al – Previously

Metal Metal

via via via

*Ref: http://www-03.ibm.com/ibm/history/ibm100/us/en/icons/copperchip/

In the last slide, we have seen the properties of interest for metal interconnects.
Based on it, Al was chosen initially and then we moved to Cu.

Why Al was used initially and why we moved from Al to Cu which we will see in the
next couple of slides.

Regarding Picture: grey – SiO2 .

9
  Al – W process to make interconnect is more
easier than Cu.
 Mechanical properties of Al is compatible
with Si
 Al has high melting point
 Mismatch of CTE b/w Al and Si is lower
 Does not contaminate Si

10

Why Al is used initially?

Although Al resistivity value is higher compared to Cu, when considering other

properties(read this slide for understanding), Al is a better choice for interconnects.

10
  Cu is widely used now [ Al – Previously]

11

But later we moved from Al to Cu.

Currently, we are using Cu only although continuous research on exploration of
possibility of using other metals as interconnects is going on.

Why we moved from Al to Cu? Before addressing this question, first we will see how
device size is continuously shrinking with years?

This plot is given for various units such as DRAM- dynamic random access memory,
MPU (memory protection unit) gate length, print gate length. The trend for all the
units are almost same (slope is ~ 12-13%) . During 60’s, the device length is 25000
nm, in 90’s the device size is shrink to 800-900 nm and currently, it is in the range of
10 nm. However, in this plot, you could see only till 2014.

So, from this plot, it is clearly observed that the device size is continuously shrinking.

But , how does it affect BEOL performance? We will see in next slide.

11
 12

The signal from one device to other has to go through metal interconnects. How fast
it will go? We can quantitatively measure this and call it as RC delay. If the RC delay is
low, the signal will go fast. How to calculate RC delay. The equation is given in the
next slide. Before this, see this plot. Just focus on Pink line (Al is used as interconnect,
SiO2 is used as insulator) and blue line (Cu as an interconnect and low dielectric
material in the place of insulator). This plot is given for how RC delay is changing with
device size. Below 0.18 micrometer (left to green line), the difference in delay b/w
Cu-low K interconnect and Al –SiO2 is not significant. However, the difference is
significant for lower device sizes (right to green line). Especially below 0.18 micron
size, we have to shift to Cu technology to improve the speed of the chip.

In summary, we have seen the device size is shrinking with years and when the device
size decreases, the RC delay for Cu is lower compared to that of Al. This is mainly
because of lower resistivity value for Cu. So, we have to move from Al to Cu.

12
 ρ L2
RC Delay = ε
M S
ρ = resistivity
M = metal thickness
ε = permittivity of ILD
L = length of metal layer
S = ILD thickness

13

The RC(Resistive-capacitive) delay associated with metal layer is influenced by various

parameters.
To decrease the delay, the resistivity has to be lower i.e. conductivity value has to be
high. Note Cu has higher conductivity than Al
Decrease in metal thickness (decrease in device size) increase the RC delay. So, to
compensate that, we have to chose a high conductivity material. That’s why, we
moved from Al to Cu.
Similarly if we choose a material with low epsilon (low dielectric constant), RC delay
could be decreased. People are exploring various low K materials in the place of SiO2.

13
  Cu has lower resistivity
 Lower joule heating
 Allowing higher current densities and
therefore smaller sizes
 Lower electro migration resistance – less
failures

14

In addition to higher conductivity, Cu has few more advantages which is mentioned in

this slide.

As you know, joule heating (or ohmic heating) is directly proportional to resistance of
the given material, the joule heating is lower for Cu.

Besides, current density is inversely proportional to resistivity of the material, thus Cu

allows higher current densities and only smaller size is required compared to that of
Al to allow the same current.

Electro migration Resistance:

When current is passing through a conductor, the electrons move from one end to
the other end. They transfer some of their momentum to the metal atoms and
gradually the metal atoms also move. This is called electromigration. This
phenomenon is not of much importance when the current densities are low. In IC
chip the current densities are very high and electromigration can cause failure of a
circuit.

In the beginning, the metal would fill the space between the insulators and the
current density would be at a certain level. If sufficient atoms move due to
electromigration, then a small void will form. Now the all current has to go through

14
the metal and hence near the void region, the current density will increase. The
electrical resistance of the metal line is also higher now, because the electrical
resistance is inversely proportional to the cross sectional area. This results in larger
heat release and hence higher local temperature. At higher temperatures, the metal
atom diffusivity is higher, which makes it easier to ‘push’ the atoms. The increased
current density and higher temperature accelerates the formation of voids and finally
results in the circuit failure.
The extent of electromigration movement depends on the nature of the material. For
example, materials such as copper, tungsten and gold have good electro migration
resistance. We must note the difference between electrical resistance and electro
migration resistance clearly. Electrical resistance indicates the resistance to
movements of electrons. We want good electrical conductors (i.e. low electrical
resistance). At the same time, we want materials which have high electro migration
resistance.
If the electro migration resistance is poor, then after many hours of operation, the
resistance of one or few wires will increase dramatically. It can lead to the failure of
the chip. These types of failures, where the chip originally functions well and after
few months of operation fails, are called “reliability issues”. This means that the chip
appears to be good during testing in the fab, but it is not reliable and after sometime
it can fail.

14
  Difficult to pattern using conventional
etching technique
▪ Generate etching products such as CuCl2 which is
not easy to evaporate.
 Quickly diffuses into oxides and Si
▪ Altering the property of Si and oxides –more
failures
 Oxidizes in air
▪ Poor oxidation resistance
15

But there are new issues coming up in the process side when Cu technology replaced
Al technology. What are those issues? It is mentioned in this slide.

If you want to create patterns on a given metal, you have to remove some part of the
metal. The metal is removed conventionally by etching technique (we will discuss this
process later). For example, if you have metal A, it will react with other chemicals B
and it will form a etching product C. The “ C” has to be volatile /dissolvable so that
the metal will be removed.

For Al, the removal is done by etching. However for Cu, the etching products are non-
volatile in nature. So , we can’t use etching for Cu removal.

Also Cu quickly diffuses in to Si and SiO2 unlike Al. If Cu (conductor) diffuses into SiO2
(insulator), it will alter the property of SiO2 and causes of failure of chips. These are
the two major issues.

How to overcome them. We will discuss this in this chapter when we are discussing
process flow diagram of Cu technology.

15
  Etching products –non volatile
 Instead of etching , chemical mechanical polishing is
introduced

 Diffusion of Cu in to SiO2
▪ Introducing barrier layers between Cu and SiO2
such as Ta, TaN, TiN

16

As we discussed, we have few issues in introducing Cu technology in in fabrication.

How we overcame them?

Instead of etching, chemical mechanical polishing – a removal technique was

introduced. We will see this process in detail in removal chapter. A brief introduction
to this process is given at the end of this chapter.

Diffusion of Cu in to SiO2 is overcome by introducing a barrier layer (ex: Ta, TaN, TiN)
b/w Cu and SiO2.

Using these techniques, we moved from Al to Cu. In the next couple of slides, we will
see Al and Cu technology in detail.

16
 Metal layers

Cu Cu Al Al

Cu Cu Cu W W W

Vias

17

The difference b/w Cu and Al technology

Metal layer Contact Vias

Al W W

Cu W Cu

But why we are using W. It is easy to deposit W in high aspect ratio structures than
Al. But note W has higher resistivity. But the overall length of vias are small compared
to that of metal layers. Hence contribution to overall resistivity will be low. So, we can
use W in vias

But for contact, W is used for both Cu and Al.

Aspect ratio - ratio of length to width

High aspect ratio - the ratio of length to width is small.

17
 a

18

This slide shows the conventional aluminum process.

Here Yellow color region represents SiO2. Blue color region represents Al. Brown
color region represents positive pattern/positive photoresist.

I have structure as shown in (a). I want to pattern this so that I could get a structure
as shown in (d). How to achieve this ? The major steps involved in it are shown in
here.

Basically I have a rectangular block of Al as shown in (a) and I want to get a vertical
structures as shown in (b). To do this patterning, put a positive pattern (I will be
discussing more about positive pattern & negative pattern, how to put that on top of
any layer as shown in (a) in next chapter) on top of Al layer. Now if you expose this
structure to etching solution, the region beneath the positive pattern will not be
exposed to the solution and hence it cannot be removed(ideally). However, the
region which is exposed to the etching solution will be removed. After that we have
to remove the positive pattern. Then we will get the structure (b). Then, we have to
deposit SiO2 layer as shown in (c) by using suitable deposition technique. Afterwards,
the excess SiO2 layer will be removed by suitable removal techniques(subtractive
etching) by as shown in (d).

The main point I want to share here is, the Al patterning could be done by etching
process. But you cannot employed this step for Cu patterning as explained
previously.

18
 Ref: https://www.philamuseum.org/booklets/7_43_80_1.html
19

For making Cu patterns, people used damascene technique. The name damascene
originates from Damascus, the capital of modern Syria.
This is the old technique by which people inlay one metal in to other metal. The
techniques was used for making decorative patterns for jewellery, bowls etc.
See the figure in LHS. First we have to create pattern on the substrate. Then, cut the
metal which is to be inlaid into required shape. Then hammering the metal in to the
substrate, we will get the required structure as shown in 3.

The above technique was inspired for making Cu patterns in the Chip. Hence, it got
the name Cu damascene technique.
Now see the RHS figure. The first step is the same. In the second step, copper is
applied to the entire substrate and then polish the copper so that the copper is
stayed only on the channel made.

19
 20

How the same Al pattern created by both using conventional process and damascene
process is shown in this slide.

In RHS figure, read the negative pattern as positive pattern.

If you look conventional process, first deposit Al, then create patterns on Al by
etching. Then deposit SiO2. But in damascene technique, deposit SiO2, create
patterns on SiO2, then deposit Al and finally remove extra Al by polishing. So there is
no etching process involved in the damascene technique.

Hope you got the difference b./w these two techniques.

It is to be noted that dark blue represents etch stop layer. It is to make sure that
etching will proceed until this layer exposes to the solution. As soon as, this layer
exposed to the etching solution, the etching stops. It is to make sure that etching will
be proceeded upto a certain height. We will discuss this in detail in removal chapter.

20
 Example of Single Damascence Process

Single, because one layer is created in one

damascene step
Polishing of Copper makes this possible

Polish
Etch
Dep

21

Again in damascene process, we have single damascene and dual damascene

process. In this slide, single damascene process is described.

Here the vertical structure is created first followed by horizontal structure. i.e. only
one layer is created in a single step.

21
 Example of Dual Damascence Process

Dual, because two layer are created in one

damascene step

Polish
Dep
Etch

22

Here, both the horizontal and vertical structures are created at the same time (in a
single step). It reduces the number of steps involved and increases the throughput.

22
 Fig .1 Fig .2

23

Let see what are the steps involved to make the structure given in Fig. 2 from Fig. 1

Cu metallization – Process integration: Copper has lower electrical resistance and

higher electromigration resistance then aluminum. Hence it was introduced as
interconnect material in the 1990s. Dry etching of copper was difficult and hence the
aluminum process integration scheme could not be used for copper. A new set of
processes and sequence was needed. The following describes the process integration
scheme of copper metallization.

Fig 1. Schematic of chip in BEOL , with Cu line (a) after M1 layer Fig 2. after
fabrication of via12 and M2 layer.
Here via12 refers via connecting M1 and M2 layer.

23
 Fig. 3 Fig. 4

Fig. 5 Fig. 6

24

At first, a thin layer of silicon nitride is deposited on top of copper, by LPCVD (Low pressure chemical vapour deposition) as shown in Fig 3. Next, a thick layer of silicon
dioxide is deposited on top (Fig. 4). Both the silicon nitride and silicon dioxide are insulators. Silicon nitride acts as an etch stop layer. In the next step, using lithography
and dry etching, holes for the vias are created (Fig. 5). In this process, the etching ‘stops on nitride’. i.e. only the oxide layer is removed but the nitride layer is not
removed. The etching chemicals and process conditions are chosen such that only the oxide will etch.
Then, again using lithography and dry etching, trenches (horizontal structure) for metal lines are made (Fig. 6). This is called as ‘blind etch’ because the etch does not stop
at another material. The etching time is controlled so that the expected depth (with some variation) will be created.

24
 Fig. 7 Fig. 10

Fig. 8
Fig. 11

Fig. 9
Fig. 12

25

Then a thin layer of the silicon nitride, inside the via hole, is removed using dry etching using suitable combination of chemicals and plasma (Fig.
7). During this etch, a slight damage to Cu lying below may occur. However, since the nitride layer is thin, the etch time will be very short and the
damage is also limited. If the nitride layer were not present and only oxide were used as insulator, the potential damage to Cu line would be
severe.
Subsequently, a thin layer of barrier (Ta/TaN, and in some cases, an additional layer of Ru) is deposited (Fig. 8). This is needed to prevent the
diffusion of Cu through the silicon dioxide insulator. Then, another thin layer of Cu is deposited using CVD method (Fig. 9). This is needed to obtain
a layer of at least moderate electrical conductivity for the next step.
After the seed layer is deposited, a thick Cu layer is deposited using electrochemical deposition (Fig. 10). The Cu formed has larger crystals, lower
electrical resistance and higher electromigration resistance compared to Cu deposited by other methods such as PVD or CVD. The Cu can not be
deposited only inside the vias and trenches. Hence it is deposited throughout the wafer surface. Then in the next step, the excess Cu is removed
using CMP (Fig. 11)
The removal is done in two steps. In the first step, only the Cu is removed. The barrier and the insulator are not removed (Fig. 11). In the second
step or 2nd stage of the CMP, a different slurry is used and the barrier metal is also removed in the unwanted places (Fig. 12). Subsequently, the
Cu is annealed so that the crystal size increases.
This scheme of intergration is called “via first” integration because via holes are made before trenches here. In another process sequence, the
trenches can be made first and the vias can be made afterwards (i.e. the processes in Fig. 5 and Fig. 6 can be done in reverse order) and that
scheme is called “trench first” integration. Most fabs use the via first scheme for copper metallization.
Summary: Process integration denotes combining various processes to obtain the desired structure, to obtain a functioning chip, in a robust
fashion. In the modern chips, the BEOL part plays a significant role in determining the yield as well as the speed of the chip. Electromigration is
the movement of metal atoms due to the movement of electrons. It can cause failures at the later stage of chip operation and hence is a
reliability issue. If the metal lines are long, and/ or if large current densities are used, then the chances of failure by electromigration is high. It is
desirable to have high electromigration resistance and low electrical resistance. Aluminum has more electrical resistance than Cu and less
electromigration resistance than Cu. However, it can be etching using plasma and a process sequence using tungsten vias and aluminum metal
lines was used to make interconnects. With the introduction of CMP, it is possible to make Cu vias and Cu metal lines on chips, and the different
process sequence needed to obtain Cu interconnects was discussed.

25
 26

We will see trench first and via first Cu process in detail. I am concentrating only on
making vias and trenches. So do not worry about other processes such as copper
deposition and Cu polishing.

In this slide, trench first (via next) process is given: PR represents photoresist (in the
previous slide, it mentioned as positive pattern).

First they make trench (Fig. 3) and then deposit photoresist (Fig. 4). Here they have to
deposit thick layer of photoresist (referred as photoresist pooling) and then make
small hole (via –high aspect ratio) as shown in Fig. 5. This is difficult to do. Hence, it is
usually not preferred.

Finally, photoresist is removed. You will be end up with trench and via structure as
shown in Fig. 6

26
 27

Here via first (trench next process is given): As you see in the figure, via is created first
(Fig. 9) followed by trench (Fig. 10- fig. 12). The main advantage is , we need not to
make via in the thicker photoresist as in the previous case. Thus, this process is really
preferred. But it also has few disadvantages For example, as you see in figure Fig. 10,
residual photoresist is present at the bottom. This may be absorbed by the SiO2 layer
and alter its characteristics.

27
 Fig .1 Fig .2

28

Let see what are the steps involved to make the structure given in Fig. 2 from Fig. 1

Aluminum process: When aluminum is used as interconnect material, a layer of

titanium and titanium nitride is used as a barrier and adhesion promoter. This
prevents the diffusion of aluminum atoms through the insulator. The insulator
material used is SiO2. The sequence of process steps needed to fabricate a via and a
metal line are given below.
Let us assume that the fabrication of M1 is completed and that via12 and M2 have to
be fabricated.

28
 Fig. 3 Fig. 5

Fig. 4 Fig. 6

W deposition
29

First, a layer of silicon dioxide is deposited on top of M1 (Fig.3). Then using lithography and plasma etching, via12 hole is made (Fig.4). Next, a thin
layer of TiN/Ti is deposited on top. This film is formed on the top of the surface as well as on the sides and bottom of the via hole (Fig. 5). Then, W
is deposited using CVD-chemical vapor deposition (Fig. 6)

29
 Fig. 9
Fig. 7

Fig. 8
Fig. 10

30

Then, excess W is removed using CMP (Fig.7)

In the next step, aluminum and titanium are deposited on the top (Fig.8). After that, using lithography and plasma etching,
aluminum is removed from unwanted locations. The titanium barrier layer is also removed along with aluminum in those
locations (Fig.9).
Oxide layer is deposited on top of the aluminum (Fig. 10) and the non-planar surface is subjected to CMP, to make it planar. This
is necessary so that subsequently lithography can be done on the surface with minimal distortions.

30
 31

In this slide, I am explaining about CMP process which was introduced to remove
excess copper in the place of etching.

Chemical mechanical polishing is a process in which both chemical and mechanical

actions are used to remove the excess material. The schematic of CMP machine is
given in this slide. The wafer needs to be polished to be kept upside down (shown as
blue color) and rotate against the pad under pressure. The CMP slurry consists of
abrasive particles (Silica powder, alumina powder etc), oxidizers, corrosion inhibitors,
pH tuners and surfactants are continuously supplied to be the pad. The slurry
chemicals react with wafer surface and will remove the excess material.

We will discuss about CMP process in detail in removal chapter.

31
 ❑ Al vs Cu processes
❑ Al -etch / Cu Damascene (CMP)
❑ Al -via is W / Cu- via is Cu
❑ Al & Cu: Contact is W

❑Overall, the processes involved are

❑ Lithography, PVD, CVD, Electrochem
Dep, Etch, Anneal

32

32
33

33
34

34