Short-channel effect immunity

(CMOS Technology Boosters)

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 Structural By choosing
Different different
techniques modifications
Materials

Combination
of both

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 Different techniques
• Silicon on Insulator (SOI)
• High-k dielectric
• Strain Engineering
• Junctionless (JL) FET
• Double/triple material gate
FET
Structural modifications
• FIN-FET
• Double Gate (DG) MOSFET
• Triple-gate MOSFET
• Triple plus-gate (quasi-
surrounding-gate) MOSFET
• Π-gate
• Ω-gate
• Gate-all-around (GAA)
MOSFETs
• Quadruple Gate MOSFET
• Cylindrical MOSFET
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 Silicon on Insulator (SOI) –
for substrate leakage reduction

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 Silicon on Insulator

Low Drain Junction Capacitance:

• In bulk MOSFETs, the parasitic capacitance at the drain junction consists

of two components: Capacitance between the drain/substrate junction and
the capacitance between the drain and the channel stop implant under the
field oxide

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• As scaling the MOSFETs to nanometer regime, highly doped substrate regions
are inevitable which leads to high junction capacitances. On the other hand,
SOI MOSFETs mainly contains only one parasitic capacitance which exits
between the buried oxide and the silicon substrate. This capacitance is typical
much lower when compared to the capacitance of bulk MOSFETs

Reduced Short-Channel Effects:

• In SOI MOSFETs, SCEs such as threshold voltage roll-off and DIBL are mainly
influenced by the channel thickness, buried oxide thickness, substrate doping
and channel doping concentration.
• The threshold voltage roll-off occur at the smaller gate voltages in SOI
MOSFETs than in bulk MOSFETs, by using ultra-thin SOI film the threshold
voltage roll off can be reduced.
• Another SCE, DIBL occurs due to the charge sharing between the gate and the
S/D junctions. However, in ultra-thin SOI MOSFETs, the channel region
prohibits drain to take control of channel charges. 6
No Latch-Up :
Latch-up is an unwanted condition occurs in bulk CMOS devices as shown in fig
(a). The triggering of inherent PNPN thyristor structure formed by the Bi-polar
transistors in bulk CMOS devices lead to severe problems in device performance.
However in SOI CMOS devices, the latch-up problem is ruled out as there is
electrically isolated thick buried oxide layer between the devices as shown in fig (b).

IN

GND VDD

OUT GN IN
VDD
D
p+ n+ n+ p+ p+ n+ OUT

n+ n+ p+ p+

BO
X
n-well

Si-sub
p-sub
Thyristor

(a) (b)
Fig: Cross-sectional view of (a) bulk CMOS (b) SOI CMOS 7
 High-k dielectric –
Reducing Gate Leakage Current

• The ultimate limit at which bulk oxide could be used was that
required in 45nm technology node = 1nm. It is about three atomic
layers in thickness.
• The oxide thickness at which direct tunneling starts is 3nm.
• With reduction of gate oxide thickness, direct quantum-mechanical
tunneling of electrons from the gate across the gate oxide to the
underlying silicon causes an increase in the gate leakage current.
• After reaching the 70 nm node, a desperate need was felt to use a
high dielectric constant insulating material above the silicon dioxide
layer to subdue the gate leakage current to ignorable proportions.
• Zirconium oxide (ZrO2) with k = 25, Hafnium oxide (HfO2) with k
= 24, etc.

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 High-k Dielectric Concept

(a) (b)

Fig. (a) MOSFET with SiO2 as dielectric material (b) MOSFET with High-k as dielectric material
  
o Physical Oxide Thickness tox  EOT  k  where,  Sio 2 is relative
  SiO 2 
dielectric constant of SiO2 and k is relative dielectric constant
of high-k material.
o Replacing the silicon dioxide gate dielectric with a high-κ material
allows increased gate capacitance without the associated leakage
effects
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High-k dielectric - Reducing Gate Leakage Current

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 Strain Engineering – for Enhancing Carrier Mobility
• One could replace silicon (electron mobility 1400 cm2V−1 s−1) with
high mobility semiconductors GaAs (electron mobility 8500
cm2V−1 s−1) or Indium phosphide (InP) (electron mobility 5400
cm2V−1 s−1). But for these semiconductors, the level of
technological maturity for large-scale production of ICs is much
lower.
• In strained silicon, the silicon atoms are pulled apart from their
normal positions in the lattice, increasing their interatomic distance
by a small amount ~1%.
• Strain engineering is a strategy employed in silicon IC
manufacturing to increase the carrier mobility.
• By virtue of the increase in spacing between the atoms than for
regular silicon, the electronic band structure of silicon is modified
in such a manner that effective mass of charge carriers in silicon is
reduced.
• Lower is the effective mass higher is the mobility. 11
 Strained channel MOSFET

(a) (b)
Fig : Lattice structure of (a) unstrained Si and SiGe (b) strained Si on relaxed SiGe

• The strain is a very useful parameter in devices as carrier

mobility significantly increases by altering the band structure at
the channel.
• The mobility becomes roughly twice that of a conventional Si
substrate.
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 Strain Engineering – Strained silicon channel

Interatomic spacing is 4.2% greater in Ge than in Si. So if a Si

overlayer is deposited on a SiGe substrate, Si atoms are placed at
larger distances than they would be in a normal Si lattice

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Junctionless (JL) FET – to overcome doping difficulties in short
channel devices

• Unlike conventional inversion mode MOSFET, a JLT has a

single type doped channel that extent from source to drain
electrodes.
• This avoids the necessity of abrupt doped junctions at the
source/drain to channel junctions at smaller scales.
• A sufficient gate metal work function and thin channel is
required for complete channel depletion.

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Junctionless (JL) FET

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 Dual-metal-gate

• One of the prominent means to get rid of hot carrier effect (HCE) is
the gate engineering technique in which the cascaded gate structure
consisting of two/three metals of different work functions is used.

• If there are two gate metals, they are so cascaded that the gate near
the source is a metal (M1) with higher work-function and the drain
side metal (M2) is of relatively lower work-function.

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 Contd.

Fig. dual metal gate structure

Fig. Channel electric field distribution of
• Reduces DIBL. DMGFET.

• Hot carrier effects are minimized due to the peak electric field at
the drain end is reduced.
• As a result of this, the electron velocity and the lateral electric
field along the channel increases sharply at the interface of the
two gate material which further results in the increased gate
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transport efficiency.
 Contd.
• Further, the structure creates a step-like surface potential profile in
the channel and thereby ensures screening of the minimum potential
point from drain voltage variations.
• The metal gate M1 is thus rightfully known as the Control Gate and
the metal M2 as the Screen Gate.

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 Back gate

• Back gate gives the extra

opportunity to control the threshold
voltage of any structure with its
negative and positive polarities.
• The front gate can be used to
switch the device, whereas the
back-gate can be used to set the
correct threshold voltage.
Fig. Schematic representation of the UTB FD-
SOI MOSFET

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Structural modifications

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 Double Gate (DG) MOSFET

• The main idea of a double-gate MOSFET (DGFET) is to have a

Si channel of very small width and to control the Si channel by
applying gate contacts to both sides of the channel.
• The double gate concept can be garnered from the fully depleted
(FD) SOI structure.
• The most common mode of operation is to switch both gates
simultaneously.
• Another mode is to switch only one gate and apply bias to the
other (back gate).

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 Double Gate (DG) MOSFET

DGFET is of the following types:

• Planar (Gates and channel are horizontal)

• Vertical (Conduction direction is vertical)

Planar DG MOSFET Vertical DG MOSFET 22

 Triple-gate MOSFET

• The current drive of multiple-gate SOI MOSFETs is essentially

proportional to the total gate width.
• For instance, the current drive of a double-gate device is double that
of a single-gate transistor with same gate length and width.
• Multi gate structures offer better short channel immunity due to
enhanced gate control over channel owing to thinner channel and
more gate area. 23
 Triple plus-gate (quasi-surrounding-gate) MOSFET

Π-gate Ω-gate

• These devices are basically triple-gate devices with an extension of

the gate electrode below the active silicon island, which increases
current drive and improves short-channel effects. 24
 Triple plus-gate (quasi-surrounding-gate) MOSFET

• The gate extension can readily be formed by slightly over-etching

the buried oxide (BOX) during the silicon island patterning step.
• The gate extension forms a virtual, field-induced gate electrode
underneath the device that can block drain electric field lines from
encroaching on the channel region at the bottom of the active
silicon.
• These gate structures very effective at reducing short-channel
effects than double/triple-gate devices.

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 FIN-FET
-- Gate controllability

• With the decrease in chip size, the gate began to lose its
control over the channel.
• In short-channel MOSFETs, the drain began to dominate,
overpower, and overtake the gate in its influence over the
channel through drain-induced barrier lowering.
• The FIN-FET device has emerged as a consequence of these
endeavors of building an architecture in which gate will be the
master electrode under whose authoritarian control all device
activities will be managed.
• FIN-FET is the first non-planar MOSFET structure.

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 FIN-FET

The FINFET is influenced by physical parameter fluctuations such as

variations in gate oxide thickness, fin thickness, gate length and other
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parameters.
 Gate-all-around (GAA) FETs

•Volume inversion and the superior transconductance is possible in

‘‘gate-all-around’’ (GAA) device.

•Excellent short channel immunity from increased gate area and gate
controllability.

•Gate-all-around (GAA) FETs

• Quadruple Gate MOSFET
• Cylindrical MOSFET

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 Quadruple gate MOSFET

Fig. Quadruple gate MOSFET structure 29

 Cylindrical MOSFET

• Corner effects can be minimized

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 Nanowire FET

Fig. Silicon Nanowire FET structure 31

 Nanotube FET

Fig. Silicon Nanotube (SiNT) FET structure 32

 Problems associated with MuGFETs
• MuGFETs require more advanced fabrication techniques such as improved
etching accuracy and reliability.

• MuGFETs exhibits a very undesirable characteristic known as corner effect

which occurs due to the electrostatic coupling of two adjacent gates at the
corners. This effect degrades the device performance by increasing the off state
leakage current

• In order to retain the desired values for current, threshold voltage, and
subthreshold swing, the width of the fin needs to be decreased as the channel
length and the gate length are decreased. This imposes a difficult task on the
fabrication process.

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