STM32L0 ULP Peripherals

OBJECTIVES 2

• Introduce STM32L0 Ultra-Low-Power peripherals

• Highlight key features and discuss possible applications

• With focus on energy consumption optimizing enhancements

• Test some of the peripherals in operation (exercises)

After this presentation you will understand

the benefits of Ultra-Low-Power peripherals
included in STM32L0.
 ULP Peripherals Overview 3

Flash I/F
SW Debug 64KB Power Supply
CORTEXTM-M0+
M0+ Flash Memory Reg 1.8V/1.5V/1.2V
CPU POR/PDR/BOR/PVD
32 MHz 2KB

Matrix / Arbiter (max 32MHz)

ARM ® Lite Hi-Speed Bus
Data EEPROM
With MPU Int. RC 16 MHz
8KB SRAM
Xtal 1-24MHz
20B
Backup Reg.
37/51 I/Os Int. RC 37 kHz
TSC
NVIC Xtal 32,768 kHz
RNG
SysTick Int. RC 65K..4.2MHz
RCC
DMA PLL
7 Channels
RTC / WUT
AES Tiny 4 x 16-bit Timer
1x LPTIM
EXTI 2 x Watchdog
(ind. & window) Glass LCD Control.
(up to 8x24)
2 x SPI 2 x COMP
USB 2.0 FS
1 x 12-bit DAC
2 x USART
1 x 12-bit ADC
19 channels / 1Msps 1 x LPUART

Temp Sensor 2 x I2C

Digital peripherals
Real-Time Clock (RTC)
 Block Diagram (RTC) 5

RTC_TAMP1 Backup Registers and Tamper Event

RTC Tamper
RTC_TAMP2 Control registers
TimeStamp Event
RTC_TS TimeStamp Registers
RTC_REFIN Alarm B
Alarm B Event

RTCSEL [1:0] =
Alarm A
HSE / 32
hh:mm:ss:ssr
Smooth dd/mm/year
LSE
Calibration
LSI Alarm A Event
hh:mm:ss:ssr
RTCCLK
dd/mm/year =
Calendar Calendar
ssr
(binary format)
Asynchronous Synchronous ck_spre OSEL
7-bit Prescaler 15-bit Prescaler Day/date/month/year HH:mm:ss
(12/24 format)
PREDIV_A [6:0] PREDIV_S [14:0]

Control
Output
1 Hz
RTC_CALIB

512 Hz Wake-Up
COSEL RTC_OUT

Prescaler
/2, /4, /8, /16 Wake-Up Event
16-bit autoreload
Timer
 RTC Calendar 6

• The initialization or the reading of the calendar value is done

through 3 shadow registers, SSR, TR and DR. The RTC TR and
DR registers are in BCD format.

• SSR register represents the RTC Sub seconds register

Calendar

12h/24h

Actual Date Time

registers
Day : Month : Date : Year hh : mm : ss : ssr

Shadow
registers DR TR SSR
 Wake-Up Timer (WUT) 7

RTCCLK (LSE, 32.768 kHz)

To Calendar
Asynchronous Synchronous
7-bit Prescaler 15-bit Prescaler
ck_spre
VALUE <0x00, 0x7F> VALUE <0x0000, 0x7FFF>
DEFAULT = 0x7F DEFAULT = 0xFF

2 VALUE <0x(1)0000, 0x(1)FFFF>

3
Wake-Up
WakeUpCLK

Prescaler
/2, /4, /8, /16 Wake-Up Event
16-bit autoreload
Timer
1

WakeUpCLK MIN_TIME MAX_TIME Resolution

RTCCLK /2 121 µs 4s 61 µs resolution

1
RTCCLK /16 976 µs 32 s 488 µs resolution

2 1s 18.2 h 1s resolution
ck_spre = 1Hz
3 18.2 s 36.4 h 1s resolution
 BACKUP domain 8

RCC CSR LSE (32 kHz)

IWDG LSI (37 kHz)

Wakeup Logic
Wakeup Pin 1 /
Tamper 2

RTC + 20 Bytes Data

RTC output / Wakeup Reference clock
Pin 2 / Tamper 1 / input
Timestamp

RTC pins alternate functions

Tamper detection (resets all RTC user backup registers)
Time Stamp detection: the calendar is saved in the time-stamp registers
Configurable level: low/high, interrupt request generation
Wake-Up:
Reference clock input: 50 / 60Hz precise signal resynchronization
Alarm Ouput: Alarm A, Alarm B and RTC Wakeup event signals
Clock calibration Output: 1 Hz / 512 Hz when using 32.768 kHz crystal
 Smooth Digital Calibration 9

• Consists in masking/adding N (configurable) 32kHz

clock pulses, fairly well distributed in a configurable
window.
• A 1Hz output is provided to measure the quartz
frequency and the calibration result.
• Calibration value can be changed on the fly.

Calibration window Accuracy Total range

8s ±1.91 ppm [0 ±480ppm]
16s ±0.95 ppm [0 ±480ppm]
32s ±0.48 ppm [0 ±480ppm]
 RTC registers write protection 10
10

• By default and after reset, the RTC registers are write protected to
avoid possible parasitic write accesses.
• DBP bit must be set in PWR_CR to enable RTC write access

• A Key must be written in RTC_WPR register.

• To unlock write protection on all RTC registers

• 1. Write ‘0xCA’ into the RTC_WPR register

• 2. Write ‘0x53’ into the RTC_WPR register

* Except for the clear of Alarm and Wakeup timer interrupt flags

Writing a wrong key reactivates the write protection.

 Tamper detection 11

• 2 tamper pins and events

RTC_TAMPx
• Configurable active level for each event
Tamper
switch STM32
• Configurable use of I/Os pull-up resistors

• Configurable pre-charging pulse to support different

Capacitor is optional (filtering can be
done by software)
Biasing is done using the I/O’s Pull-
up resistor
capacitance values
• 1, 2, 4 or 8 cycles
• Configurable filter:
• Sampling rate
(128Hz, 64Hz, 32Hz, 16Hz, 8Hz, 4Hz, 2Hz, 1Hz)

• Number of consecutive identical events before

issuing an interrupt to wake-up the MCU
(1, 2, 4, 8)

• Reset of backup registers when tamper event detected

• Tamper event can generate a timestamp event

 12

Digital peripherals
LPTIM
 Low-Power Timer Block diagram 13

APB bus

Registers

Up/Down 1 2 3

Glitch
Encoder Filter Input 2

Glitch
1 2 3
Filter Input 1
up to 8 ext
trigger
Glitch
s/w
Filter trigger 16-bit ARR

MUX trigger

APB clock + 16-bit Counter Output

LSE 3-bit Prescaler
LSI
HSI16 CLKMUX
16-bit Compare
 LPTIM Glitch Filters 14

Glitch
Filter
2 consecutive 2 consecutive 2 consecutive
samples samples samples

CLK

INPUT

Filtered
OUTPUT

Filtered glitches

2, 4 or 8 consecutive samples configuration

 LPTIM as Waveform Generator 15

• 3 configurable waveforms
• PWM waveform
• One Pulse waveform
POL = 0
• Set Once waveform
LPTIMx_ARR

LPTIMx_CMP

LPTIMx_CNT

PWM

One Pulse

Set Once
 LPTIM as Encoder Interface 16

1 2 3
• Encoder mode
• Same operation as Encoder mode on General Purpose Timers
• Only available when LPTIM runs in Continuous mode

CLK

INPUT1

INPUT2

COUNTER
 LPTIM as External Pulse Counter 17

Sampling Glitch
1 2 3
Filter
Input 1

16-bit ARR

APB clock + 16-bit Counter Output

LSE 3-bit Prescaler
LSI
must be ‘000’
HSI16 CLKMUX
16-bit Compare

Fully asynchronous operation

Glitch
1 2
Filter
Input 1

16-bit ARR

APB clock + 16-bit Counter Output

LSE 3-bit Prescaler
LSI
HSI16 CLKMUX
16-bit Compare
 18

Digital peripherals
USART
 USART – Block Diagram 19

Transmit Data
Register

Receive DMA Requests

Transmit. DMA
Tx Receiver Control Control
IrDA SIR
Encoder /
Rx Decoder
Interrupt IRQ Requests
Transmit
Receive Data Control /
Control
Register Status
Wakeup
from STOP
Node
nRTS Address Baud
/DE Rate
HW Flow
Generator
Control Wakeup
nCTS Unit

Clocks
SCLK Control
SCLK PCLK
SYSCLK
USART peripheral HSI
LSE
 USART Features List 20

Frame • 7, 8, 9 DATA bits

• 0.5, 1, 1.5, 2 STOP bits
• Even, odd, none PARITY
• Oversampling /8 and /16 (default)
Modes • Asynchronous 4Mbps
LIN
SmartCard (T=0, T=1)
IrDA
Basic MODBUS
Multiprocessor communication
Half duplex
• Synchronous (CLK line)
Other • DMA support
NO data loss
• HW flow control (RTS, CTS lines)
on wakeup
• Auto baudrate detection
• Programmable data order (MSB/LSB)
• Swappable Tx/RX pins
• Wakeup from STOP (!!! no data loss !!!)
 Wakeup from STOP (USART) 21

Typical Wakeup from STOP flowchart: There is a deviation add-on, due

Select the USART clock source to wakeup time:
HSI LSE tWUSTOP
DWU =
Set the UESM bit
(10 + M )⋅ Tbit
M is 0 for 8 bit, 1 for 9 bit frame
Select the Wakeup event
tWUSTOP is the time for wakeup
Address
RXNE Start bit
Match
from STOP mode (typ. 4.2 usec)

The first byte is received correctly

Go to STOP mode
if this timing is included in the
After wakeup, the WUF bit is set allowed overall deviation
 USART – Automatic Baudrate Detection 22

2 patterns for auto-baudrate detection:

T measured

T measured

The auto-baudrate completed Baud rate register updated

Conditions: ABRF flag set
Detection range: bit time from 16 to 65535 USART clock periods.
BRR must be a value different from 0.
Only oversampling by 16 allowed
 USART – Synchronous Mode 23

USART supports Full duplex synchronous communication mode

Another SPI like interface Full-duplex, three-wire synchronous transfer

USART Master mode only

Synchronous clock generated on (SCLK)

Programmable clock polarity (CPOL) and phase (CPHA)

Programmable Last Bit Clock Pulse generation (LBCL)

Master Slave
SCLK SCK

RX MISO

USART SPI
TX MOSI
NSS
Full Duplex
 USART – Single Wire Half Duplex mode 24

USART supports Half duplex synchronous communication mode

Only TX pin is used (RX is no longer used)

Used to follow a single wire Half duplex protocol.

VDD

R = 10 KΩ
USART1 USART2

TX TX

Half Duplex
 USART – Smart Card Mode 25

USART supports Smart Card Emulation ISO 7816-3

Half-Duplex, Clock Output (SCLK)

9Bits data, 1.5 Stop Bits in transmit and receive.

T = 0, T = 1 support

Programmable Clock Prescaler to guarantee a wide range clock input

ISO 7816-2 Electrical contact layout

USART C1 C5
TX
C2 C6

C3 C7
SCLK
C4 C8
 USART – IrDA SIR Encoder Decoder 26

USART supports the IrDA SIR Specification

• Half-duplex, NRZ modulation,
• Max bit rate 115200 bps
• The pulse width is 3/16 bit duration in normal mode
• Low power mode: 1.42MHz <PSC < 2.12MHz

USART

IrDA

SIR TX
Encoder
USART IrDA
transceiver
SIR RX
Decoder
USART – RS485, RS422 Transceiver Control 27

TX signal

DEAT DE signal DEDT

time time

TX +
USART
DE RS485
transceiver -
RX

The times are expressed in oversampling time units (1/8 or 1/16 of bit time)

The polarity can be selected by DEP bit

DE pin shared with RTS pin

 28

Digital peripherals
Low-Power UART (LPUART)
 LPUART 29

• LPUART includes all necessary hardware support to make

asynchronous serial communications possible with minimum power
consumption
• With just the LSE 32.768 kHz it is possible to run at up to 9600 baud
• For this purpose, the baudrate generation has been changed
comparing to the USART peripheral

SYSCLK
HSI16 to LPUART
LSE
APB (PCLK)

• Can be kept enabled and clocked even during STOP mode

 LPUART baudrate generation 30

256 × fCK
Tx/Rx Baud =
LPUARTDIV

Where: Tx/Rx_baud... desired baudrate

fck... LPUART clock source frequency
LPUARTDIV... coded on the the BRR register
(LPUARTx_BRR value can’t be lower than 0x300)

Desired Baud rate Actual Baud rate LPUARTx_BRR % Error

2400 Bps 2400.17 Bps 0xDA7 0.007
9600 Bps 9608.94 Bps 0x369 0.093

Assuming LSE (32.768 kHz) used as clock source

 USART/LPUART feature list 31

Features USART1/2 LPUART1

Programmable data word length (7,8 or 9 bits) • •
Configurable stop bits (1 or 2) • •
Hardware Flow Control (Modem, RS-485 transceiver) • •
Continuous communication using DMA • •
Multi-processor communication • •
Single wire half duplex mode • •
Dual clock domain and Wake-Up from STOP mode • •
Swappable Rx/Tx pin configuration • •
Synchronous mode •
Smartcard mode •
IrDA •
LIN •
Receiver timeout •
Modbus Communication •
Autobaudrate detection •
 32

Digital peripherals
2
IC
 I2C Block Diagram 33

PCLK
SYSCFG_CFGR1 /
HSI16 Data control I2C_PBx_FM+
SYSCLK I2C_CLK WUPEN
Digital Analog
Noise Noise
SMBus PEC Filter Filter GPIO SDA
gen./check logic
RCC_CFGR_I2CxSEL Wake-Up on
address match Digital Analog
Clock control
Noise Noise
MASTER clk GPIO
control Filter Filter SCL
logic
SLAVE clk.
stretching
SMBus
Timeout chck
SYSCFG_CFGR1 /
I2C_PBx_FM+

SMBus Alert ctrl.

& status SMBA

PCLK
Registers

APB bus
 Wakeup from STOP on address match 34

• When I2C_CLK clock is HSI, the I2C is able to wakeup MCU from
STOP when it receives its slave address. All addressing mode are
supported:
• During STOP mode and no address reception: HSI is switched off

• On START detection, I2C enables HSI, used for address reception

• Wakeup from STOP is enabled by setting WUPEN in I2C1_CR1

• The HSI oscillator must be selected as the clock source for I2CCLK in
order to allow wakeup from STOP.

• Clock stretching must be enabled to ensure proper operation

(NOSTRETCH=0)

2 configurable addresses
 Easy Master mode management 35

• For payload <= 255 bytes : only 1 write action needed !! (apart data rd/wr)
I2Cx_CR2 is written with : START enable (START=1)
Slave address configuration (SADD)
Transfer direction (RD_WRN)
Number of bytes to be transferred (NBYTES = N)
Autoend enable (AUTOEND=1) => peripheral will
generate STOP automatically after N bytes are sent

AUTOEND
0 : Software end mode End of transfer SW control after NBYTES data transfer :
• TC flag is set. Interrupt if TCIE=1.
• TC is cleared when START or STOP is set by SW
If START=1 : RESTART condition is sent
1 : Automatic end mode STOP condition sent after NBYTES data transfer

• Data transfer managed by Interrupts (TXIS / RXNE) or DMA

 36

Analog peripherals
Power Supply Supervisors
 Power Supply monitoring
VDD / VDDA / Reset circuitry 37

2.0V

100mV hysteresis
(PVD) 1.9V
(1.9V min)

1.8V
(BOR)
1.8V (min) 100mV hysteresis
1.7V

PDR / POR 1.5V

(1.5V)
Reset Temporization (tRSTTEMPO)

PVD interrupt
PVD enabled (if enabled)
by Software
PVD output

BOR reset
(NRST) Option Bytes
Reload
BOR/PDR reset
(NRST)

POR/PDR
(NRST)
 38

Analog peripherals
COMPx
 COMPx Block diagram 39

COMP1 window
mode selection COMP1 polarity WAKEUP
selection EXTI_LINE_21
PA1 +
COMP1 GPIOx
COMP1_VALUE
-
PA0 TIM2_ETR
PA4 (DAC) TIM2_CH4
PA5 TIM21_ETR
VREFINT TIM21_CH2
TIM22_ETR
COMP2 non-inverting TIM22_CH1
input selection LPTIM_ETR
COMP1 inverting LPTIM_CH2
PA3 input selection COMP2 polarity WAKEUP
PB4 selection EXTI_LINE_22
+
PB5
COMP2 GPIOx
PB6
PB7 COMP2_VALUE
-
PA2 TIM2_ETR
PA4 (DAC) TIM2_CH4
PA5 TIM21_ETR
PB3 TIM21_CH2
VREFINT TIM22_ETR
¾ VREFINT TIM22_CH1
½ VREFINT
LPTIM_ETR
¼ VREFINT
LPTIM_CH2

COMP2 inverting
input selection
 COMP features 40

• Parameters at a glance
• Full voltage range 2V < Vdda < 3.6V
• Propagation time vs consumption (typ. 2.7 < Vdd < 3.6V, for 200 mV step with 100
mV overdrive)
• High speed mode: 120ns / 100µA
• Low power mode: 1µs / 3µA

• Input offset: +/-5mV typ, +/- 20mV max

• Programmable hysteresis: 0, 8, 15, 31 mV

• Fully asynchronous operation

• Comparators are still operational even in STOP mode
• No clock related propagation delay (analog peripheral)

• Functional safety (Class B)

• The comparator configuration can be locked with a write-once bit
 41

Analog peripherals
ADC
1.8V ~ 3.6V
ADC Block Diagram 42
Vref+
VDDA

VSSA
AUTOFF
ADC_IN0
ADEN/ADDIS
.
.
.
. ANALOG MUX Bias & Ref
. GPIO
. Ports
. VIN
.
CONVERTED DATA Oversampler

ADDRESS/DATA BUS
.
ADC_IN15
S&H Sampling
Temp Sensor
time control SAR ADC
VREFINT
16-bit DATA
VLCD Analog Watchdog
Start
Higher Threshold
Input Sel. &
Scan Control
Lower Threshold
AUTDLY
Start & Stop
ADSTP Control s/w trigger h/w trigger

ADSTART ADRDY EOSMP EOSEQ EOC OVR AWD

Flags

TRG0 EXTRIG bit

Interrupt
TRG1 1 2 3 ADRDYIE EOSMPIE EOSEQIE EOCIE OVRIE AWDIE enable bits
TRG2

… DMA
Trigger enable and request
TRG7 edge selection

EXTSEL[2:0] bits

Interrupt
request
 Clock sources (ADC) 43

• The ADC has a dual clock-domain architecture:

• Dedicated 16MHz clock
• PCLK clock divided by 2 or divided by 4, in case of /1 the duty cycle must be 50%

ADC PERIPHERAL
PCLK ADC Prescalers: Digital Interface
/1 or /2 or /4

Analog Interface
16MHz
max
16MHz internal /1, /2, /4 .. /256
oscillator

Guaranteed maximum speed whatever the MCU operating frequency.

Capability to use the low-power auto-off mode.
(automatic ON/OFF switch of 16 MHz internal oscillator)
 Total Conversion Time 44

• Total conversion Time = TSampling + TConversion

Resolution TConversion TSampling Total conversion time tADC at fADC =

16MHz

12 bit 12.5 Cycles 1.5 Cycles 14 Cycles 875ns

10 bit 11.5 Cycles 1.5 Cycles 13 Cycles 813ns

8 bit 9.5 Cycles 1.5 Cycles 11 Cycles 688ns

6 bit 7.5 Cycles 1.5 Cycles 9 Cycles 562ns

Lower resolution allows faster conversion times for applications where high
data precision is not required.
 Auto delayed conversion 45

• Auto Delay Mode

• When AUTDLY = 1, a new conversion can start only if the previous
data has been treated, once the ADC_DR register has been read or
if the EOC bit has been cleared.

HW/SW Trigger

ADC State 1 Delay 2 Delay 3 Delay

EOC Flag

i Channel conversion #i

Note : A trigger event (for the same group of conversions) occurring during this delay is ignored.

This is a way to automatically adapt the speed of the ADC to the

speed of the system that reads the data.

Auto-delayed mode avoids any possible overrun issue

 Auto-OFF mode (Power Saving) 46

• ADC power-on and power-off can be managed by hardware and turn

OFF the 16 MHz internal oscillator in order to save power. The ADC
can be powered down:
• During the ADC is waiting for a trigger event (AUTOFF= 1) The ADC is powered
up at the next trigger event.
• During the delay and waiting for a trigger event (AUTDLY= 1 and AUTOFF= 1)
The ADC is powered up again at the end of the delay and at the next trigger event.

HW/SW Trigger

AUTOFF =1 1 Delay 2 Delay 1 Delay

AUTDLY =1 OFF ON OFF ON OFF OFF ON OFF

AUTOFF =0 1 Delay 2 Delay 1 Delay

AUTDLY =1 ON

AUTOFF =1
AUTDLY =0
1 2 1
OFF ON OFF ON OFF

AUTOFF =0 1 2 1
AUTDLY =0 ON

ADC Waiting for Trigger Startup Time i Channel conversion #i

 Oversampling 47

• Principle
• The ADC hardware can do averaging according to the formula:

• M and N are programmable

• N – 2 to 256
• M – division is made by logical shift up to 8 bits (division by 256)

• Benefits
• Data rate reduction
• SNR improvement
• Basic filtering
 STM32L0 implementation
48
• ADC does oversampling and averaging by HW
• N is setup by OVFS[2:0], 2x to 256x
• M by OVSS[3:0], 0 to 8 bit

19 0
Raw 20-bit
accumulator 0xDEDA1

Programmable Up to 8 bits
shift
15 0
16-bit result, the 0xDEDA
MSB is truncated Shift by 4 bits in this example

• EOC = 1 when new averaged value is ready

• ADC can be put to AUTOFF mode between conversions

 49

Analog peripherals
Glass LCD Controller (LCD)
 LCD Controller Block diagram 50
Frequency generator
LCDCLK
16-bit prescaler
COM0

Registers Clock MUX

COM3
Divide by 16 to 31
ADDRESS/DATA BUS

Interrupt SEG0
ck_div
COM
8-to-1 MUX
LCD RAM SEG Driver Analog
switch
(32x16 bits) Driver array

SEG27

SEG COM SEG28/COM4

MUX
SEG29/COM5
Registers Voltage VSS

Generator 1/3 – 1/4 VLCD

SEG30/COM6
2/3 – 3/4 VLCD
Pulse
1/2 VLCD SEG31/COM7
Generator
Contrast VLCD

Controller

Analog STEP-UP converter

 Frequency generator 51
• The LCD Controller (LCDCLK) uses the same
clock as RTCCLK. It can be: LSE, LSI,
HSE_DIV divided by 1, 2, 4 or 8.
LSE/LSI/
• The LCDCLK input clock must be in the range HSE_Div1/2/4/8
16-bits Prescaler
of 32 kHz to 1MHz.
LCDCLK LCDCLK / 32768
• The LCDCLK divided by 2PS[3:0] : ck_ps PCLK1 PS[3:0]
Clock MUX
LCD_FCR
ck_ps
• The ck_ps to be also divided by 16 to 31 to
adjust the resolution rate: ck_div DIV[3:0]
Divide by 16 to 31
f LCDCLK ck_div
fck_div = f LCD =
2PS (16+ DIV)
• The frame frequency is obtained from the LCD
frequency by dividing it by the number of active
common terminals

f Frame = f LCD * duty

The frame frequency must be selected to be within a range of around ~30 Hz to ~100 Hz
 Memory/Segment mapping 52
Digit 16 Segment 31 …… 2 1 0
X 3
A COM0
Example of Writing the
I character “A” on the
F H J B Liquid crystal display COM1
first digit
G K
COM2

E L M N C
COM3

DP
D

COM0 COM1 COM2 COM3 .

.
SEG0 X F E D .

SEG1 I J K N

SEG2 A B C DP COM7

SEG3 H G L M

0x 4 D 7 0 LCD RAM
 Common/Segment driver(1/2) 53

• Every common signal has identical waveforms but different phases

• The common has the maximum amplitude VLCD or VSS only in the
corresponding phase of a frame cycle.

• During the other phases, the signal amplitude is 1/4 VLCD or 3/4 VLCD in
case of 1/4 bias or 1/3 VLCD or 2/3 VLCD in case of 1/3 Bias and 1/2 VLCD
in case of 1/2 Bias.

• The first frame generated is the odd one followed by an even one

• Five Duty ratios can be selected: Static Duty, 1/2 Duty, 1/3 Duty, 1/4 Duty or
1/8 Duty

• Three modes can be selected: 1/2 Bias, 1/3 Bias or ¼ Bias

 Common/Segment driver(2/2) 54
Odd Frame Even Frame

The segment terminals are multiplexed and VLCD

COM0
2/3 VLCD
each of them controls four segments 1/3 VLCD

VSS
A segment is active if the corresponding VLCD

COM1
segment line gets a maximum voltage opposite 2/3 VLCD
1/3 VLCD
to the common
VSS

VLCD
Common signals are phase inverted in order

COM2
2/3 VLCD

to reduce EMI 1/3 VLCD

VSS

To activate segments[n] connected to COM0, VLCD

COM3
2/3 VLCD
SEGn needs to be inactive (VSS) during phase 0 1/3 VLCD
of an odd frame and active (VLCD) during phase VSS

0 of an even frame when COM0 is active VLCD

SEGn
2/3 VLCD
1/3 VLCD
To deactivate segments[n+44] connected to VSS
COM1, SEGn needs to be active during the Pixels[n] Pixels[n+44] Pixels[n+88] Pixels[n+132]Pixels[n] Pixels[n+44]Pixels[n+88] Pixels[n+132]

phase 1 of an odd frame and inactive during the RAM refresh RAM refresh
phase 1 of an even frame when COM1 is active
LCD RAM LCD RAM

Double Buffer Memory: LCD RAM AREA ALWAYS ACCESSIBLE

 LCD Contrast Control 55

The contrast can be adjusted using two different methods:

Method 1 (external VLCD voltage)

Contrast can be controlled by programming a dead time (up to 8 phase periods)
between each couple of frames where the COM and SEG value is tied to Vss in
the same time.
Odd Frame Even Frame

VLCD
COM0

2/3 VLCD
1/3 VLCD

VSS

phase0 phase1 phase2 phase3 phase0 phase1 phase2 phase3

3 phase dead time

Method 2 (internal STEP-UP converted used)

The software can adjust VLCD between 2.6 V to 3.3 V in 8 steps
 LCD Signals Generation 56

The LCD voltage levels can be generated :

Internally using an internal step-up converter or externally using VLCD voltage
An internal resistor divider network generates all VLCD intermediate voltages
External capacitor can be used to stabilize intermediate VLCD voltage
Signal shape and thus VRMS are improved without the use of High Drive (suitable
especially for large displays with higher segment capacity)

The nodes provide several

The RL and RH resistive
intermediate voltage:
networks are used to
• One (Bias ½),
increase the current during
• two (Bias 1/3)
transitions and to reduce
• three (Bias ¼)
consumption in static state.

remains active in STOP modes

not active in STANDBY mode
 Thank you

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