Save trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com CB COSCHENE USN TTT ISEVEIS st Semester M.Tech. Degree Examination, Dec.2019/Jan.2020 Digital VLSI Design “Time: 3 hrs Max. Marks: ! Note: Answer amy FIVE full questions choosing ONE ull question from each. Modute-1 1a. Describe the behavior of MOS system under extemal bias with ener Rosca and relevant equations ar) b, Explain the channel length modulation with fds equation. (06 Maris) ‘© Write the difference berncen enhancement mode and depletion JOSFEB) (04 Marts) OR 2a Explain the effects of short channel in MOS transistor and Og the expression for the b. Consider (08 Marts) Vyq =08V, resistive load inverter With Vop = $V, 1,200 40 and 22. Find eel wags noite margin ofthe circuit (06 Marts) Draw t depletion load nMOS inverter cteuit Vou and Vor ofthe creat, ‘nd Vig and find the (06 Marks) i 3. a Draw the neat cieuit diagram of Cl and explain the circuit operation with its charaeteristis mentioning all five (to Marts) Consider a CMOS inverter he AIRring parameters: Vp =3:3.V, Vig, = 06 TV, Ky = 200 wA/V?, Ke = 80 KAIV". Caleulate the noise margins ofthe gu (08 Marts) © Derive relationship tnt | 2) for symmetis CMOS iver. Also dics the 1 (0 Marks) or 4a tor cteut, What is the expression for fequency in arbitrary odd inverters (a0 nae b ays and derive the expression fOr Tyg. and Ty, for CMOS inverte, al equation method. (10 ark Modute-3 5 4 Explain four vansstor, theo transistor, wo transistor and one transistor DRAM cell Marks) 1b NsplatMincmory structure SRAM with read and write eiruitry with aid of read and write it diagrams (0 Macks) Lot? BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Vturesource Go Green initiativeSave trees use e-Question Paper Go green DOWNLOAD THIS FREE AT www.viuresource.com 1SEVEAS oR 6 a Explain the memory structure of feroelstrc random aecess meron (08 Mary Design 4x4 NOR base ROM array that ean store the following daa given, Note Ry, Bo, Rs, Ry —>Adatess 1G), Cs, C3, Cy Memory locations Rife Te EGG TG [Ge Tyofofofolifolt of to}oloferite opefi peti yefots * Coreteti tori ito os gre Differentiate between DRAM and SRAM. an M 7 a. Explain how to overcome tneshoié vollage drop in dighal tits strapping technique oxi) What is dynamic CMOS logic? Explain with an example (osatanks) Explain briefly with sable eco pas transistor in dyna GIOMNRE. (05 Marks on 8 a. Explain the static behavior of BICMOS inverter. (68 marks) 1 What is BICMOS loge ctcuit? Write an appli (Marks 6. Implement the following funtion using, BIC BCD (08 Marks 9a, What are the different models of ESD AF ‘With suitable diagrams. (40 Mars) Draw the circuit diagram to reduce LSA arte a few lines about their working. (ao Marky 10a, Explain fctoria sien gg (00 ark Explain performance vaility tion and performance modsling. 0 Marks) 2of? BRANCHES | ALL SEMESTERS | NOTES | QUESTON PAPERS | LAB MANUALS A Vturesource Go Green initiative