EC8691: Microprocessor and Microcontroller

Part –B:
12 B. Closely and Loosely coupled
Closely coupled system:
1. Share memory multiprocessor system.
2. Several processors share a common memory.
3. Processor communicates through shared memory.
Loosely coupled system:
1. Distributed memory multiprocessor.
2. Each processor has its own local memory.
3. Processors are tied tighter by switching through message passing scheme.

1. Closely Coupled Configuration:

 The main difference between coprocessor and closely coupled configuration is no special
instruction such as WAIT and ESC are used.
 The communication between 8086 and independent processor is done through memory space.
 Closely Coupled processor may take control of the bus independently. Two 8086’s cannot be
closely coupled.

Figure: closely coupled configuration

2. Loosely Coupled Configuration:

 In loosely coupled configuration, number of modules of 8086 can be interfaced through a
common system bus to work as a multiprocessor system.
 Each module in the loosely coupled configuration is an independent microprocessor based
system with its own clock source, own memory and devices interfaced through a local bus.
 Each module can also be a closely coupled configuration of a processor or coprocessor.
The block diagram of a loosely coupled configuration of 8086 is shown in figure.
 Fig: loosely coupled configuration

Advantages:
1. Better system throughput by having more than one processor.
2. Each processor is an independent unit and normally on a separate PC board.
3. One can be added or removed without affecting the others in the system.
4. Greater degree of parallel processing can be achieved

Disadvantages
1. Bus Arbitration (contention): Make sure that only one processor can access the bus at any given
time
2. It must synchronize local and system clocks for synchronous transfer
3. It requires control chips to tie into the system bus.

Bus allocation schemes:

 It needs priority allocation.
 It outputs a Bus Request (BRQ) to request the bus and BRQ line goes to some controller.
 The CPU input a Bus Grant (BGR) to gain access to bus
 To allocate the bus various methods are available. They are
 Daisy Chaining
 Polling
 Independent Priority
Daisy Chaining:
Need a bus controller to monitor bus busy and bus request signals
 It does not require any priority resolving network. The priorities of all the devices are
essentially assumed to be in sequence.
 All the masters use a single bus request line for requesting the bus access.
 The controller sends a bus grant signal, if the busy signal is inactive when the bus is free.
 The bus grant pulse goes to each of the masters in the sequence till it reaches a requesting
master.
 The master then receives the grant signal. It activates the busy line and gains the control of
the bus.
 The priority is decided by the position of the requesting master in the sequence.

Polling:
 In polling schemes, a set of address lines is driven by the controller, to address each of the
masters in sequence.
 When a bus request is received from a device by the controller, it generates the address on the
address lines.
 If the generated address matches with that of the requesting masters, the controller activates
the BUSY line.

Independent Priority
 In this scheme each master has a pair of Bus request and Bus grant lines and each pair has a
priority assigned to it.
 The priority decoder selects the highest priority request and asserts the corresponding bus
grant signal.
 Synchronization of the clocks must be performed once a Master is recognized.
 Master will receive a common clock from one side and pass it to the controller which will
derive a clock for transfer.
 Due to separate pairs of bus request and bus grant signals, arbitration is fast.