This article has been accepted for inclusion in a future issue of this journal.
Content is final as presented, with the exception of pagination.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
A Continuous-Time Delta-Sigma Modulator
Using ELD-Compensation-Embedded SAB
and DWA-Inherent Time-Domain Quantizer
Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Member, IEEE, Chang-Tsung Fu,
and Tsung-Hsien Lin, Senior Member, IEEE
Abstract—This paper presents an energy-efficient third-order
3 bit continuous-time delta-sigma modulator (CTDSM). In this
work, several architectural and circuit techniques are adopted to
facilitate a low-power modulator. In the loop filter design, a single-
amplifier biquad (SAB) topology is incorporated to realize the
desired transfer function. With the SAB architecture, only two
amplifiers are needed for implementing a third-order CTDSM.
Furthermore, in the proposed SAB, the excess-loop-delay (ELD)
compensation is implemented without using an extra summing
circuit. For the 3 bit quantizer, a time-domain quantizer is pro-
posed, where the data-weighted-averaging function is embedded
in this quantizer to mitigate the nonlinearity issue due to the mis-
match of digital-to-analog converter (DAC) unit cells. Fabricated
in a 90 nm CMOS technology and clocked at 300 MHz sampling
frequency, the proposed SAB-based modulator achieves a 67.2 dB
SNDR and a 69.3 dB SNR in an 8.5 MHz signal bandwidth. The
overall CTDSM dissipates 4.3 mW and achieves a figure-of-merit
of 135 fJ/conversion-step.
Index Terms—Delta-sigma modulation, excess loop delay,
single-amplifier biquad, quantizer.
I. I NTRODUCTION
D ELTA-SIGMA modulators (DSMs) have been a popular
analog-to-digital converter (ADC) architecture in various
applications, such as in sensor interfaces and wireless systems.
For high-resolution and wide-bandwidth applications, the
continuous-time delta-sigma modulator (CTDSM) is a good
candidate for realizing the ADC. Comparing to a discrete-time
delta-sigma modulator (DTDSM), the CTDSM is favored
owing to its relaxed integrator design requirement and inherent
antialiasing filtering characteristic. Still, to achieve a good SNR
performance (e.g., > 11 bits) with a wide signal bandwidth
(∼ 10 MHz), the modulator usually employs a high-order
loop filter, a multibit quantizer, and needs to operate at a
high sampling frequency. Optimization of the loop filter and
quantizer from system to circuit design is crucial in designing
a low-power CTDSM.
Manuscript received May 18, 2015; revised December 01, 2015; accepted
February 07, 2016. This paper was approved by Associate Editor Andrea
Baschirotto. This work was supported in part by NTU, in part by Intel-NTU
Connected Context Computing Center (ICCC), in part by Intel Corporation,
and in part by the Ministry of Science and Technology (MOST), Taiwan.
C.-H. Weng, T.-A. Wei, and T.-H. Lin are with the Department of Electrical
Engineering, Graduate Institute of Electronics Engineering, National Taiwan
University, Taipei 106, Taiwan (e-mail: thlin@ntu.edu.tw).
E. Alpman and C.-T. Fu are with Intel, Hillsboro, OR 97124 USA.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2016.2532345
0018-9200 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
In high-order CTDSMs, several design techniques are pre-
sented in prior publications to facilitate low-power operation.
For example, in the modulators reported in [1] and [2], some
stages of the loop filter are implemented with passive resistor–
capacitor (RC) networks, instead of using active circuits to
realize the entire loop filter. In [1], the summing of the input
and feedback signals is performed in the current or charge
domain at the input of the modulator; the summed current then
charges a capacitor to realize a first-order integration function.
However, replacing the active op-amp integrator with a pas-
sive RC circuit implies that the signal summing takes place at
a nonvirtual-ground node. As a result, the output of feedback
digital-to-analog converter (DAC) may experience a large sig-
nal swing, which increases the design effort on the feedback
current DAC. Furthermore, without a virtual short node, the
driving capability requirement on the previous stage becomes
more demanding as the feedback DAC now directly loads
the preceding integrator stage. In [2], the modulator adopts a
hybrid loop filter topology that consists of active-RC, gm-C,
and passive RC networks to implement a fifth-order modulator.
The integration function realized by the passive network leads
to additional parasitic poles and weakens the noise-shaping
characteristic of the modulator.
To reduce the number of active amplifiers used in a modula-
tor, several works exploited the single-amplifier biquad (SAB)
topology to realize the loop filter [3]–[7]. By incorporating
proper passive device networks, the SAB can realize a higher
order transfer function with only one amplifier, which poten-
tially reduces the modulator power consumption. However, the
SAB architecture inherently comes with fewer virtual ground
nodes; its design flexibility in realizing a given transfer function
is more restricted. In addition, implementing the feedforward
path and excess-loop-delay (ELD) compensation in a SAB-
based modulator becomes more difficult. Although these tasks
may be accomplished by introducing an additional summing
amplifier, this extra amplifier diminishes the benefit of the SAB
topology. To avoid the power consumption penalty of an active
summing amplifier, passive summers can be adopted. However,
the signal swing at the loop filter output usually contains the
majority of the input signal. Large signal swing complicates the
design of the preceding-stage op-amp and feedback DAC in the
passive summer approach.
The other important building block in a low-power CTDSM
is the quantizer, which is typically a multibit implementation in
a wide-bandwidth high-performance system. The conventional
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
2 IEEE JOURNAL OF SOLID-STATE CIRCUITS
Fig. 1. Architecture of the initial feedforward/feedback hybrid third-order
CTDSM.
flash-type quantizer can operate at a high sampling frequency.
However, both the hardware and the power consumption grow
exponentially with the resolution. Several solutions are pro-
posed to address this issue, such as successive-approximation-
register (SAR) quantizer [12], [13], two-step quantizer [15],
VCO-based quantizer [8]–[11], and time-to-digital converter
(TDC) [14]. Considering the data-weighed-averaging (DWA)
function among all types of quantizers, the VCO-based quan-
tizer can achieve barrel-shifting operation with simple digital
hardware and low latency since the ring oscillator can provide
integration and modulus functions on a phase-domain signal.
In this work, several architecture and circuit techniques are
proposed to design a low-power CTDSM. In the loop filter, the
SAB technique is applied. The proposed SAB-based loop filter
incorporates ELD compensation and proper feedforward paths
to realize the desired transfer function. In the quantizer, a multi-
bit time-domain quantizer operating in a barrel-shifting manner
is proposed, which effectively realizes a DWA-embedded TDC.
This paper is organized as follows. Section II presents the mod-
ulator architecture and system-level design of the proposed
SAB-based loop filter. Section III describes circuit imple-
mentation details. Section IV provides measurement results.
Section V gives conclusion for the implemented work.
II. SAB-BASED L OOP F ILTER
A. Modulator Architecture
Fig. 1 shows the initial system-level block diagram of
the CTDSM design. This modulator targets a bandwidth of
8.5 MHz with an SNDR around 70 dB and it employs a third-
order, single-loop DSM with a 3 bit quantizer. The loop filter
adopts a hybrid feedforward and feedback topology. The feed-
forward paths f1 and f2 can facilitate smaller internal swings,
which helps to lower the hardware design requirements of asso-
ciated integrators. Instead of using a single feedforward path f1
to realize the whole s−1 term in the transfer function, the feed-
back path b2 contributes to partial s−1 term that enables a better
system stability. The purpose of b3 path is to realize the ELD
compensation. The local feedback path fb along with the sec-
ond and third integrators implements a resonator, which further
optimizes the in-band quantization noise. The noise transfer
function of the system shown in Fig. 1 can be described by the
following equations:
 3  SAB resonator, the coefficients of the s−1 and s−2 terms are
Vo s + ωn2 s a2 a3 f b
NTF (s) = = ; ω2 = ;
e As3 + Bs2 + Cs + D n T2
A = (b3 · e−td + 1); B = (a3 b1 b2 + a1 b1 f1 ) · e−td /T
Fig. 2. Third-order feedforward/feedback hybrid CTDSM implemented with
three integrators [26].

C = a2 a3 fb + a1 a2 b1 f2 · e−td + a2 a3 b3 fb · e−td

+a2 a3 b1 b2 f2 fb · e−td /T 2
 
D = a1 a2 a3 b1 +2a2 a23 b1 b2 fb +a1 a2 a3 b1 f1 fb ·e−td/T 3 .
(1)
In (1), td is the delay contributed by the loop filter and
quantizer. The notch frequency is adjustable by tuning the coef-
ficients of second and third integrators, and local feedback
path (fb ).
For the third-order CTDSM shown in Fig. 1, the loop filter is
usually realized with three integrators; one active-RC integrator
attains a first-order integration function and the other two inte-
grators with a feedback resistor realize the resonator function.
All signal components corresponding to first-, second-, and
third-integration paths (called s−1 , s−2 , s−3 terms hereafter)
and ELD compensation signals are summed up in the last-stage
integrator and then fed to the input of the quantizer. Fig. 2 illus-
trates a CTDSM implementation example that employs three
integrators to realize the hybrid feedforward and feedback loop
filter [26]. This design adopts a local feedforward path (via
RFF ) to replace one of DACs; meanwhile, the DAC2 path is
kept to implement the s−1 and ELD compensation terms. In
short, to implement all these design attributes, three individual
integrators are employed.
To reduce the number of op-amps used in the modulator,
instead of the direct three-integrator implementation, the pro-
posed loop filter adopts the SAB topology with a twin-T filter
to realize the resonator function. While the advantage of reduc-
ing one op-amp is apparent, there are several major design
issues in a SAB-based loop filter. First, one less op-amp implies
one less virtual ground node available for signal summing.
Most prior SAB-based loop filters still mandate either a pas-
sive summer [3]–[5] or an active summing amplifier [6] for
signal summation (i.e., summing of signals from paths f1 ,
f2 , b3 , and third-integrator output). A passive summer usually
leads to signal attenuation, while an active summing amplifier
takes extra power. Either active or passive summer implemen-
tation compromises the advantages of adopting the SAB-based
modulator.
Second, considering the transfer function of a twin-T fil-
ter (from the input of the twin-T filter to its output) of an
tightly coupled and cannot be determined independently [3],
which leads to severe constraint in designing and optimizing
the loop filter. One further drawback relating to the previous
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
WENG et al.: CTDSM USING ELD-COMPENSATION-EMBEDDED SAB AND DWA-INHERENT TIME-DOMAIN QUANTIZER
Fig. 3. (a) System-level view focusing on the second- and third-stage inte-
grators with associated feedforward/feedback and ELD compensation signals;
(b) corresponding SAB implementation with the twin-T filter.
two issues is that the ELD compensation design becomes more
challenging. The feedback network of the twin-T filter is dif-
ferent from that of a single active-RC integrator. The technique
of reusing the virtual ground node of the last-stage integrator
to realize ELD compensation is no longer feasible in the SAB-
based topology [17], [22]. In other words, an additional summer
seems indispensable for the ELD compensation.
To address the aforementioned issues, a new twin-T topology
for SAB, shown in Fig. 3, is proposed in this work. In Fig. 3(a),
the system-level view focusing on the second- and third-stage
integrators with associated feedforward/feedback and ELD
compensation signals is shown, while Fig. 3(b) depicts the cor-
responding SAB implementation with the twin-T filter. In the
proposed realization, an additional resistor RE in series with
C3 creates a proportional path, which realizes the f1 path with-
out an explicit summer. As mentioned previously, lacking one
virtual ground node in the SAB-based topology leads to diffi-
culty in injecting feedback DAC current to complete the ELD
compensation loop. In this design, the ELD compensation is
realized by injecting the feedback signal into an intermediate
node between capacitors C2 and C3 (node A of Fig. 3) to gen-
erate the desired compensation term. In this proposed scheme,
benefitting from the filtering capability of the RC network, the
signal fluctuation at node A is considerably smaller than that at
the loop filter output. Therefore, the DAC2 design requirement
is relaxed. Comparing to prior SAB-based modulators [3]–[7],
this design does not use any active or passive summer circuit
to sum all feedforward and feedback signals. Another implicit
benefit of this proposed twin-T filter is that the proposed injec-
tion path also provides an additional design freedom to realize a
fast s−1 feedback path, which helps to improve the overall loop
stability.
3
Node A DAC2
C2 C3 RE
R3 Partial s–1 &
Vo,op1 RX Ry
C1 ELD path
CX VLP
R2
V i R1 Dout
OP1 OP2
s–1,s–2 and s–3 terms
DAC1
Fig. 4. Proposed realization of the SAB-based third-order CTDSM with a 3 bit
quantizer.
Fig. 5. Simulated voltage swings at node A (of Fig. 4) with different values of
C2 /C3 .
Finally, the overall third-order CTDSM is shown in Fig. 4. It
is composed of a first-order integrator followed by the proposed
SAB-based resonator, which embeds the ELD compensation.
The proposed CTDSM adopts a multibit time-domain quan-
tizer, which is consisted of a voltage-to-time converter (VTC)
and a circular TDC (CRTDC). The time-domain quantizer will
be described in Section III-C.
B. Design Considerations
To transform the architecture of Fig. 1 into circuit-level
implementation shown in Fig. 4, several design considerations
must be carefully evaluated. Considering the input stage of the
modulator, the first feedback DAC (DAC1 ) and the input resis-
tors (R1 ) typically set the thermal noise floor of the modulator.
Therefore, they are designed to meet the noise requirement.
In the subsequent SAB-based resonator, the DAC2 signal is
injected into a node between C2 and C3 (node A), which is
not a virtual ground node. The signal swing at this node affects
the current accuracy of DAC2 , which introduces nonlinearity to
the modulator. Therefore, the magnitude of signal swing at this
node should be carefully optimized for a given linearity require-
ment. Here, the ratio between C2 and C3 is taken as a design
parameter. The voltage swing at node A is examined by vary-
ing the C2 /C3 value and is plotted in Fig. 5. As the value of
C2 /C3 increases, the voltage swing at node A decreases, which
relaxes the design requirement of DAC2 . In the proposed SAB-
based loop filter, the value of C3 is first determined by the value
of s−2 term; next, the chosen C2 /C3 value determines C2 and
Cx . Considering the voltage swing at node A and total capacitor
area, the value of C2 /C3 is chosen as 2 in this design. The RC
network formed by components Rx , Ry , C2 , and C3 determines
the notch frequency ωn (= 1/ Rx Ry C2 C3 ). The resistor RE ,
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
4 IEEE JOURNAL OF SOLID-STATE CIRCUITS
Fig. 6. Fast path realized by DAC2 helps to boost loop filter gain at high frequency and extend the bandwidth.
which is in series with C3 , serves to accomplish the ELD com-
pensation (path b3 in Fig. 1), and attains partial coefficient for
the s−1 term with the DAC2 current.
In most prior SAB-based CTDSMs, the loop filter usually
adopts the multiple feedforward topology to reduce internal
swing and lower design complexity on feedback paths [3]–[7].
However, two feedback paths are still required to implement the
desired transfer function. One feedback path goes through the
whole loop filter and the other one is for ELD compensation. In
a multiple feedforward modulator, the s−1 term usually suffers
from longer phase delay comparing to that of a multiple feed-
back modulator. The excess phase shift of the s−1 term mainly
comes from two sources; one is the finite GBW of the first
integrator and the other is the summing operation ahead of the
quantizer. The prolonged phase shift of the s−1 term degrades
the stability of the modulator. To mitigate this effect, the op-
amp located in this critical path has to consume more power in
order to minimize the phase. In [20], this issue is alleviated by
adopting a feedback path that goes through the last-stage inte-
grator to realize the s−1 term to minimize the parasitic phase
shift.
The same principle is applied in this work, where a fast s−1
term is realized by injecting the feedback signal via DAC2 .
Since the DAC2 path only experiences the delay of op-amp2 ,
this DAC2 path partially realizes a fast s−1 term with less
propagation delay and mitigates the roll-off rate of the loop
filter gain response. The benefit of the proposed topology
can be observed from Fig. 6, where the gain responses of
loop filter transfer function H(s) with and without DAC2 are
compared. The transfer functions of H(s) without DAC2 is
defined as VLP (s)/Vb1 (s), while H(s) with DAC2 is defined
as VLP (s)/Vb1 (s) + VLP (s)/Vb2 (s). As seen from Fig. 6, with
the fast path realized by DAC2 , the gain response of H(s) rolls
off at a slower rate than that of the H(s) without DAC2 path.
This implies that the proposed loop filter can use an op-amp
designed with a relaxed GBW since the proposed SAB-based
modulator with the assistance of DAC2 path is more tolerant to
delay.
C. Comparison
In order to evaluate the resonator behavior realized with
the proposed SAB-based topology, we compare the proposed
SAB-based resonator to that implemented with a conventional
two-active-RC-integrator architecture. Three resonator cases
are studied: 1) conventional two-integrator resonator with ideal
op-amps (modeled with an infinite GBW); 2) conventional two-
integrator resonator with practical op-amps (modeled with a
finite gain bandwidth, GBW = 2 × fs ); and 3) the proposed
SAB-based resonator with a practical op-amp (modeled with a
finite GBW = 2 × fs ). The adopted op-amp model is consisted
of voltage control current source, single pole implemented with
resistor and capacitor, and ideal output buffer. Among these
three cases, case (1) represents the ideal design. These res-
onators are all designed to place a notch at 6.5 MHz in the
overall modulator NTF.
Fig. 7 shows the three cases simulated for different types of
resonators and Fig. 8 plots the magnitude and phase responses
for the corresponding simulation results. Fig. 8(a) shows that
the quality factor of the peaking (corresponding to notch in the
modulator NTF) in the SAB-based resonator is slightly lower
than that attained by the two-op-amp resonators. A lower qual-
ity factor may lead to a worse notch performance. However, in
a practical circuit-level design considering device noise, the in-
band noise is usually dominated by the circuit noise, instead
of the quantization noise. Therefore, the design requirement
on quality factor of the notch is less crucial. Also observed in
Fig. 8(a), compared to the two-integrator resonator with a finite
GBW, the SAB-based resonator exhibits a less steep roll-off
at higher frequencies, which implies that it has a wider band-
width. Note that the gain response of the SAB-based resonator
is close to that of the ideal resonator (adopting op-amps with
infinite GBW). Benefited from only single op-amp used in a
SAB-based resonator, the latency of the signal flows is reduced
and wider unity gain bandwidth can be achieved.
In terms of phase response behaviors, Fig. 8 shows the plots
of simulated phase for the three resonator cases. The SAB-
based topology induces less phase shift compared to that of the
practical conventional two-integrator architecture, and is again
behaving similar to the ideal case. This is mainly attributed to
the shorter path delay as only one op-amp is used in the res-
onator. In short, the attribute of wider resonator bandwidth may
relax the op-amp design requirement for a given design target.
Next, we evaluate the overall modulators. Two cases, shown
in Fig. 9(a), a conventional third-order CTDSM and the pro-
posed SAB-based CTDSM, are studied. The conventional
three-integrator CTDSM (from Fig. 2) is designed first, and
then the SAB-based modulator (from Fig. 4) is derived by
following the design guideline discussed in Section II-A. In
both cases, op-amps with the same finite GBW(= 2 × fs ) are
utilized in the system simulation. The simulated magnitude
responses of the loop filter (H(s)) and STF are shown in
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
WENG et al.: CTDSM USING ELD-COMPENSATION-EMBEDDED SAB AND DWA-INHERENT TIME-DOMAIN QUANTIZER
Fig. 7. Three cases for comparison with two resonators: (a) conventional resonator; (b) SAB-based resonator. Case 1: resonator (a) with OPideal (60 dB dc gain
and infinite GBW); Case 2: resonator (a) with OPmodel : (60 dB dc gain and 2 × fs finite GBW); Case 3: resonator (b) with OPmodel (60 dB dc gain and
2 × fs finite GBW).
Fig. 8. Comparison of (a) magnitude responses and (b) phase responses for three resonator cases.
Fig. 9(b) and(c), respectively. In both the conventional archi-
tecture and proposed loop filter, the dominating term of system
stability, first-order term, is achieved with feedback DAC2 with
RE and only goes though the last-stage op-amp. Therefore,
the loop filter and STF frequency responses of the SAB-based
CTDSM are similar to those of the conventional three-op-amp
modulator. The similarity between two modulators in both plots
validates the design of transforming the original modulator into
the proposed one.
In short, in a conventional three-integrator CTDSM, the
design of the intermediate integrator stage, although relatively
relaxed compared to those of the first- and last-stage integra-
tor, still demands an op-amp GBW of at least larger than fs /2
[26], [28]. This integrator still consumes a notable amount
of power. With the SAB-based resonator, a high-order loop
filter is achieved with fewer active circuits. Using fewer cir-
cuits not only lessens the latency contributed by the loop filter
but also relaxes the GBW design requirement on the circuits
along the signal path. Furthermore, the proposed SAB architec-
ture can achieve the resonator function and ELD compensation
concurrently with only single op-amp where these two func-
tions are usually implemented with separate circuit blocks in a
conventional SAB-based resonator.
Considering the STF peaking in proposed SAB-based work
[shown in the right of Fig. 9(a)], with the assistance of feedback
path DAC2 , part of the s−1 term goes through the inner loop
5
consisted of OP2 and DAC2 . Therefore, this design has lower
signal peaking effect than that of the multiple-feedforward
topology. Although the feedforward term contributed by RE
still results in an elevated STF peaking than that of the multiple-
feedback topology, the same feedforward path achieved by RE
helps to lower the signal swing of OP1 and reduce the num-
ber of DACs required to realize the entire modulator including
the ELD compensation. Overall, the proposed hybrid modulator
achieves a good compromise among STF peaking, magnitude
of internal swing, and hardware complexity on feedback paths.
III. C IRCUIT I MPLEMENTATION
A. Architecture of the Proposed Modulator
Fig. 10 shows the detailed block diagram of the imple-
mented CTDSM. It features a SAB-based third-order modulator
with a 3 bit CRTDC [21]. Benefited from the proposed ELD-
embedded SAB topology, only two op-amps are needed to real-
ize the third-order modulator. For the quantization operation, a
time-domain architecture is adopted; a VTC first converts the
loop filter output (VLP ) to a pulse signal, then the CRTDC dig-
itizes the pulse signal to digital codes. Meanwhile, the CRTDC
shuffles these output codes in a barrel-shifting manner, which
helps to suppress the nonlinearity due to mismatch of DAC
unit cells. To compensate for PVT variations, the loop filter
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
6 IEEE JOURNAL OF SOLID-STATE CIRCUITS
Fig. 9. Comparison of frequency responses of the proposed SAB-based and
conventional third-order modulators. (a) Two modulator topologies under com-
parison. (b) Plots of loop filter (H(s)) frequency responses. (c) Plots of STF
frequency responses.
Fig. 10. Block diagrams of the implemented CTDSM.
coefficients are made programmable by adjusting the capacitor
of the first-stage integrator and feedback currents of DAC1 and
DAC2 . To avoid undesired parasitic terms induced by inserting
additional switches into the twin-T network, the compensation
mechanism is not implemented in the SAB-based resonator.
B. Operational Amplifier
The op-amp adopted in this work is shown in Fig. 11. A two-
stage architecture, which is composed of a high-gain path and
a high-speed path, is employed [13], [23]. For the inner input
Gm2 M7 M8
M11 M12
Vbiasp M5 M6 Vbiasp
Von,opa RC CC CC RC V –Gmf
op,opa
VCMFB
M3 M4
Gm1 Vbiasp Vi,opa Vo,opa
Gm1 –Gm2
Vin,opa M1 M2 Vip,opa
Vip,opa Vin,opa
Gmf
VB
M9 M10
Rbias Rbias
Fig. 11. Left: circuit schematic of the operational amplifier; right: its equivalent
model.
stage, instead of the conventional cascode topology, the com-
pound transistor pairs (M1 /M3 and M2 /M4 ) are adopted. The
body voltages of M3 /M4 and M5 /M6 are biased at a separate
dc voltage Vbiasp to reduce their threshold voltages and assist
M1 /M2 and M7 /M8 pairs operating in the saturation region
[24]. This pseudocascode topology achieves a better dc gain
without consuming large overdrive voltage. The bias voltage
Vbiasp is generated by a simple replica biasing circuit.
For the high-speed path, transistors M9 and M10 serve as
the input pair where the input signals (Vin,opa /Vip,opa ) are ac-
coupled to the gate terminals. This feedforward path provides
additional trans-conductance at high frequency which extends
the amplifier bandwidth. Fig. 11 also shows the equivalent
model of this dual-path amplifier. Gm1 is formed by the com-
pound transistor pairs M1 /M3 and M2 /M4 ; Gm2 is composed
of transistors M11 and M12 ; Gmf is realized by transistors M9
and M10 .
In the proposed CTDSM, both op-amps used in the first-
stage integrator and the subsequent SAB-filter adopt the same
amplifier topology. The dc gains of both amplifiers are close to
60 dB. The GBW of the first and second integrators are 750 and
890 MHz, respectively, and power consumed by the first and
second integrators are 0.665 and 0.95 mW, respectively. In this
design, the delay of the second integrator dominates the phase
of the first-order term (s−1 ), and a wider unity gain bandwidth
is necessary for the second integrator considering the stability
of the modulator. The GBW values are chosen to be sufficiently
high to ensure that the modulator works properly even at worst
corners.
C. Time-Based Quantizer—VTC and CRTDC
A conventional multibit voltage quantizer is comprised of
multiple comparators. The design of these comparators entails
efforts in optimization of power consumption and several non-
idealities, such as mismatch and offset voltage. The offset
voltage mismatch among comparators is known to cause modu-
lator nonlinearity and degrade the SNDR [4]. Furthermore, the
resilience of modulator to nonideality of the quantizer becomes
weaker in low-OSR designs.
In this design, to avoid the aforementioned issues in a multi-
bit quantizer, a time-based quantizer architecture is adopted
[14]. The proposed overall time-based quantizer is composed
of two parts: a VTC and a CRTDC. The VTC converts the
output voltage of the loop filter into a pulse signal; next, the
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
WENG et al.: CTDSM USING ELD-COMPENSATION-EMBEDDED SAB AND DWA-INHERENT TIME-DOMAIN QUANTIZER
Fig. 12. VTC circuit consisted of ramp generator and comparator.
CRTDC digitizes the pulse signal generated by the VTC into
digital codes which represent the loop filter output.
Fig. 12 depicts the circuit schematic of the VTC; it consists
of two comparators and a ramp generator. In Fig. 12, VLP is
the loop filter output; Vref is a reference voltage that is deter-
mined by the lowest voltage of the loop filter output. Vramp is a
triangular-shaped ramp signal that is generated by a ramp gen-
erator circuit. As also illustrated in Fig. 12, by comparing VLP
and Vref with Vramp via the two comparators, two time-domain
edge signals Vpulse+ and Vpulse− are generated, respectively.
These two edges then constitute a pulsewidth that is propor-
tional to the voltage difference between VLP and Vref . In effect,
the VTC acts as a pulsewidth modulation (PWM) circuit that
converts the VLP signal into a pulsewidth signal.
To ensure that the VTC operates as designed, the ramp
generator demands some design considerations. In [14], the
conversion from an analog signal to a pulse signal occupies
nearly a full clock period due to excessive quantization lev-
els; therefore, the ramp signal must also be valid for the full
clock cycle. A switched-current integrator is adopted to realize
the ramp generator, where the tail current of the integrator and
the load capacitor (Cramp ) determines the slope of the ramp
signal. As the ramp signal must be valid for the whole clock
cycle, the ramp generator adopts the class-A architecture, which
is less power efficient. Furthermore, to maintain a stable input
to VTC during one clock period, a sample-and-hold (S/H) cir-
cuit is required before the comparator. Both issues lead to larger
circuit latency and higher power consumption.
In this work, the ramp generator design is based on a single-
ended two-stage operational amplifier. The outer stage of the
proposed ramp generator is a class-AB stage that generates a
linear ramp signal efficiently. Instead of using a whole clock
period for the analog-to-pulse-signal conversion, only a por-
tion of the ramp signal (Vramp ) is adopted for comparison.
Therefore, the linearity of Vramp only needs to be ensured dur-
ing a narrow period. Furthermore, for low-power consideration,
the frontend S/H circuit is eliminated. (The design robustness
of the modulator without S/H circuit is verified by applying
two out-of-band interferences to the modulator in testing, and
is demonstrated in Section IV.) Considering the OSR (∼ 17.6)
in this modulator, the performance loss due to eliminating S/H
circuit is negligible. This has been verified in system analysis
7
Fig. 13. Schematic of the CRTDC.
with simulation (and measurement presented in Section IV).
This design approach not only reduces the quantizer power
consumption but also relaxes the design effort on the prior
stage.
Considering the PVT variations, the characteristics of delay
elements of TDC and ramp generator also vary; these effec-
tively change the quantizer gain. With the 3 bit time-domain
quantizer and 8 dB out-of-band gain adopted in this design, a
±10% gain variation of the quantizer leads to less than 1.4 dB
change in the SQNR. Despite the small degradation, the vari-
ation in the effective quantizer gain is mitigated in this work
by adjusting the value of Cramp shown in Fig. 12 with 4 bit
external control.
To further lower power dissipation, current-gating technique
is employed in the VTC. Since the comparison operation
only occupies a fraction of a clock cycle, powering down the
comparator temporarily in the unused time interval is possi-
ble. However, turning off the whole comparator would lower
the operation speed of the VTC. In this design, only the most
power-hungry part of the comparator, which is the input inverter
stage with the active load, is turned off during the inactive
period. In Fig. 12, the gating transistor M7 serves to discon-
nect partial branches (M1 − M6 ) of the comparator from the
supply voltage when CLK = 0 (CLKB = 1).
Following the VTC, the CRTDC circuit digitizes the
pulsewidth signal formed by the edges of Vpulse+ and Vpulse− .
Fig. 13 shows the CRTDC circuit which replaces the conven-
tional flash-type quantizer. The Vernier TDC-based configura-
tion is adopted with a time resolution of 75 ps. However, in
contrast to a conventional Vernier TDC, the delay cells of the
proposed CRTDC are connected in a circular manner, as illus-
trated in Fig. 13. Furthermore, the input of each delay cell can
serve as a signal entry point by adding a multiplexer to each
delay cell input. As a pulse signal travel through the CRTDC,
the end point of the present pulse signal can be easily identi-
fied by detecting the transition of output codes from 1 to 0. The
subsequent incoming pulse signal would then be injected to the
input of next delay cell to start another conversion operation.
One important advantage of the proposed CRTDC is that
both the mismatches among multiple DAC cells and those
of multiple TDC delay cells are mitigated due to this barrel-
shifting operation. In effect, the CRTDC implements an
inherent data-weighted averaging (DWA) algorithm with little
hardware overhead. Furthermore, with this inherent-DWA oper-
ation, the latency associated with the DWA algorithm is elimi-
nated and the timing constraint on the CRTDC is considerably
relaxed. Comparing to a VCO-based quantizer, the CRTDC
can realize the quantization and DWA functions concurrently
without the assistance of the explicitly preceding ring oscillator.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
8 IEEE JOURNAL OF SOLID-STATE CIRCUITS
Fig. 14. DAC1 circuit for the input stage and DAC driver.
Fig. 15. Chip micrograph.
Fig. 16. Pie chart of the power consumption distribution.
D. DAC Circuits
The noise performance of the DAC feeding back to the input
stage is crucial, as this noise source is not shaped by the mod-
ulator. Fig. 14 depicts the DAC circuit schematic. For linearity
and noise considerations, the cascode topology is adopted to
implement the current cell. The DAC is supplied from a 1.4 V
supply voltage to allow additional headroom to accommodate
the degeneration resistor for suppressing the thermal noise
contributed by the tail current. Two off-chip capacitors (Cext
shown in Fig. 14) are added to filter the thermal noise from
the bias current. The mismatch among the DAC unit cells is
solved by the DWA function inherent in the CRTDC (described
in Section III-C). However, the fast-switching DWA operation
would still induce unwanted current spike at the drain node of
the tail current and result in signal-dependent harmonic tones.
To mitigate this effect, a DAC driver is inserted between the
quantizer output and inputs of DAC cells to control the crossing
point of the DAC control signals (in this case, a low-crossing
signal) and minimize the current spike energy. The associated
waveforms are also illustrated in Fig. 14.
Fig. 17. Output spectrum with the (a) DWA function disabled and (b) DWA
function enabled by configuring the TDC as a CRTDC.
IV. E XPERIMENTAL R ESULTS
The CTDSM incorporating the proposed SAB-based loop
filter and DWA-embedded CRTDC is fabricated in a 90 nm
CMOS process. Fig. 15 shows the chip photo of the imple-
mented modulator. The active part of the proposed design
occupies an area of 0.2 mm × 0.6 mm. The modulator is mostly
operated from a 1.2 V supply, except the input-stage feed-
back DAC which is supplied from a 1.4 V voltage for noise
and linearity consideration, as described in Section III-D. Total
power dissipation of the modulator is 4.3 mW. Fig. 16 shows
the power breakdown of the modulator. The most power con-
suming circuits are op-amp2 , which is used in the SAB-based
resonator, and the quantizer (including VTC and TDC). In this
design, the op-amp2 plays a key role in facilitating both the
ELD compensation path (s0 term) and s−1 term, which largely
determines the modulator stability. Therefore, the op-amp2 is
designed with a higher GBW compared to that of op-amp1 .
On the quantizer, two techniques DWA-embedded CRTDC and
supply-gated VTC are realized to facilitate low-power opera-
tion. However, converting an analog signal to a pulse signal at
a high operating speed of 300 MHz still consumes considerable
amount of power.
For observing the SNDR and SNR performance, a 2 MHz
single-tone input signal with a maximum input voltage of
1.6 Vpp-diff (−4 dBFS) is applied to the modulator. The mea-
sured output spectrum is shown in Fig. 17. Fig. 17(a) and
(b) shows the output spectra with the inherent-DWA func-
tion disabled (the TDC is configured as a conventional Vernier
TDC by breaking the circular connection) and enabled (as a
CRTDC), respectively. The output spectra show that both the
in-band noise floor and harmonic tones are improved when the
inherent-DWA function is activated with the CRTDC topology.
With an 8.5 MHz signal bandwidth, the maximum SNDR is
67.2 dB. Fig. 18 illustrates the measured plot of the two-tone
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
WENG et al.: CTDSM USING ELD-COMPENSATION-EMBEDDED SAB AND DWA-INHERENT TIME-DOMAIN QUANTIZER
Fig. 18. Measured output spectrum with two-tone inputs.
Fig. 19. Measured STF: (a) frequency span from 800 kHz to 150 MHz and
(b) close-up plot showing a maximum peaking of 6.3 dB.
test, where the frequencies of the two sinusoidal input tones are
located at 1.5 and 2 MHz. With −8 dBFS two-tone input sig-
nals, the measured third-order intermodulation distortion (IM3)
is 71 dB below the two tones. The DWA operation results in
signal-dependent switching activities and induces second-order
harmonic tones [4]. In the measured result of Fig. 17(b), the in-
band noise is mainly dominated by the second-order harmonic
tone and it may be caused by the interaction between the off-
set voltage of op-amp and spiking current induced by frequent
switching of DAC cells with the DWA function.
With the hybrid feedforward and feedback topology, the
modulator exhibits some peaking in the STF. This is observed in
measurement shown in Fig. 19. The STF is measured by sweep-
ing the input signal frequency from 800 kHz to 150 MHz. The
measured STF with a frequency span up to 150 MHz is plot-
ted in Fig. 19(a); a close-up plot up to 40 MHz is shown in
Fig. 19(b). The maximum peaking is 6.3 dB at 21 MHz and
close to the value (∼ 7 dB) predicted by the behavior model.
In the proposed time-domain quantizer, the S/H circuit,
which is typically required before the VTC, is eliminated for
low-power consideration. To test the robustness of this design
approach, two out-of-band signals at 11.5 and 21 MHz with
−11 dBFS amplitude [tones A and B in Fig. 20(a)] are injected
9
Fig. 20. Measured out-of-band linearity (a) with two out-of-band tones at 11.5
and 21 MHz and (b) with two out-of-band tones at 20 and 42 MHz.
Fig. 21. SNR/SNDR versus normalized input signal level.
into the modulator to observe the in-band noise floor and the
out-of-band linearity. As shown in Fig. 20(a), the second-order
intermodulation tone located at 9.5 MHz is −69 dBFS and the
third-order intermodulation tone at 2 MHz is −86 dBFS. The
noise floor remains at a level similar to that of Fig. 17(b). To test
the immunity to blocker signals at even higher frequencies, two
input signals of 20 and 42 MHz with −11 dBFS [tones A and B
in Fig. 20(b)] are applied to the modulator. Fig. 20(b) shows that
the measured output spectrum and the third intermodulation
tone at 2 MHz is −75.5 dBFS. As these intermodulation levels
are low and the noise floor remains similar to that without high-
frequency interferers, the performance loss due to eliminating
the S/H circuit is insignificant.
Fig. 21 shows the measured SNR and SNDR versus the
normalized input amplitudes. The modulator achieves 73 dB
dynamic range (DR) in 8.5 MHz signal bandwidth, and the peak
SNR and peak SNDR are 69.3 and 67.2 dB, respectively.
Table I summarizes the measured chip performance and com-
pares with other CTDSM designs targeting at similar signal
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE JOURNAL OF SOLID-STATE CIRCUITS

TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON

FoM = Power/(2 × Bandwidth × 2((Peak SNDR-1.76)/6.02) ).

Conv.: loop filter implemented with active-RC integrators.
TD: time-domain quantizer.
BG*: circuit block for DAC linearization is implemented with digitally estimated auxiliary DAC and background operation.
FG*: circuit block for DAC linearization is implemented with post lookup table and foreground operation.

bandwidth requirement. The presented CTDSM incorporat- R EFERENCES

ing the proposed techniques achieves an FoM value of 135
fJ/conversion-step, where the FoM is defined as power/(2 ×
band width × 2((Peak SNDR-1.76)/6.02) ).
V. C ONCLUSION
In this paper, a low-power CTDSM is demonstrated. The
proposed CTDSM incorporates two major architectural innova-
tions: a new SAB-based architecture with ELD compensation
and DWA-embedded time-domain quantizer. The SAB-based
loop filter enables a low phase shift modulator and relaxes the
requirement on the op-amp design. Furthermore, the ELD com-
pensation is accomplished by injecting the feedback signal into
the twin-T filter without requiring additional active circuits. On
the quantizer design, a time-domain architecture is adopted.
The CRTDC configured in a barrel-shifting manner provides
an inherent DWA function, which helps to suppress the nonlin-
earity caused by the mismatch of DAC unit cells as well as the
TDC delay cells. The current-gating technique applied to the
VTC (PWM circuit) effectively reduces the power consumption
of the proposed quantizer.
Targeting at a signal bandwidth of 8.5 MHz, the realized
CTDSM incorporating these techniques achieves a peak SNDR
of 67.2 dB while consuming only 4.3 mW. The resulted FoM is
135 fJ/conversion-step, which is comparable to other state-of-
the-art designs in similar CMOS technology.
[10] K. Reddy et al., “A 16-mW 78-dB SNDR 10-MHz BW CT ADC using
ACKNOWLEDGMENT
[11] T. Oh, N. Maghari, and U. Moon, “A second-order ΔΣ ADC using noise-
The authors would like to thank the National Chip
Implementation Center (CIC), Taiwan, for chip fabrication.
[1] A. Das, R. Hezar, R. Byrd, G. Gomez, and B. Haroun, “A 4th-order
86 dB CT ΔΣ ADC with two amplifiers in 90 nm CMOS,” in IEEE
Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2005,
pp. 496–497.
[2] T. Song, Z. Cao, and S. Yan, “A 2.7-mW 2-MHz continuous-time ΣΔ
modulator with a hybrid active-passive loop filter,” IEEE J. Solid-State
Circuits, vol. 44, no. 2, pp. 330–341, Feb. 2008.
[3] K. Matsukawa, Y. Mitani, M. Takayama, K. Obata, S. Dosho, and
A. Matsuzawa, “A fifth-order continuous-time delta-sigma modulator
with single-opamp resonator,” IEEE J. Solid-State Circuits, vol. 45, no. 4,
pp. 697–706, Apr. 2010.
[4] K. Matsukawa et al., “A 69.8 dB SNDR 3rd-order continuous time
delta-sigma modulator with an ultimate low power tuning system for a
worldwide digital TV-receiver,” in IEEE Custom Integr. Circuits Conf.,
Sep. 2010, pp. 19–22.
[5] K. Matsukawa, K. Obata, Y. Mitani, and S. Dosho, “A 10 MHz BW 50
fJ/conv. continuous-time ΔΣ modulator with high-order single opamp
integrator using optimization-based design method,” in IEEE Symp. VLSI
Circuits Dig. Tech. Papers, Jun. 2012, pp. 160–161.
[6] R. Zanbaghi, P. K. Hanumolu, and T. S. Fiez, “An 80-dB DR, 7.2-
MHz bandwidth single opamp biquad based CT modulator dissipating
13.7-mW,” IEEE J. Solid-State Circuits, vol. 48, no. 2, pp. 1–15,
Feb. 2013.
[7] H. Chae, J. Jeong, G. Manganaro, and M. P. Flynn, “A 12 mW low power
continuous-time bandpass ΔΣ modulator with 58 dB SNDR and 24 MHz
bandwidth at 200 MHz IF,” IEEE J. Solid-State Circuits, vol. 49, no. 2,
pp. 405–415, Feb. 2014.
[8] M. Z. Straayer and M. H. Perrott, “A 10-bit 20 MHz 38 mW 950 MHz
CT ΣΔ ADC with a 5-bit noise-shaping VCO-based quantizer and DEM
circuit in 0.13 µ CMOS,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers,
Jun. 2007, pp. 246–247.
[9] M. Park and M. H. Perrott, “A 78 dB SNDR 87 mW 20 MHz band-
width continuous-time delta-sigma ADC with VCO-based integrator and
quantizer implemented in 0.13 µm CMOS,” IEEE J. Solid-State Circuits,
vol. 44, no. 12, pp. 3344–3358, Dec. 2009.
residue-cancelling VCO-based quantizer,” IEEE J. Solid-State Circuits,
vol. 47, no. 12, pp. 2916–2927, Dec. 2012.
shaped two-step integrating quantizer,” IEEE J. Solid-State Circuits,
vol. 48, no. 6, pp. 1465–1474, Jun. 2013.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
WENG et al.: CTDSM USING ELD-COMPENSATION-EMBEDDED SAB AND DWA-INHERENT TIME-DOMAIN QUANTIZER
[12] M. Ranjbar, A. Mehrabi, O. Oliaei, and F. Carrez, “A 3.1 mW continuous-
time ΔΣ modulator with 5-bit successive approximation quantizer for
WCDMA,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1479–1491,
Aug. 2010.
[13] H.-C. Tsai, C.-L. Lo, C.-Y. Ho, and Y.-H. Lin, “A 64-fJ/conv.-step
continuous-time ΣΔ modulator in 40-nm CMOS using asynchronous
SAR quantizer and digital ΔΣ truncator,” IEEE J. Solid-State Circuits,
vol. 48, no. 11, pp. 2637–2648, Nov. 2013.
[14] V. Dhanasekaran et al., “A 20 MHz BW 68 dB DR CT ΔΣ ADC based
on a multi-bit time-domain quantizer and feedback element,” in IEEE
Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2009,
pp. 174–175.
[15] O. Rajaee et al., “A 79 dB 80 MHz 8X-OSR hybrid delta-sigma/pipeline
ADC,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2009,
pp. 74–75.
[16] M. S.-W. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asyn-
chronous ADC in 0.13-µm CMOS,” IEEE J. Solid-State Circuits, vol. 41,
no. 12, pp. 2669–2680, Dec. 2006.
[17] M. Vadipour et al., “A 2.1 mW/3.2 mW delay-compensated GSM/
WCDMA sigma-delta analog-digital converter,” in IEEE Symp. VLSI
Circuits Dig. Tech. Papers, Jun. 2008, pp. 180–181.
[18] M. Keller, A. Buhmann, J. Sauerbrey, M. Ortmanns, and Y. Manoli,
“A comparative study on excess-loop-delay compensation techniques for
continuous-time sigma-delta modulators,” IEEE Trans. Circuits Syst. I,
Reg. Papers, vol. 55, no. 11, pp. 3480–3487, Dec. 2008.
[19] M. Ranjbar and O. Oliaei, “A multibit dual-feedback CT ΔΣ modulator
with lowpass signal transfer function,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 58, no. 9, pp. 2083–2095, Sep. 2011.
[20] W. Yang et al., “A 100 mW 10-MHz BW CT SD modulator with 87 dB
DR and 91 dBc IMD,” in IEEE Int. Solid-State Circuits Conf. (ISSCC)
Dig. Tech. Papers, Feb. 2008, pp. 498–499.
[21] C.-C. Lin, C.-H. Weng, T.-A. Wei, Y.-Y. Lin, and T.-H. Lin, “A
TDC-based two-step quantizer with swapper technique for a multibit
continuous-time delta-sigma modulator,” IEEE Trans. Circuits Syst. II,
Exp. Briefs, vol. 61, no. 2, pp. 75–79, Feb. 2014.
[22] G. Mitteregger, C. Ebner, S. Mechnig, T. Blon, C. Holuigue, and
E. Romani, “A 20 mW 640 MHz CMOS continuous-time ADC with
20 MHz signal bandwidth, 80 dB dynamic range and 12 bit ENOB,” IEEE
J. Solid-State Circuits, vol. 41, no. 12, pp. 2641–2649, Dec. 2006.
[23] P. Shettigar and S. Pavan, “Design techniques for wideband single-bit
continuous-time modulators with FIR feedback DACs,” IEEE J. Solid-
State Circuits, vol. 47, no. 12, pp. 2865–2879, Dec. 2012.
[24] M. Taherzadeh-Sani and A. A. Hamoui, “A 1-V process-insensitive
current-scalable two-stage opamp with enhanced DC gain and settling
behavior in 65-nm digital CMOS,” IEEE J. Solid-State Circuits, vol. 46,
no. 3, pp. 660–668, Mar. 2011.
[25] S. Yan and E. Sanchez-Sinencio, “A continuous-time ΣΔ modulator with
88-dB dynamic range and 1.1-MHz signal bandwidth,” IEEE J. Solid-
State Circuits, vol. 39, no. 1, pp. 75–86, Jan. 2004.
[26] J. G. Kauffman, P. Witte, J. Becker, and M. Ortmanns, “An 8.5 mW
continuous-time ΣΔ modulator with 25 MHz bandwidth using digital
background DAC linearization to achieve 63.5 dB SNDR and 81 dB
SFDR,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2869–2881, Mar.
2011.
[27] P. Witte, J. G. Kauffman, J. Becker, Y. Manoli, and M. Ortmanns, “A
72 dB DR CT ΔΣ modulator using digitally estimated, auxiliary DAC
linearization achieving 88 fJ/conv in a 25 MHz BW,” in IEEE Int. Solid-
State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 154–155.
[28] Y.-S. Shu, J.-Y. Tsai, P. Chen, T.-Y. Lo, and P.-C. Chiu, “A 28 fJ/conv-
step CT ΔΣ modulator with 78 dB DR and 18 MHz BW in 28 nm CMOS
using a highly digital multibit quantizer,” in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, Feb. 2013, pp. 268–269.
Chan-Hsiang Weng received the B.S. degree from
the National Central University, Taoyuan, Taiwan,
and the M.S. and Ph.D. degrees from the National
Taiwan University, Taipei, Taiwan, in 2005, 2008, and
2015, respectively, all in electrical engineering.
From 2008 to 2011, he was a Mixed-Signal Design
Engineer with Airoha Corp., Hsinchu, Taiwan, dur-
ing which time he was involved in the development
of wireless for FM, BT, and audio applications. In
the summer 2013, he was an Intern with Intel Labs,
Portland, OR, USA. He is currently with Mediatek
Corp., Hsinchu, Taiwan, where he has been engaged in the design of mixed-
signal integrated circuits for wireless communications. His research interests
include data converters, temperature sensors, and mixed-signal circuit designs.
Dr. Weng was the recipient of the Intel-NTU Center Fellowship in 2014 and
2015 and the Best Paper Award for the 2015 IEEE VLSI-DAT Symposium.
11
Tzu-An Wei was born in Taipei, Taiwan, in 1987.
He received the B.S. degree from the National
Cheng Kung University, Tainan, Taiwan, in 2011,
and the M.S. degree from the National Taiwan
University, Taipei, Taiwan, in 2014, both in electronic
engineering. His thesis focused on the design
and implementation of low power continuous-time
delta-sigma modulator in wireless communication
receivers.
In 2014, he joined MediaTek Inc., Hsinchu,
Taiwan, where he is involved in mixed-signal cir-
cuits for wireless receivers. His research interests include wide-bandwidth
continuous-time delta-sigma ADC in cellular system.
Erkan Alpman (M’09) received the B.Sc. and M.Sc.
degrees in electrical and electronics engineering from
Middle East Technical University, Ankara, Turkey, in
2003 and 2005, respectively, and the Ph.D. degree in
electrical and computer engineering from Carnegie
Mellon University, Pittsburgh, PA, USA, in 2009.
Since 2009, he has been an Analog Engineer/
Research Scientist with Intel Labs, Hillsboro, OR,
USA, working on analog and mixed signal circuits
and architectures for wired/wireless transceivers in
scaled CMOS processes.
Chang-Tsung Fu received the M.S and Ph.D.
degrees in electrical engineering from the National
Chiao Tung University, Hsinchu, Taiwan, in 2001 and
2009, respectively.
In 2008, he joined Intel Labs, Hillsboro, OR, USA,
as a Research Scientist and has dedicated on criti-
cal component and circuitry path finding on CMOS
RF/analog circuits, RF SoC integration, and design
methodology. In 2015, he joined Intel Radio Product
Development Group, focused on connectivity for
applications including Internet of Things. He cur-
rently holds 8 issued and pending patents and has authored or coauthored
16 papers in first-tier IEEE conferences or journals. His research works
include broadband noise matching theory, CMOS T/R switches, and high-
linearity LNA. His research interests include RF/microwave component design,
RF/analog circuit design, and wireless transceiver system.
Tsung-Hsien Lin (M’03–SM’09) received the B.S.
degree in electronics engineering from the National
Chiao-Tung University, Hsinchu, Taiwan, and the
M.S. and Ph.D. degrees in electrical engineering from
the University of California, Los Angeles, CA, USA,
in 1997 and 2001, respectively.
In 2000, he joined Broadcom Corporation, Irvine,
CA, USA, as a Senior Staff Scientist, where
he was involved in wireless transceiver develop-
ments. In 2004, he joined the Graduate Institute
of Electronics Engineering and the Department of
Electrical Engineering, National Taiwan University, Taipei, Taiwan, where he
is currently a Professor. His research interests include the design of wireless
transceivers, clock and frequency generation systems, delta-sigma modulators,
and transducer interface circuits.
Dr. Lin served on the IEEE Asian Solid-State Circuit Conference (A-SSCC)
Technical Program Committee (TPC) from 2005 to 2011 and was the TPC Vice-
Chair for 2011 A-SSCC. He was a Guest Editor for the IEEE J OURNAL OF
S OLID -S TATE C IRCUITS (JSSC) in 2012 and was an Associate Editor for the
same journal from 2013 to 2015. He has been serving the ISSCC International
Technical Program Committee (ITPC) since 2010, and is in the ISSCC Student
Research Preview (SRP) Committee since 2012. He was the recipient of the
Best Presentation Award for his paper presented at the 2007 IEEE VLSI-DAT
Symposium, and the Best Paper Award at the same Symposium in 2015. He was
also the recipient of the Teaching Excellence Award from the National Taiwan
University in 2007, 2008, and 2014, and Exceptional Teaching Excellence
Award in 2009.