EE695K VLSI Interconnect

Interconnect Delay Models

Basic Circuit Analysis Techniques

Network structures & state Natural response vN(t)

(zero-input response)
• Output response

Input waveform & zero-states Forced response vF(t)

(zero-state response)
For linear circuits: v(t ) = vN (t ) + vF (t )
• Basic waveforms
– Step input
– Pulse input
– Impulse Input
• Use simple input waveforms to understand the impact of
network design

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Basic Input Waveforms

1/
1 T

0 -T/2 T/2
unit step function pulse function of width T unit impulse function

0 t< 0 1  T T  δ(t) : PT (t) when T → 0

u(t)= PT (t ) = u (t + 2 ) − u(t − 2 )
T   δ(t) = 0 for t ≠ 0
1 t≥ 0
singular for t = 0
By definition s.t. for anyζ >0
ζ
∫
t
u (t ) =
− ∞
δ( x ) dx ∫ δ(t)dt =1
−ζ

du ( t )
or d(t) =
dt

Step Response vs. Impulse Response

• Definitions:
– (unit) step input u(t) (unit) step response g(t)
– (unit) impulse input δ(t) (unit) impulse response h(t)
(Input Waveform) (Output Waveform)

du ( t ) dg ( t )
• Relationship δ( t ) = → h (t ) =
dt dt

∫ ∫ h ( x ) dx
t t
u (t ) = δ( x ) dx → g (t ) =
− ∞ 0

• Elmore delay
∞ ∞
TD = ∫ g ' (t )t ⋅dt = ∫ h(t )t ⋅dt
0 0

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Analysis of Simple RC Circuit

R ⋅i ( t ) + v ( t ) = v T ( t ) i(t)
R
d ( Cv ( t )) dv ( t ) vT(t) C v(t)
i (t ) = =C
±

dt dt
dv ( t )
⇒ RC + v (t ) = vT (t ) first-order linear differential
equation with
dt constant coefficients

state
variable
Input
waveform

Analysis of Simple RC Circuit

dv ( t )
zero-input response: RC + v (t ) = 0
dt
1 dv(t) 1 − t RC
(natural response) = − ⇒ v N (t) = Ke
v(t) dt RC

dv ( t )
step-input response: RC + v (t ) = v 0 u (t )
dt
− t
v F ( t ) = v 0 u ( t ) ⇒ v ( t ) = Ke RC + v 0 u ( t )

match initial state: v (0 ) = 0 ⇒ K + v 0 u (t ) = 0

v0u(t)
v0
output response − t RC
for step-input: v ( t ) = v 0 (1 − e ) u (t ) v0(1-eRC/T)u(t)

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Delays of Simple RC Circuit

• v(t) = v0(1 - e-t/RC) under step input v0u(t)

• v(t)=0.9v0 ⇒ t = 2.3RC
v(t)=0.5v0 ⇒ t = 0.7RC

• Commonly used metric

TD = RC (Elmore delay to be defined later)

Lumped Capacitance Delay Model

• R = driver resistance
• C = total interconnect capacitance + loading capacitance
• Sink Delay: td = R·C
N3
Rd

N2 Cload
driver

N+

• 50% delay under step input = 0.7RC

• Valid when driver resistance >> interconnect resistance
• All sinks have equal delay

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Lumped RC Delay Model

t D = R d ⋅C load = R d ⋅(C int + C g )
= R d ⋅(C 0 ⋅L + C g )
• Minimize delay ⇔ minimize wire length

N3
Rd

N2 Cload
driver

N+

Delay of Distributed RC Lines

R R
Laplace VIN VOUT VIN VOUT
Vout(t) Vout(s) C C
Transform
VOUT

1
Vout ( s) = 1.0 DISTRIBUTED
s cosh sRC
e x + e− x 0.5
cosh( x ) =
LUMPED

2
x2 x4 1.0RC 2.0RC time
= 1+ + + ......
2! 4! Step response of distributed and lumped RC networks.
A potential step is applied at VIN, and the resulting V OUT
is plotted. The time delays between commonly used
reference points in the output potential is also tabulated.

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Delay of Distributed RC Lines (cont’d)

Output potential range Time elapsed Time elapsed

(Distributed RC (Lumped RC
Network) Network)
0 to 90% 1.0 RC 2.3 RC
10% to 90% (rise time) 0.9 RC 2.2 RC
0 to 63% 0.5 RC 1.0 RC
0 to 50% (delay) 0.4 RC 0.7 RC
0 to 10% 0.1 RC 0.1 RC

Distributed Interconnect Models

• Distributed RC circuit model

– L,T or Π circuits

• Distributed RCL circuit model

• Tree of transmission lines

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Distributed RC Circuit Models

Distributed RLC Circuit Model

Z0

Z0

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Delays of Complex Circuits under Unit Step Input

• Circuits with monotonic response

1
T50% v(t)
0.5
t
TR

• Easy to define delay & rise/fall time

• Commonly used definitions
– Delay T50% = time to reach half-value, v(T50%) = 0.5Vdd
– Rise/fall time TR = 1/v’(T50%) where v’(t): rate of change of v(t)
w.r.t. t
– Or rise time = time from 10% to 90% of final value
• Problem: lack of general analytical formula for T50% &
TR!

Delays of Complex Circuits under Unit Step

Input (cont’d)

• Circuits with non-monotonic response

• Much more difficult to define delay & rise/fall time

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Elmore Delay for Monotonic Responses

v(t)
1
• Assumptions:
0.5
– Unit step input
– Monotone output response t
T50%
v’(t)

• Basic idea: use of mean of v’(t)

to approximate median of v’(t)
v ( t ) : output response (monotone) t
median ∞
v ' ( t ) : rate of change of v ( t ) of v’(t) TD = ∫ tv' (t )dt
0

(T50%) mean of v'(t)

Elmore Delay for Monotonic Responses

• T50%: median of v’(t), since

T50 % +∞
∫0
v ' (t ) dt = ∫
T50 %
v ' (t ) dt
= half of final value of v (t ) (by def.)

• Elmore delay TD = mean of v’(t)

∞
TD = ∫ 0
v ' ( t ) tdt

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Why Elmore Delay?

• Elmore delay is easier to compute analytically in most cases

– Elmore’s insight [Elmore, J. App. Phy 1948]
– Verified later on by many other researchers, e.g.
• Elmore delay for RC trees [Penfield-Rubinstein, DAC’81]
• Elmore delay for RC networks with ramp input [Chan, T-
CAS’86]
• .....

• For RC trees: [Krauter-Tatuianu-Willis-Pileggi, DAC’95]

T50% ≤ TD

• Note: Elmore delay is not 50% value delay in general!

Elmore Delay for RC Trees

h(t) = impulse response
• Definition
– h(t) = impulse response
– TD = mean of h(t) H(t) = step response
∞
=
∫h(t) ⋅t dt
0

• Interpretation
– H(t) = output response (step process) median ∞
TD = ∫ tv' (t )dt
of v’(t) 0

– h(t) = rate of change of H(t) (T50%) mean of v'(t)

– T50%= median of h(t)

– Elmore delay approximates the median of h(t) by
the mean of h(t)

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Elmore Delay of a RC Tree

[Rubinstein-Penfield-Horowitz, T-CAD’83]
Lemma: when a step input is applied to a RC tree
vi (t ) is monotonic in t for every node i in tree
Proof: ⇔ v 'i (t ) ≥ 0 at every node i (v ' i (t ) = hi (t ))
⇔ impulse response hi (t ) ≥ 0 at every node i
Let hmin (t ) be the min. voltage of any node at t
Apply impulse func. at t=0:
hmin (0+ ) ≥ 0
Assume that hmin (t 0 ) < 0
Then, ∃t1 < t0 s.t. h'min (t1 ) < 0
imin Let node imin achieve hmin (t1 ) at t1
Then, the current from any node i to imin is ≥ 0 at t1
current i→ imin Since hi (t1 ) ≥ hmin (t1 ) & i connects imin via resistors
i Since all currents i → imin charge the capacitor at imin
h'min (t1 ) ≥ 0 ⇒ contradict ion!

Elmore Delay in a RC Tree (cont’d)

Pi : path from input to node i ; si :subtree rooted at i Si j
R jk : resistance of common path
path resistance Rii
Pj ∩ Pk from input to j & k i
Theorem : Elmore delay to node i input
TDi = ∑ Rki Ck Rjk
k
k

dv (t )
Proof : The current to cap. of node i = Ci i
dt
1 − vi (t ) = The voltage drop on Pi = ∑ Rk ⋅(current to all cap' s in Si )
k∈ Pi

= ∑ (current to cap k ) ⋅(common path res. between Pi and Pk )

k

dvk (t ) dv (t )
= ∑ Ck ⋅Rki = ∑ Rki Ck k
k dt k dt
∞ ∞
TDi = ∫ v'i (t )t ⋅dt = vi (t ) ⋅t |∞0 − ∫ v (t)dt
i
0 0
T ∞
= lim [vi (T ) ⋅T −
T→ ∞ ∫ v (t)dt] = lim (v (T ) − 1) ⋅T + ∫ (1 −
0
i
T→ ∞
i
0
vi (t ))dt

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Elmore Delay in a RC Tree (cont’d)

• We shall show later on that Tlim (1 − vi (T )) ⋅T = 0
→ ∞
i.e. 1-vi(T) goes to 0 at a much faster rate than 1/T when T→ ∞

t
• Let f i (t ) = ∫[1 − vi ( x)]dx
0
vi(t)
fi (t ) = ∫[1 − vi ( x)]dx
t
dvk ( x )
f i (t ) = ∫∑ RkiCk
t area
dx 0
0
k dx 1
= ∑ RkiCk v k (t )
k

= ∑ Rki Ck − ∑R ki Ck [1 − vk (t )]
k k t
(1) 0
f i (∞ ) = ∑ RkiCk
k
∞
∴ TDi = lim (1 − vi (T ))T +
T→ ∞ ∫ [1 −
0
vi (t )]dt
= f i (∞ ) = ∑ Rki Ck
k

Some Definitions For Signal Bound Computation

Let Tp = ∑ Rkk C k Recall TDi = ∑ RkiC k

k k

TRi = (∑ R Ck ) Rii 2
ki
k

Then, TRi ≤TDi ≤Tp (since Rkk ≥ Rki & Rii ≥ Rki )

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Signal Bounds in RC Trees

• Theorem
Lower bounds
0 t≥0
TDi
vi (t ) ≥ 1 − t ≥ 0 (non - trivial when t ≥ TDi − TRi )
t + TRi
( T p − TRi ) −t
TDi
1− ⋅e t ≥ T p − TRi
Tp Tp
e
Tp

Upper bounds
TD − t
1− i t≥0
Tp
v i (t ) ≤
(T Di − TRi ) −t
TRi
1− ⋅e t ≥ TDi − TRi
TRi T Ri
e
Tp

Proofs of Signal Bounds in RC Trees

• Lemma: Rii [1 − vk (t )] ≥ Rki [1 − vi (t )] (2)
Proof: Rii ≥ max( Rki , R ji ) R jk ≥ min( Rki , R ji )
∴ Rii ⋅R jk ≥ Rki ⋅R ji
Rii [1 − vk (t )] − Rki [1 − vi (t )]
dv j (t ) dv j (t )
= Rii ∑ R jk C j − Rki ∑ R ji C j
j dt j dt
dv j (t )
= ∑ ( Rii R jk − Rki R ji )C j ≥0
j dt
(Since v j (t ) is monotonic)

• Lemma: Rki [1 − vk (t )] ≤ Rkk [1 − vi (t )] (3)

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Proofs of Signal Lower Bounds in RC Trees

From (1) : TDi − fi (t ) = ∑ RkiCk (1 − vk (t ))
k

From (2) & (3) : TRi [1 − vi (t)] ≤TDi − fi (t ) ≤Tp [1 − vi (t )] (4)

TDi − fi (t ) dfi (t ) TDi − fi (t)
i.e. ≤1 − vi (t ) = ≤
Tp dt TRi
1 1 df (t ) 1
Thus, ≤ ⋅ i ≤
Tp TDi − fi (t ) dt TRi

Integrating from t1 to t2 : (t2 − t1 ) ≤− ln(TDi − fi (t )) |tt12 ≤(t2 − t1 )

Tp TRi
− ( t2 − t1 )
TDi − fi (t2 ) − (t2 − t1 )
(t4-t3)[1-v i(t4)]
≥ ≥e
Tp TRi
i.e. e (5)
TDi − fi (t1 )
Also, since vi (t) is monotonic fi(t4)-fi(t3)
(t4 − t3 )[1 − vi (t4 )] ≤ fi (t4 ) − fi (t3 ) (6)
t3 t4
Let t3 = 0, t4 = t fi (t ) ≥ [1 − vi (t )]⋅t (7)

Proofs of Signal Lower Bounds in RC Trees

From left - half of (4) and (7)
T R i [1 − v i ( t )] ≤ T D i − f i ( t ) ≤ T D i − [1 − v i ( t )] t
TDi TDi
⇒ 1 − v i (t ) ≤ ∴ v i (t ) ≥ 1 −
t + T Ri t + T Ri
Let t3 = t − T p + T Ri t4 = t in (6)
( T p − T R i )[ 1 − v i ( t )] ≤ f i ( t ) − f i ( t 3 ) (8)
Let t1 = 0 and t2 = t3 in left - half of (5)
− t3
T D i − f i ( t3 ) ≤ T D i e
Tp
(9)

From left - half of (4)

T R i [1 − v i (t) ] ≤ T D i − f i ( t ) (10)

( 8 ) + ( 9 ) + (10 ) :
− t3
T p [1 − v i ( t )] ≤ T D i e
Tp

− t3 − ( T p − T Ri ) − t
TDi TDi
∴ v i (t ) ≥ 1 − = 1− ⋅e
Tp Tp Tp
e e
Tp Tp

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Delay Bounds in RC Trees

Lower bounds :
t ≥ TD i − Tp [
1 − vi (t )]
TRi TRi
t ≥ TDi − TRi + TRi ln when vi (t ) ≥ 1 −
Tp [
1 − vi (t )] Tp

Upper bounds :
TDi
t≤ − TRi
1 − vi (t )
TDi TDi
t ≤Tp − TRi + Tp ln when vi (t ) ≥ 1 −
Tp [
1 − vi (t )] Tp

Computation of Elmore Delay & Delay Bounds

in RC Trees

• Let C(Tk) be total capacitance of subtree rooted at k

• Elmore delay
TDi = ∑R
k ∈ pi
k ⋅C (Tk )

upper bound :
Tp = ∑ Rk ⋅C (Tk )
k

lower bound :
C
TRi = ∑ Rki2 ⋅ k
k Rii
* all three formula can be computed in linear tim e recursively in a bottom - up
fashion

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Comments on Elmore Delay Model

• Advantages
– Simple closed-form expression
• Useful for interconnect optimization
– Upper bound of 50% delay [Gupta et al., DAC’95, TCAD’97]
• Actual delay asymptotically approaches Elmore delay as input
signal rise time increases
– High fidelity [Boese et al., ICCD’93],[Cong-He, TODAES’96]
• Good solutions under Elmore delay are good solutions under
actual (SPICE) delay

Comments on Elmore Delay Model

• Disadvantages
– Low accuracy, especially poor for slope computation
– Inherently cannot handle inductance effect
• Elmore delay is first moment of impulse response
• Need higher order moments

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