ELEC 6036 High Performance Computer

Architecture

A Quick Quiz for Revision #1

JUST FOR REVISION during the class – NOT COUNTED
for any assessment.

Time allowed : 12 mins

o This review exercise is solely for your OWN REVISION AND

THUS NO NEED TO SUBMIT the answers.
o Try to attempt each question and then review the suggested
answers afterwards.
o This quick quiz exercise consists of 8 questions. Check it out
yourself.

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True / False Question on Pipelining (for Revision on Mod-1)
Carefully read each of the following statements to decide whether it is True
or False. Write down T for True or F for False for each statement.

[TIPS : Refer to Page 9 of Module-1 notes]

1. With pipelining, the latency of each single instruction

is reduced.
2. Pipeline rate is limited by the shortest pipeline stage.
longest

3. Pipeline stages with unbalanced durations decrease

the speedup.
4. The time required to “fill” and “drain” a pipeline
increases the speedup.
5. Structural hazards occur when two or more pipelined
instructions contend for the same resource (like the
main memory) in a high-performance computer
system.
6. Controls hazards commonly occur for any branch
instruction when a decision is required to be made
only after the condition of the branch instruction is
evaluated.
7. Data hazards occur when an instruction depends on
the result of a previous instruction still in the pipeline.

Answer:
1. F 2. F 3. T 4. F 5. T 6. F 7. T

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