Hardware implementation of an Echo-Canceller for
DVB-T On-Channel Repeaters
Altamura P., Cardarilli G.C. and Re M.
Dept. of Electr. Engineering
University of Rome "Tor Vergata"
Rome, Italy
{g.cardarilli, marco.re} @ ieee.org
Abstract-The necessity to obtain a better area coverage for
services such as terrestrial digital television (DVB-T) is often
obtained by using isofrequency channel repeaters. In this case
the repeater receives at the input part of the transmitted signal
and consequently an echo canceller is requested. The echo
canceller is often based on a loop comprising a complex FIR
filter with variable coefficients, that are calculated from the
autocorrelation function of the received signal. In this paper, a
hardware implementation of an Echo-canceller is presented. A
board based on a Texas Instruments floating-point DSP and an
Altera Cyclone II FPGA has been used for the final prototype.
I. INTRODUCTION
The increasing necessity to obtain a better coverage of the
territory for services like terrestrial digital television (DVB-
T) can be technically difficult and expensive for problems of
topography and co-existence with other operators. Using
isofrequency channel repeaters often may be the only
alternative to get coverage extension in circumstances when
traditional solution cannot be deployed. Single frequency
networks (SFN) can offer an attractive option to extend
coverage with the simple addition of lower-power
transmitters at various sites throughout the desired coverage
area. SFN are more flexible in terms of coverage area and
inherently more fault-resistant than one-transmitter systems,
they are more interference-resistant and also cause less
interference, they also can lower installation costs[1].
The BBC first recognize the potential need for on-channel
repeaters in relation to hole-filling in the coverage of its
Digital Audio Broadcasting service [2].
An on-channel repeater receives and retransmits a signal
on the same channel frequency as it receives, the main
problem is that the repeater receives at the input a fraction of
the transmitted signal making a feedback loop and causing a
loss of quality of transmission because these feedback signals
interfere with the weak signal received by the repeater
causing oscillations and instability with the effect of
distorting (degrading) the output signal; this happens in
particular for unwanted coupling between the receiving and
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Del Re A.
Skytechnology s.r.l.
Rome, Italy
andrea.delre @ sky-team.it
the transmitting antennas [3]. To avoid instability, the
isolation between the input and output antennas of the
repeater must be high, but, in practical situations, perfect
isolation can never be achieved due to the presence of
physical obstacles, such as mountains or buildings, which
reflect transmitted signals generating echoes that are captured
by the receiving antenna.
Considering an isofrequency channel repeater as a simple
amplifier, its impulsive response is simply an impulse with
increased amplitude. When an echo is received by the
repeater another impulse, whose delay regarding the wished
impulse is proportional to the distance from the repeater to
the obstacle which generates that echo, is added to the
original impulse response.
II. ECHO CANCELLATION
In the literature some papers have been presented on echo
cancellation for this kind of application such as in [4-8].
Echo cancellation can be obtained by digital signal
processing techniques to model and remove undesired
feedback signals, one possible approach is space domain
signal processing: adaptive antennas place a null in the
direction of echoes; another approach is time domain signal
processing, implemented by using a filter with complex
coefficients to model and reject echoes.
This approach is adaptive since, if the echoes change,
because of a mutation of the propagation conditions, the
system is able to change the canceller coefficients in order to
eliminate the new spurious echoes.
Echo cancellation techniques are used extensively in
digital signal processing for audio application or for
telephonic networks [9-13], in last years it became possible to
adapt them to digital broadcasting using digital hardware
running at the speed required for DVB.
There are many design tradeoffs such as the selection of
the filter type (FIR or IIR), the selection of a suitable channel
estimation and weight updating algorithms (feedback or
987
 feedforward) which will affect the stability and speed of UHF Inputl 36 MHz Digital Signa Output Signav
convergence. Signal IF Signal (1 4 bit) (echo free)

One of the methods of estimating filter taps is the Least

Mean Square algorithm that consists of minimising the square Figure 1. System Architecture Block Diagram
of the error for tap coefficient adaptation of the echo
canceller, but it needs a compromise between the speed of At reset the FIR filter coefficients are initialized to zero
convergence and signal-to-noise ratio; another algorithms is by the DSP, then the autocorrelation of the signals captured
Fast Recursive Least Squares that estimates autocorrelation of through the FIFOs is computed in order to estimate the
signal and has assured convergence properties, but requires echoes and calculate the new set of FIR filter coefficients to
much greater computational complexity. perform cancellation. This procedure is repeated many times
until the correction is optimal. The DSP is also able to carry
Since DVB-T can use multilevel QAM modulation [14], it out other types of estimate on the input signal such as, for
imposes strict limits on signal-to-noise ratio, therefore to example, automatic gain control useful in the algorithm
achieve faster and more precise tracking of feedback Fast implemented in FPGA. Hardware tests of the final system
RLS algorithm is preferable at the expense of more hardware have been carried out by placing in cascade two equal boards,
resources. in the first one the coefficients of the FIR filter have been set
to arbitrary values in order to generate echoes, the second one
III. HARDWARE IMPLEMENTATION instead works as canceller and it is able to compute the
In this paper a hardware implementation and a fast coefficients in order to cancel the echoes generated by the
prototype for the echo canceller is presented. The method first board. Currently, the number of programmable FIR
adopted to cancel the echoes in our implementation is based filters taps is 240 and considering that the sample-rate is 10
on a closed loop containing a complex FIR filter with MHz, the maximum delay of the cancellable echo is 240 *
variable coefficients which are estimated and updated starting 100 ns = 24 gs that corresponds to a maximum distance from
from the autocorrelation function of output signal. an obstacle equal to (3 * 108* 2.4 * 10-) /2 = 3.6 Km.
In Fig. 1 a block diagram of the architecture of the system A fast prototype of the echo-canceller has been
is shown. The input signal to the echo canceller is a UHF implemented by using a board based on a floating-point DSP
television channel, characterized by a 8 MHz band. This (Texas Instruments TMS320C6713) and an FPGA Altera
signal has been down-converted to a 36 MHz IF (by using a Cyclone II EP2C50F484C7 with 50528 Logic Elements,
suitable analog front end) and then digitized by using a 14 bit 594432 memory bits, 172 embedded multipliers 9-bit
ADC working at 100 MHz (sample rate). The maximum elements. The DSP has been used to implement the
delay of echoes that can be cancelled is called "temporal adaptation algorithm that computes the updated FIR filter
window of correction", it increases with the number of FIR coefficients. The complex filter itself has been implemented
filter's taps and with sample period at which the canceller in the FPGA using 4 real filters generated by Altera's "FIR
works; wider is the temporal window of correction longer is Compiler MegaCore Function", each FIR has 2 sets of
distance from the repeater to the obstacle which can be coefficients and coefficients reload capability, one set of
tolerated. In order to obtain a wider temporal window of coefficients is used for filtering while the other one is written
correction, getting cancellation of echoes caused by far by DSP, periodically DSP writes 14-bit fixed point
obstacles, without excessively increasing the number of coefficients and swaps set of coefficients. DSP-FPGA
filter's taps, the input signal is converted to base-band and interface is based on a COMMAND BUS driven by DSP and
then decimated. a bidirectional DATA BUS for transmitting coefficients or
other parameters from DSP to FPGA or FIFOs content or
In the FPGA this signal is then converted to base-band other statuses from FPGA to DSP. In this situation the
and decomposed in its phase and quadrature components percentage of use of the FPGA resources is of approximately
(both with a 4 MHz band) (Fig. 2 illustrates the Simulink 90% for the Logic Elements (LE), 95% for the RAM blocks
Model used for the fixed point validation of the algorithm). and 100% for the embedded multipliers. The maximum
Then these two signals are decimated by a factor 10 so that working frequency of the echo canceller is approximately 120
the sample-rate is reduced to 10 MHz. In particular in order MHz.
to minimize the FPGA resources the factor 10 decimation has
been obtained by firstly decimating by a factor 5 and then by This implementation of echo canceller is simple and
a factor 2. economical, since it does not need a training sequence for
channel estimation, it does not decrease performances of
In the base-band section we find a loop in which FIR throughput. Since FIR filter used for echo cancellation is
filters are used to reject adjacent channel interference and inserted in a feed-back loop, it does not increase total input-
complex variable coefficients FIR filters are used to cancels output delay of echo-canceller which is due only to
the echoes. The adaptation algorithm has been implemented decimation-interpolation FIR and adjacent channel rejection
in the DSP that periodically reads the content of the two FIR; actually total delay is about 6gs and is much smaller
FIFOs containing 4096 samples of the input signal I and Q than guard interval of OFDM modulation used in DVB-T, so
components. The FIFOs have been implemented by using the it does not affect quality of signal received by domestic
FPGA RAM blocks. demodulators in areas where they capture signals coming
from more than one repeater.

988

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 Figure 2. Simulink model of the FPGA architecture
CONCLUSIONS
IV.
In this paper a hardware implementation and a fast
prototype for the echo canceller is presented.
A fast prototype of the echo-canceller, has been
implemented by using a board based on a floating-point DSP
(Texas Instruments TMS320C6713) and an Altera Cyclone II
FPGA.
This implementation of echo canceller is simple and
economical, since it does not need a training sequence for
channel estimation, it does not decrease performances of
throughput.
Total delay of echo canceller is about 6pts and is much
smaller than guard interval of OFDM modulation used in
DVB-T, so it does not affect quality of signal received by
domestic demodulators.
REFERENCES
[1] A. Mattsson, "Single frequency networks in DTV" IEEE Trans. on
Broadcasting, vol. 51, issue 4, pp. 413-422, Dec. 2005.
[2] A. Wiewiorka and P.N. Noss, "Digital on channel repeater for DAB",
BBC R&D White Paper WHP120, BBC, September 2005
[3] K. Salehian, M. Guillet, B. Carson, and A. Kennedy, "On-channel
repeater for digital television broadcasting service," IEEE Trans. On
Broadcasting, vol. 48, no. 2, pp. 97-102, June 2002.
[4] Karim M Nasr, John Cosmas, Maurice Bard, Jeff Gledhill, "An Echo
Canceller for DVB-T/H On-Channel Repeaters", Vehicular Technology
Conference, 2007. VTC2007-Spring. IEEE 65th April 2007 Page(s):639
- 643.
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Authorized licensed use limited to: Instituto Nacional De Telecomunicações (INATEL). Downloaded on December 08,2021 at 13:34:56 UTC from IEEE Xplore. Restrictions apply.
[5] Karim M Nasr, John Cosmas, Maurice Bard, Jeff Gledhill,
"Performance of an Echo Canceller and Channel Estimator for On-
Channel Repeaters in DVB-T/H Networks" IEEE Trans. On
Broadcasting, Volume 53, Issue 3, Sept. 2007 Page(s):609- 618
[6] S. W. Kim, Y. T. Lee, S. I. Park, H. M. Eum, J. H. Seo, and H. M. Kim,
"Equalization Digital On-Channel Repeater in the Single Frequency
Networks", IEEE Trans. on Broadcasting, vol. 52, no. 2, pp. 137-146,
June 2006.
[7] Lee, Y.-T.; Park, S. I.; Eum, H. M.; Seo, J. H.; Kim, H. M.; Kim, S. W.;
Seo, J. S.; "A Design of Equalization Digital On-Channel Repeater for
Single Frequency Network ATSC System", IEEE Trans. on
Broadcasting, vol. 53, issuel, part 1, pp. 23-37, March 2007.
[8] Suk Chan Kim; Dong Chan Park; Sung Ik Park; Yong Tae Lee;
"Loopback Signal Cancellation Scheme in the Equalization Digital On-
Channel Repeater";
Consumer Electronics, 2007. ICCE 2007. Digest of Technical Papers.
International Conference on 10-14 Jan. 2007 Page(s): 1 - 2
[9] K. Murano, S. Unagami, F. Amano, "Echo cancellation and
applications", IEEE Communications Magazine - January 1990
[10] J.M.Cioffi and T.Kailath, "Fast, recursive-least-squares transversal
filters for adaptive filtering", IEEE Transactions on Acoustics, Speech,
and Signal Processing, vol.ASSP-32, no.2, pp.304-337, 1984
[11] B. Hatty, "Recursive least squares algorithms using multirate systems
for cancellation of acoustical echoes", International Conference on
Acoustics, Speech, and Signal Processing, vol.2, pp.1 145-1148, 1990.
[12] M. N. Kloos, W.K. Jenkins, "The investigation of new adaptive filtering
algorithms for telecommunications echo cancellation implemented in
TMS32010 Fixed point assembly code
[13] J.L. Dixon, W Y. Chen, "The implementation of an adaptive echo
canceller for high-speed digital data transmission"
[14] Digital video broadcasting (DVB); framing structure, channel coding
and modulation for digital terrestrial television, ETSI EN 300 744
V1.5.1 (2004-11), European Telecommunications Standards Institute.