JOURNAL OF ELECTRONIC TESTING: Theory and Applications 23, 293–307, 2007

* 2007 Springer Science + Business Media, LLC. Manufactured in The United States.
DOI: 10.1007/s10836-006-0711-0

The Effectiveness of Test in Controlling Quality Costs: A Conformability

Analysis Based Approach

J. M. GILBERT AND I. M. BELL

Department of Engineering, University of Hull, Hull, UK
j.m.gilbert@hull.ac.uk

Received February 10, 2006; Revised November 23, 2006

Editor: A. Ivanov

Abstract. Test and inspection are an increasingly costly element of electronic system design and manufacture and so it
is critical that the cost effectiveness of test and inspection are well understood. This paper presents techniques which may
be used to assess test capability and hence the implied test quality costs of PCB level electronic circuits. The techniques
presented are based on the electronic Conformability Analysis (eCA) approach which combines process capability indices
and Failure Modes and Effects Analysis with a cost mapping procedure. It introduces a new measure of test capability
based on the widely used process capability measure Cpk. This analysis allows the quality costs associated with design
and manufacture induced faults to be estimated and the effectiveness of test strategies in reducing these costs to be
determined. It allows the trade-off between quality costs and the component, manufacturing process and test costs to be
explored. The technique has been applied to analogue & mixed signal, safety critical circuits from automotive systems.

Keywords: quality, test escapes, test coverage, design for test, test capability, process capability, electronics design

1. Introduction—The Cost of Quality
Failures incorporated into an electronic product during its
manufacture may be classified as either parametric (or
soft) defects resulting from in-specification variation in
component values or as hard defects resulting from
failures in manufacturing processes [7]. Defects cause
quality costs to be incurred that may range from the costs
of repair through scrap and replacement costs and even
up to compensation costs in the event of a product
liability claim. Alongside the occurrence of defects we
must also consider the effectiveness of testing in terms of
test escapes and yield loss [5]. Part of our objective in this
paper is to provide feedback to the designer of the circuit,
system, or manufacturing/test process on the quality cost
impact of design and production decisions relating to test.
In [5] we consider design optimisation in more detail;
here we concentrate on test aspects.
Traditionally digital circuit test has employed a very
simple defect-orientated approach (e.g. using the classic
stuck-at fault model), whereas analogue circuits have been
tested against their specification. This situation has been
increasingly challenged over the past ten or more years due
to the need for more realistic and hierarchical digital fault
models, and the potential costs savings offered by defect-
orientated analogue test [14]. Defect orientated test is also
recognised as potentially providing reliability screening of
circuits which would pass standard tests [13]. It is also
amenable to metrics which distinguish between device and
connection test coverage [15]. Thus any general approach
attempting to analyse test quality needs to be able to deal
with both defect orientated and specification based test and
must be workable with different levels of abstraction for
design description.
Most of the literature (e.g. [18]) relating electronics
manufacturing processes to fault modelling and simulation
and to design centring focuses on IC design. The
techniques described are not fully applicable to PCB
manufacturing due to the different nature of the processes;
in particular the use of commodity parts and the manner in
which test and inspection is deployed. In particular, the
multi-stage, multi-modal nature of PCB manufacture has
different implications from IC test which is generally only
conducted at one or two points in the production process.
Furthermore such work is often focused on yield max-
imisation rather than quality cost minimization. The
application of six sigma [22] techniques to PCB level
electronics manufacture has been considered [17] but this
has focussed on the capability of manufacturing processes
and has largely ignored design and test aspects.
294 Gilbert and Bell
This paper describes a methodology, suitable for use with
analogue and mixed-signal electronics, which provides
feedback to the designer on the quality-cost implication of
decisions regarding design, testing and manufacturing
processes. Given that we are interested in this broad range
of activities, it is important that the output from applying our
methodology is consistent across the domains of design,
manufacture and test. The Conformability Analysis meth-
odology provides this consistency of approach. In terms of
test, the methodology aims to provide tools that can deal
with both design induced failures and failures due to
manufacturing defects in a consistent manner. Section 2 of
the paper provides a brief outline of the Conformability
Analysis methodology on which this work is based. We
show how this methodology may be adapted to electronic
system design, manufacture and test. The particular issues
associated with test capability are explored more fully in
Section 3. Section 4 demonstrates the application of the
technique to a simple example circuit while Section 5
discusses its application to a commercial safety critical
circuit. Evaluation and conclusions about the applicability
of the technique are presented in Sections 6 and 7.
2. Conformability Analysis
Conformability Analysis (CA) [1, 4, 20] had been shown
to be effective in determining quality costs associated
with mechanical products, arising from manufacture and
assembly induced faults. This paper describes a modified
form of CA applicable to electronic systems [5], with
particular focus on mixed signal test.
The key elements of the Conformability Analysis
methodology are an assessment of the capability of a
manufacturing process to produce products which meet
their specification and an assessment of the cost implica-
tions of any failures which do occur. The first of these is
embodied in the process capability index Cpk while the
latter is determined using a quality cost mapping process.
These two steps will be explained before showing how
they may be adapted to the electronics design, manufac-
ture and test arena.
2.1. Process Capability Index, Cpk
The Process Capability Index, Cpk, represents a pro-
cesses_ ability to produce products that meet their
specification. Assuming a characteristic is normally
distributed, with mean m and standard deviation s, and
that the acceptable range of performance is from the
lower specification limit, LSL, to the upper specification
limit, USL, then Cpk is defined as [6]:
 
jm  LSLj jUSL  m:j
Cpk ¼ min ; ð1Þ
3s 3s
The number of Defects Per Million Opportunities
(DPMO) is the probability that the performance measure
of interest lies outside of the specification limits [4].
Thus, if the probability that a performance measure has a
value x is p(x) then the DPMO value is:
8 LSL 9
<Z Z1 =
DPMO ¼ pð xÞdxþ pð xÞdx  106 ð2Þ
: ;
1 USL
The definition of the Process Capability Index is based
on the normal distribution. Where the process is not
normal, we may however determine the value of DPMO,
either by transformation or by curve fitting techniques
[3], and hence derive an equivalent Cpk value. Target Cpk
values are often specified for processes, a typical value
being CpkQ1.5, which corresponds to fault occurrence of
less than 3.4DPMO.
2.2. Quality Cost Mapping
The expected costs resulting from a particular product
defect depend on both the probability of its occurrence
and upon the severity of its effects. The relationship
between quality and cost has been addressed by a number
of authors. Taguchi [21] developed the concept of the
Quality Loss Function (QLF) in which the cost of
deviation from the target value of a parameter is
represented as a quadratic function of the difference
between actual and target values. This is scaled by the
acceptable range of performance and the cost of repair or
replacement. An alternative approach is to apply a scale
to different severities of failure and develop a relationship
between severity and cost. The definition of a failure
severity scale is not straightforward but one suitable
scale, defining Impact (Severity), has been developed by
Batchelor and Swift [1] based on the Failure Modes and
Effects Analysis (FMEA) severity scale [23]. The
characteristics of the points on the Impact (Severity)
scale are given in Table 1 [1].
Having defined a scale against which to assess the
severity of failure the second issue is to relate this scale to
likely cost. This relationship will depend on a number of
factors including the market sector for which the product is
designed, the internal organisation and field service
arrangements of the company involved as well as the
technologies adopted. Thus companies may wish to
develop their own scale. However, a simple general scale,
based on the Brule of ten^ [1], has been found to give a
good indication of likely costs for a range of industries.
The rule of ten states that costs of failure generally
increase tenfold at each process step in the supply chain
until the failure is detected. After shipping, costs increase
with the severity of the effect of failure. Table 1 provides

Table 1. Impact (severity) ratings.
Impact Cost (% product
(severity) Characteristics cost)
1 Component failure (before/at 1st 0.1
assembly)
2 Failure in subassembly 1
3 Failure at final assembly 10
4 Scrap unit or customer reject (OE 100
return)
5 Warranty return 1,000
6 Warranty return, Consequential 104
damage
7 Breach of statutory/regulatory 105
requirement
8 Potentially hazardous failure 106
9 Hazardous failure—some control 107
possible
10 Serious hazardous Failure—no 108
control
a list of likely costs for the various Impact (Severity)
ratings [1]. The rule of ten may be written as:
CO ¼ Cunit  O  10I4
where Co is the average failure cost, Cunit is the unit cost
of the product, O is the defect occurrence probability and
I is the Impact (Severity) rating.
The conformability analysis methodology consists of
assessing Cpk for each manufacturing process and hence
the defect occurrence and determining the probable
quality costs given the Impact (Severity) rating. This is
repeated for each aspect of a products specification and so
an overall cost of quality can be determined. This cost
may then be compared with a threshold value for
acceptable design, typically taken as 0.01% of the total
product cost [4]. In the following section we will show
how this methodology may be adapted to aspects of
electronics design, manufacture and test.
2.3. Conformability Analysis in Electronics Design,
Manufacture and Test
The CA methodology has been applied to mechanical
aspects of board level electronics manufacture such as
PCB manufacture and soldering [11]. However other
aspects of electronics design, manufacture and test could
benefit from this approach. The concept of capability and
cost mapping may be applied to variations in the
functional behaviour of a circuit, to variations in the
manufacturing processes used to produce the circuit and
to variations in the test and inspection processes used to
detect faulty circuits. Thus these different sources of
product failure may be assessed within a common
The Effectiveness of Test in Controlling Quality Costs 295
framework, as illustrated in Fig. 1. This common
framework allows the relative importance of hard and
soft defects to be assessed.
The capability of each aspect of a design/manufacture/
test combination may be expressed as a Cpk value. Thus
the capability of a design to function correctly in the
presence of in-specification component parameter varia-
tions may be termed Bfunctional capability,^ Cpk(func).
The capability of a manufacturing process route for a
particular circuit may be termed Bmanufacturing capa-
bility,^ Cpk(man), and the capability of test/inspection
processes to detect faults may be termed Btest capability,^
Cpk(test). Associated with each of these are defect or test
failure rates, usually specified in DPMO.
Figures for Functional Capability may be derived from
Monte-Carlo type simulations or from production sam-
ples and typically a Cpk(func) value will be determined for
each specified measure of circuit performance.
Manufacturing Capability values may be determined by
measuring production machine performance, for example
placement accuracy, and comparing these with the require-
ments for acceptable assembly. These manufacturing de-
fects may be based on a finite defect model and may be
subdivided as in [15]. Use of a fixed defect universe such as
this facilitates comparisons (e.g. of test processes), but is not
ð3Þ essential for optimising different individual board designs,
although of course consistency is required for comparing
alternatives for a given system. In the examples in this paper
we use only defects causing open and short faults, but our
methodology is not limited to this. In common with [15] we
do not use assumptions on how testing will be conducted
when determining which defects may be present.
Test capability is a little more complex and, since it is
the primary focus of this paper, will be discussed more
fully in Section 4.
The value of Cpk is a function of the variability in
component/process parameters. One of the advantages of
this representation is that it may be manipulated to show
an estimate of the contribution which each component/
process parameter makes to overall capability. Based on
this information, it is straightforward to direct design and
analysis effort at those components and processes which
have the greatest impact on poor capability [5].
Manufacturing Functional
Capability Capability
Will the proposed processes If the circuit is put together
allow us to put it together
correctly?
correctly will it meet the
specification?
Test
Capability
Cpk (man) Cpk (func)
Will our test strategy tell
us when things are going
Critical Critical Components/
Components
wrong?
Operating conditions
Cpk(test)
Impact (Severity)
What are the consequences
Cost of
of defects? Quality
Fig. 1. Three elements of electronics CA.
296 Gilbert and Bell
3. Test Capability
As described above, Conformability Analysis involves
capability assessment to determine the probabilities of
particular faults followed by an estimation of the resulting
quality costs. The same two stages may be applied to test
and inspection processes as discussed below.
Variability in the test/inspection process can result in
both yield loss and defect escapes. Comprehensive assess-
ment of defect escapes requires understanding of the
behaviour of the circuit under all possible fault conditions,
in the presence of within-specification component param-
eter variations. This can be computationally very expensive
and so is not attractive. It is thus desirable to only analyse
those faults which are likely to occur or, preferably, those
which are associated with the greatest quality costs.
As illustrated in Fig. 1 functional and manufacturing
capability assessments identify the most likely and most
costly defects. This information may be used to ensure that
the efforts expended in test generation and testability analysis
are focusing on those aspects of manufacture and functional
behaviour, which have the greatest cost implications [5].
Inductive Fault Analysis (IFA) [16] has also been
proposed as a method of producing an ordered fault list,
and so reducing fault simulation effort for ICs. IFA has
been extended to analogue ICs [8] by using a methodol-
ogy that employs statistical process simulation. IFA
techniques may also be adapted to board layouts [12] to
determine probabilities of short-circuit and open-circuit
tracks if the properties of such defects are known. One
difficulty with this is that it requires a multi-stage
approach, as processes such as soldering may be multi-
staged with a typical board going through several
soldering operations. A straightforward application of
IFA analysis to board tracks may also not produce the
most effective ordered list of faults to be investigated. For
example, this approach may not indicate variation in fault
probability due to the positioning of a large component at
different distances from the edge of a board.
The functional and manufacturing capability and cost
assessment described in Section 3 may readily be
presented as an ordered fault list since this simply
involves a ranking of design and manufacture induced
faults on the basis of capability or cost [10].
Having obtained an ordered fault list, assessment of the
capability of the electrical test processes may be carried
out using fault simulation. In our work we use a modified
form of the ANTICS fault simulator [2, 19] to estimate
the probable occurrence of defect escapes. The ANTICS
software works by controlling SPICE simulations of the
test process. In our methodology we perform an initial
analysis based on a small number of simulations of each
defect to determine which ones are easily identified and
which are more subtle. More extensive simulation is then
performed on these latter faults to obtain information
about the distribution of circuit behaviour and the effect
of test variability. Other test processes such as visual
inspection will also contribute to the overall test capabil-
ity and will require an evaluation of their effectiveness
for each fault of interest. Evaluations of multiple test
stages have to be combined to determine overall test
capability and this is discussed in Section 4.3.
3.1. Test Capability Measurement
In defining a measure of test capability we wish to develop a
quantity which indicates the extent to which a particular test
can distinguish between the behaviour of defect-free
circuits and those which contain hard defects. Any test or
inspection process involves measurements of circuit char-
acteristics which are corrupted by noise. Thus these
processes introduce variability which must be combined
with the inherent variability in those circuit characteristics
in order to determine the distribution of measured perfor-
mance. Consider Fig. 2 which shows the distribution of
measured behaviour under defect-free conditions and
under three different defect conditions. It is clear that this
test, with the upper and lower test limits (UTL and LTL)
indicated, is highly capable of detecting defect conditions
1 and 2 but poor at detecting defect condition 3.
Based on the definition of Cpk for manufacturing
processes we may define Cpk(test) in terms of the distance
between the mean and the test limits scaled by the
variability in the measured behaviour under defect con-
ditions. Considering the upper test limit, we may define:
mi  UTL
CpkðtestÞi ¼ ð4Þ
3s i
where mi is the mean of measured behaviour under defect
condition i and s i is the standard deviation of measured
behaviour under defect condition i. Thus a large positive
value of Cpk(test)i implies that the test is effective in
detecting defect i. Note that if the mean behaviour lies
below the upper test limit, as in defect condition 3 in Fig. 2,
the value of Cpk(test) will be negative, indicating that the
test is not capable of detecting the defect. This measure
may also be applied to the defect-free case where it gives
an assessment of yield loss. In this case the Cpk(test) value
will be negative (assuming the test limits span the mean
performance) and a more negative Cpk(test) value corre-
sponds to lower yield loss.
In the more general case where we have an upper and
lower test limit (UTL and LTL) this may be extended to:
 
m  UTL LTL  mi
CpkðtestÞi ¼ max i ; ð5Þ
3s i 3s i
The use of the maximum of the two values ensures that
the capability in respect to the closest test limit is
considered. It may be noted that if the mean of behaviour
 The Effectiveness of Test in Controlling Quality Costs 297

Defect 1
Probability

Defect Free Defect 3

Defect 2

Measured
μ2 LTL μ0 UTL μ1 performance
Fig. 2. Effect of defects on measured performance.

under defect conditions lies between the test limits, as failing a particular test under defect or defect-free
illustrated in defect 3 in Fig. 2, both terms in Eq. 5 are conditions. In doing so we must consider defect escape
negative. and yield loss probabilities using both circuit behaviour
Clearly not all tests are equally effective at detecting all and test measurement variability. In order to estimate
defects and so it is common that several tests may be used these values, the method outlined below has been used.
to ensure coverage. Thus we may consider the capability Assume that the probability distribution of performance
of test j to detect defect condition i, defined as: of the circuit in the absence of hard faults but in the
  presence of component parameter variations is Ps(x).
mij  UTLj LTLj  mij Given performance specification limits of LSL and USL
CpkðtestÞij ¼ max ; ð6Þ
3s ij 3s ij then the circuit behaviour is acceptable for LSL <
x < USL. The distribution of this acceptable behaviour
where mij is the mean of behaviour under defect condition is a truncated version of Ps(x), namely:
i as measured in test j, s ij is the standard deviation of 8
behaviour under defect condition i as measured in test j < 0 x  LSL
and UTLj and LTLj are the upper and lower test limits Psg ð xÞ ¼ Ps ð xÞ LSL < x < USL ð7Þ
:
adopted in test j. Provided one of the test processes 0 x  USL
applied is capable of detecting each of the i defect
Likewise, the distribution of unacceptable behaviours is
conditions then there should be minimal defect  escapes.

the remainder of Ps(x), namely:
This may be interpreted as ensuring that max CpkðtestÞij
is above a specified minimum e.g. 1.5.
j¼1::m 8
< Ps ð xÞ x  LSL
Psf ð xÞ ¼ 0 LSL < x < USL ð8Þ
3.2. Test Error Occurrence :
Ps ð xÞ x  USL

On the basis discussed in Section 2.1, the Cpk(test) value Now, the variation in the performance of the test/
may be related to the probability of a circuit passing or inspection process may be represented by a distribution
298 Gilbert and Bell

T(x). The shape of this distribution will depend on the probability of defect escapes is the integral of the
nature of the test/inspection method used. The distribu- probability of faulty circuits whose measured behaviour
tion of measured performance is found from the convo- falls within the test limits, LTL to UTL:
lution of actual performance distribution and the test
performance distribution. Thus the measured performance ZUTL
of good circuits is: PDE ¼ Msf ð xÞdx ð11Þ
LTL
Msg ð xÞ ¼ Psg ð xÞ*T ð xÞ ð9Þ
Similarly the overall probability of yield loss errors is
where *R1 represents the convolution operation f ð xÞ* given by:
gð xÞ ¼ 1 f ð xÞgðx  yÞdy. Likewise, the measured per-
formance of faulty circuits is: ZLTL Z1
PYL ¼ Msg ð xÞdxþ Msg ð xÞdx ð12Þ
Msf ð xÞ ¼ Psf ð xÞ*T ð xÞ ð10Þ
1 UTL

This latter case is illustrated in Fig. 3. Clearly the effect of
measurement noise is to produce apparent behaviour which
is spread from the actual behaviour. A similar smearing
effect occurs on the measured performance of fault-free
circuits. It should be noted that although both the circuit
behaviour and the test noise are represented by normal
distributions in this illustration, this is not a requirement and
any distributions may be treated in the same manner.
The occurrence of test errors depends on the test limit
selected. The defect escapes and yield loss probabilities
may be found from the integral of the smeared functions
above and below the test limits. Thus the overall
The benefit of using the probability distributions to
represent the variation in performance and measurement
is that the computation of this smearing effect is
straightforward (since it is simply the convolution of
two functions) and the calculation of integrals given in
Eqs. 11 and 12 may be performed by numerical methods.
3.3. Test Error Cost
Using the methods described in Section 3.2 we may
estimate the probability of a particular board passing or

Faulty Circuit
Fault Free Performance
Circuits
Measured
Performance of
Faulty Circuits

Upper Defective
Specification Circuits
Limit
Fig. 3. Combined effect of performance variation and measurement variability of measured performance of out of specification behaviour.
 The Effectiveness of Test in Controlling Quality Costs 299

failing a particular test, both in the case where the board of fault 1 and when failing test 2. The probability of a
contains a specific defect and when it is defect-free. In fault-free circuits which pass all tests and which meets all
most manufacturing environments the situation is more aspects of the specification is denoted P000.
complex since there are many possible defects and many It can be difficult to determine the conditional
different test/inspection operations. In addition, since probabilities for multiple defects so we will assume that
board production is a multi-stage/multi-test process of a board can only contain a single defect. This is a
the type illustrated in Fig. 4, the probability of each fault conservative assumption since, for a given number of
type varies through the manufacturing process. In parallel defects, it results in the maximum number of defective
with this, the value of the board increases as it progresses boards. In this case, the probability of an item being
through the various stages of manufacture. In order to scrapped (either because it fails at test due to hard faults
represent the probability of fault occurrence, the proba- and or because it fails at test despite containing no hard
bility of passing at test and the probability that the circuit faults) is:
meets its specification, we will introduce the following
notation: l X
X m X
m
Ps ¼ Pij þ P0j ð13Þ
i¼1 j¼1 j¼1
P0
probability that circuit contains no hard defects, The first term in this equation represents all those
circuits which contain hard defects and fail at test while
Pi i ¼ 1:::l the second term represents those that contain no hard
probability that circuit contains hard defect i defects but which fail at test; in other words yield loss.
For the purposes of this paper we will also assume that all
Pi0 circuits which fail at test are scrapped although, in
conditional probability that circuit passes all tests in the practice, further test and rework may be carried out.
presence of defect i, The costs associated with this may be represented through
the use of an appropriate Impact (Severity) rating. The
Pij j ¼ 1:::m point in the manufacturing process at which a unit is
conditional probability that circuit fails at the jth test scrapped determines its value, as reflected in the Impact
stage in the presence of defect i (Severity) rating. If this is denoted Isj for an item
scrapped at the jth test stage then the total value of
Pij0 scrapped items is:
conditional probability that circuit meets all aspects of
!
the specification, in the presence of defect i and test X l Xm
Isj 4
X
m
Isj 4
outcome j Cs ¼ Cunit Pij 10 þ P0j 10 ð14Þ
i¼1 j¼1 j¼1

Pijk k ¼ 1:::n Or
conditional probability that circuit fails to meet the kth
X
l X
m
aspect of the specification in the presence of defect i and Cs ¼ Cunit Pij 10Isj 4 ð15Þ
test outcome j i¼0 j¼1
Thus, P123 is the probability that a board contains hard
defect number 1, fails test number 2 in the presence of Circuits which pass all tests are shipped and of these
this fault and fails to meet specification 3 in the presence some may contain hard defects while others may exhibit

Field Failure
Process Test Process Test k Test n Im pact I fk
1
G ood Product

Defective

Scrap Scrap Scrap

Defect
Impact I s1 Impact I sk Im pact I sn free
Fig. 4. Test cost model.
300 Gilbert and Bell

soft defects. In both cases these may result in field failure. 12V Node 1
The probability of field failure is thus given by:
X
l X
n 10k R1
Pf ¼ Pi0 þ P00k ð16Þ
i¼1 k¼1
Node 2
where the first term represents circuits with hard faults
which nevertheless pass all tests and the second term 100Ω R2 V3
represents circuits with no hard faults which pass all tests
but fail to meet the kth aspect of the specification. Node 3 V1
The costs resulting from a field failure depends on which
aspect of the specification is violated. Failure to meet aspect
k of the specification has an associated Impact (Severity)
220k 22k V2
rating Ifk and hence average cost for units containing soft R4 R3
defects is Cunit P00k 10Ifk 4 . It is possible that a single defect
may cause a circuit to fail to meet several aspects of its 0V Node 4
specification and these may have different consequences. Fig. 5. Example circuit design.
In general we are most concerned about those faults which
have the highest cost consequences. Thus the cost of field
failures is approximated by: interpreted as 3s=5% of the nominal value with the
distribution truncated at T 5% [18]. Using nominal
( ) component values the output voltages are V1=8.01 V,
X
l    
Ifk 4 Ifk 4 V2=7.97 V and V3=39.9 mV. A PCB layout of an
Cf ¼ Cunit max Pi0 10 þ max P00k 10
k¼1::n k¼1::n implementation of the proposed design is given in Fig. 6.
i¼1

ð17Þ
It should be noted that these equations can only be
regarded as an estimate of expected quality costs since they
neglect costs from some, less expensive, failure modes.
However, this figure is useful in itself and the terms in the
summation also indicate which aspects of the specification
and which faults are associated with the greatest quality
costs. Once this is established, additional analysis may be
applied to determine a more accurate figure for the major
cost elements and to address the causes of these costs.
4. Example Circuit
4.1. Functional Capability
Based on a sample of 1,000 randomly selected sets of
resistor values taken from truncated normal distributions,
the defect-free distributions of each voltage may be
found. From this data the functional capability of the
design, the expected failure rates and the implied average
quality costs may be calculated using Eqs. 1, 2 and 3.
This information is given in Table 3.
It can be seen that although the circuit has a fairly high
level of capability with regard to the lower limit for V1
there is a relatively high cost due to the high Impact

In this section we describe a very simple example circuit Node 1 R1

to illustrate each stage of our approach. The circuit is a
potential divider required to meet the output voltage Node 2
specification given in Table 2. The Impact (Severity) R2
rating if the circuit fails to meet this specification is also
given in Table 2, these values being set for illustrative
purposes only. Figure 5 shows a proposed design where
all resistors have 5% tolerance. This tolerance is Node 3 Node 4
Table 2. Example circuit specification.
R3
Parameter LSL USL Impact (severity)

V1 7.75 – 7
V1 – 8.25 6 R4
V2 7.75 8.25 5
V3 0.035 0.045 6
Fig. 6. Example circuit layout.
 The Effectiveness of Test in Controlling Quality Costs 301

Table 3. Functional capability of proposed design.

Parameter LSL USL Impact (severity) Cpk(fun) Fault Occurrence (ppm) Average cost (% of unit cost)

V1 7.75 – 7 1.49 4.1 0.41

V1 – 8.25 6 1.34 30.2 0.302
V2 7.75 8.25 5 1.26 80.3 0.08
V3 0.035 0.045 6 2.05 0.0004 410j6
Total 0.792

(Severity) factor. It may further be noted that the lower
limit for V1 and the limits for V2 are associated with lower
levels of capability and hence higher levels of fault
occurrence. The resulting costs are lower however due to
the lower Impact (Severity) rating. The performance with
respect to the specification for V3 is highly capable and
hence has negligible quality cost consequences.
4.2. Manufacturing Capability
In the analysis of manufacturing capability, we will only
consider two types of defects: open circuit and short circuit
defects. It is assumed in this analysis that the probability of
such defects depends solely on the processes used and not
on the component value or its location on the board. The
occurrence rate for open circuit defects is set to 10DPMO
(Cpk(man)=1.42). Unintentional short circuits may be
introduced between nodes if solder is placed or re-flowed
incorrectly. The probability of such faults decreases as the
distance between nodes increases. The illustrative prob-
abilities of short circuits are given in Table 4, as are the
corresponding Cpk(man) values in brackets.
A Monte Carlo analysis of the circuit behaviour, in the
presence of component parameter variations, has been
performed for each short and open circuit defect
condition. In most cases there will be a significant change
in circuit response. These may be identified on the basis
of a fairly small sample of simulations and so an initial
screening process involving 100 Monte Carlo simulations
was performed under each defect condition. There are,
however, circumstances in which defects occur but the
circuit still meets at least some aspects of the specifica-
tion. In particular, if R4 is not included in the circuit then
it is still possible for the circuit to meet all aspects of the
Table 4. Probabilities of short circuit faults between nodes (corresponding
values of Cpk(man)).
Nodes N1 N2 N3 N4
N1 – 10 ppm (1.42) 100 ppm (1.24) 1 ppm (1.58)
N2 – 10 ppm (1.42) 100 ppm (1.24)
N3 – 1 ppm (1.58)
N4 –
specification if the remaining component parameters fall
within certain regions of their specified ranges. A short
circuit between nodes 2 and 3 will clearly result in the
circuit failing to meet the specification for V3. It will not
necessarily however cause it to fail to meet the specifi-
cations for V1 and V2.
The probabilities of the circuit complying with each
aspect of the specification in the presence of these hard
defects are listed in Table 5. Since we are not, at this
stage, considering test processes then we can treat the
circuits as though they have all passed all tests and simply
consider the FOccurrence Probability_ (the probability of
the ith hard fault occurring, Pi) and the FEffect Proba-
bility_ (the probability of failing to meet the kth aspect of
the specification in the presence of the ith hard fault,
Pi0k =Pi ). The actual defect rate, Pi0k is the rate of
occurrence of the manufacturing defect i multiplied by
the probability of the circuit failing to meet specification
k in the presence of the defect i. Thus the probability of
an open circuit in place of R4 is 10 ppm and when such a
defect occurs, the probability that this will force V1 above
its upper specification limit is 0.576 and so the probability
of this failure due to this cause is 5.76 DPMO. Given that
the corresponding Impact (Severity) factor is 6, the
resulting average quality cost is 0.0576% of the product
cost. In the case of defect 8 (a short circuit between nodes
N2 and N3), the probability of the defect occurring is ten
DPMO but this pulls voltages V1 and V2 closer to the
centre of their specified range and so it is very unlikely
that the performance
 will be outside
 of these specification
limits Pi0k Pi ¼ 12:4  106 . However, given this
defect, it is certain that the circuit will fail to meet its
specification for V3 and so in this case Pi0k =Pi ¼ 1. In this
case the Impact (Severity) rating is six and so the average
quality cost is 1% of the product cost.
In the case of soft defects, assuming that any board can
only contain one hard defect, the number of boards which
contain no hard defects is simply the total boards less the
sum of hard defect occurrence probabilities (in this case
106  262 ¼ 999738ppm). The corresponding Effect
Probabilities are the same as those given in Table 3, with
corresponding average quality costs.
Based on the figures given in Table 5 the overall
average quality cost may be estimated as 24.8% of the
unit cost. We may also see that the major contributors to
302 Gilbert and Bell

this cost are short circuits between nodes 1 and 3 and
between nodes 2 and 4. Note that where a defect affects
several measures of performance we have included in the
total cost only that aspect of performance which has the
highest cost consequences. This is based on the premise
that a board will be removed from service as soon as any
fault occurs and so it would not be reasonable to add the
costs of all possible failures. We do not however know in
what sequence failures may occur and so it is conserva-
tive to assume that the most expensive failure will occur
first. Thus, in the total column of Table 5 we include the
maximum cost for each possible defect.
4.3. Test Capability
Using the method outlined in Section 3 and the
performance distributions determined above we may
estimate the test capability and hence quality cost for
the example circuit. Using the same 100 run Monte Carlo
simulations as used to assess manufacturing capability,
we can assess test capability. Measurement noise with a
standard deviation of 10 mV was assumed with respect to
V1 and V2 and 50 mV with respect to V3. These values
assume that the measurement instrument is capable of
measuring to 3 digits but in practice this would require
knowledge of the instrumentation used. In this evaluation
the test limits were set to the specification limits although
other values could readily be used. The test capability
figures calculated are given in Table 6.
The first row of Table 6 is for the case with no hard
defects. The negative capability indicates that the mean
performance lies between the test limits, as would be
expected for the defect-free circuit. The absolute values
of Cpk(test) mirror those for the functional capability given
in Table 3 but indicate a slightly lower capability due to
the measurement noise introduced. These capability
figures may be related to the number of boards containing
no hard defects which will fail at test. The majority of the
remaining rows of Table 6 indicate that the tests are
highly capable of detecting these defects (High values of
Cpk(test)). Consider, for example, defect 1 (R1 open
circuit) and test 1 (for the lower limit on V1). Under this
defect condition V1 will become zero but the measured
voltage will have zero mean and standard deviation of
10 mV due to measurement noise. The test capability
is thus CpkðtestÞ11 ¼ LTL3s1 m
11
11
¼ 7:750
30:01 ¼ 258. Clearly this
test is effective at detecting this defect but is not capable
of detecting defect 2 (open circuit on R2) since this causes
V1 to move further above the lower test limit. This defect
is, however, readily detected by test 2 (V1 above 8.25 V).
The only defect for which all tests show poor capability is
defect 4 (R4 open circuit). This may be predicted since R4

Table 5. Manufacturing capability of proposed layout.

Fault Component/ Occurrence Effect Impact Possible costs

Fault number, nodes probability, probability, (severity) for defect Highest
 cost fordefect
type i affected Pi (ppm) Pi0k =Pi Ifk Pi0k 10Ifk 4 max Pi0k 10Ifk 4
k¼1::n

Soft 0 999738 V1l: 4.1 ppm 7 0.41 0.41

V1u: 30.2 ppm 6 0.3
V2: 80.3 ppm 5 0.08
V3: 0.0004 ppm 6 410j6
Open 1 R1 10 1 7 1 1
2 R2 10 1 7 1 1
3 R3 10 1 7 1 1
4 R4 10 V1l: 0 7 0
V1u: 0.576 6 0.0576 0.0576
V2: 0.333 5 0.00333
V3: 0.0009 6 0.000091
Short 5 N1+N2 10 1 7 1 1
6 N1+N3 100 1 7 10 10
7 N1+N4 1 1 7 0.1 0.1
8 N2+N3 10 V1l: 12.410j6 7 12.410j12
V1u: 12.410j6 6 1.2410j12
V2: 12.410j6 5 0.12410j12
V3 : 1 6 0.1 0.1
9 N2+N4 100 1 7 10 10
10 N3+N4 1 1 7 0.1 0.1
Total (% unit cost) 24.8%
 The Effectiveness of Test in Controlling Quality Costs 303

Table 6. Test capability figure for proposed design.

Test, j
Defect 7.75V < V2 < 0.035V < V3 < Maximum
Number, i Defect Name V1 > 7.75V V1 < 8.25V 8.25V 0.045V capability
0 None -1.46 -1.32 -1.24 -2.04 -1.24
1 Open R1 258 -275 259 233 258
2 Open R2 -142 125 258 79700 79700
3 Open R3 -81 70.2 69.9 77.1 77.1
4 Open R4 -2.82 0.063 -0.143 -1.03 0.063
5 Short N1 + N2 -142 125 122 3.70 125
6 Short N1 + N3 -142 125 125 232 233
7 Short N1 + N4 -8.33 -8.33 125 26400 26400
8 Short N2 + N3 -1.38 -1.39 -1.38 233 233
9 Short N2 + N4 258 -275 258 233 258
10 Short N3 + N4 245 -262 258 8.99 258

Shaded cells indicate those tests which are not capable of detecting the corresponding defect.

(220 k) is in parallel with R3 (22 k) and so any change in
R4 is largely masked by R3. Thus the absence of R4 has
little impact on the voltages tested and so all tests display
poor capability. Three of the tests have negative capability,
indicating that the mean performance with the defect still
lies between the test limits while the most effective of the
tests (Test 2) has a Cpk(test) value of only 0.063, which
indicates that only 0.576 of circuits suffering from this
defect will fail this test.
We may also use the data in Table 6 to asses test
coverage. It may be seen that test 4 is capable of
detecting all defects except Defect 4 while test 1 is only
effective in detecting defects 1, 9 and 10, which are
adequately covered by other test. We may, therefore wish
to consider eliminating tests 1, 2 and 3 and determining
other methods to identify Defect 4. Before undertaking
such steps, it is worthwhile considering the cost con-
sequences of the various defects and proposed test
strategy. As has been seen from Table 6, the tests display
good capability for all but two defect types, defect 4 and
soft defects represented in the first row of Table 6. Given
the Cpk(test) figures in this first row, we can see that a
significant proportion of defect-free units will fail this test
(approx 100DPMO in the case of Test 3 since
Cpk(test)=1.24). Those defect-free units which fail a test will
be scrapped but the fact that their performance lies close to
the test and specification limit implies that some other
boards may pass the test (due to the measurement noise) but
fail to meet the specification. These units which possess soft
defects will be shipped and are liable to field failure while
other defect-free units are scrapped. The cost consequences
of these two outcomes will be investigated further. This,
more detailed, investigation is based on a more extensive
fault simulation of these two defect conditions.
Consider first the 999738 ppm circuits which contain
no hard defects. Out of this total, 145 boards will fail one
or more of the tests and be scrapped. Given the Impact
(Severity)
 rating of of Isj ¼ 4, the resulting
 average cost
is 145  106  1044  100 ¼ 0:0145% . Of those that
pass the test, the vast majority will meet their specifica-
tion. However, a small proportion will fail to meet some
aspects of the specification. 0.92 ppm will fail to meet
the specification for V1L, 5.9 ppm will fail V1U, 16 ppm
will fail V2. Given the corresponding Impact (Severity)
ratings of 7, 6 and 5, the resulting average costs
are 0:92  1074 þ 5:9  1064 þ 16  1054 106 
100 ¼ 0:167%. There are a negligible number of circuits
which fail to meet the specification for V3.
Considering defect 4, an open circuit on R4, which
occurs with a probability of 10 ppm, we may calculate
that in 0.5768 of cases these circuits will fail one or more
tests and be scrapped (average cost 10  106  0:5768
1044  100 ¼ 0:00058%). The remaining proportion
(0.4232 of units with defect 4 or 4.23DPMO of all units)
will pass all tests and be shipped. We may consider these
defective boards in a number of ways. We may consider
that although they contain defect 4 the majority will meet
all aspects of their specification. We may further calculate
that only approximately 2.5% of these
 defective boards
4:23  106  0:025 ¼ 0:106DPMO will fail to meet
the specifications for V1U and V2. The average cost
resulting from these failures is therefore 0:106  106 
1064  100 ¼ 0:00106% and 0:106  106  1054 
100 ¼ 0:000106%, respectively. More conservatively,
we may take the view that having shipped a defective
board we should expect it to fail at some point and
calculate the cost on this basis, even if it does meet the
specification when shipped. In this case we have 4.23 ppm
defective boards which are liable to fail the specification
for V1U and V2, and so average quality costs of 4:23 
106  1064  100 ¼ 0:0423% a n d 4:23  106 
1054  100 ¼ 0:00423%, respectively.
4.4. Combined Capability
We can see from the above analysis that the circuit
exhibits poor capability. The functional capability is low,
with a minimum Cpk(func) value of 1.26 and an average
quality cost of 0.79% of the product cost even if the
circuit could be built without the introduction of any hard
304 Gilbert and Bell

defects. Manufacturing capability is poor resulting in a
large number of faulty circuits, giving an average quality
cost of 24.3% of the product cost. If we use test (with test
limits set to the same values as specification limits) to
identify faulty boards then, due to the presence of
measurement noise, we are not able to identify all faults
and face a quality cost of 0.23% of the product cost. It is
often considered that the maximum acceptable quality
cost is 0.01% of the product cost [4] and hence the costs
found here are unlikely to be acceptable. Improving the
capability of manufacturing or test processes is likely to
require new capital equipment and hence be expensive
and so it would seem sensible, in the first instance, to
investigate design modifications.
The components which contribute most to poor
functional capability are R1 and R3 (see [5] for an
analysis of a similar circuit). Furthermore the test
processes cannot reliably detect whether R4 is present.
Combining these two findings suggests that replacing R3
and R4 by a single 20 k, 1% resistor may overcome these
problems. It is possible that the cost of a single 1%
resistor may be less than that for two 5% resistors but,
even if this is not the case, the additional cost may be
worthwhile if the result is a saving in quality costs. The
change to a 1% resistor has the effect of reducing
variability, particularly in V3, and thus significantly
improves the functional capability of the circuit, as
detailed in Table 7. In assessing the capability of this
modified circuit we will assume that the individual
manufacturing capability figures given in Table 4 (with
R4 eliminated) remain valid.
Clearly, if the redesigned circuit could be manufactured
without the introduction of faults, its performance would
be acceptable. Unfortunately, the manufacturing capabil-
ity is not significantly affected by the redesign and the
average quality costs, in the absence of test, remain at
24.3% of the product cost. Fortunately, the reduced
variability in fault-free circuits and the elimination of
R4 whose presence had only a small effect on circuit
behaviour means that the test operations are better able to
distinguish between defect-free and defective circuits.
The test capability figures for the modified circuit are
shown in Table 7. It can be seen that the tests are capable
of detecting all of the defects and, indeed Test 4 alone is
capable of detecting all of the defects. Thus we are able
to eliminate the remaining tests. It may also be noted that
the capability with respect to soft faults is improved
(more negative). Thus the tests will be expected to fail
fewer circuits which contain no hard defects and so the
yield loss is similarly reduced. With the modified circuit
the average quality cost reduces to 0.00056%.
The analysis carried out on this circuit clearly quanti-
fies the effectiveness of test in controlling quality costs.
This does not directly take account of the cost of
conducting the test but this is a relatively simple
calculation compared to those presented here.
5. Industrial Case Study
In order to assess the effectiveness of the techniques
described a number of case studies of commercial circuit
designs and manufacture/test routes have been investi-
gated [9]. The case study outlined below produced results
which are typical of those found. The circuit considered is
shown in Fig. 7. The purpose of this circuit is to take a
sine wave signal from the sensor connected to VSensor and
convert this to a square wave output of the same
frequency at Vout. Since the sensor signal is corrupted
by noise, the circuit contains low pass filter elements and
hysteresis provided by the positive feedback connection
around the comparator. The proposed test regime con-
sisted of applying a 5 V, 100 Hz square wave signal with
additive Gaussian noise to the input and monitoring the
output frequency. The test specification stated that the
output frequency should be within the range 90–110 Hz.
Using this test input the defect-free circuit was found to
produce a 100 Hz output under all in-specification
component variation conditions. Thus the standard devi-
ation of the output frequency is zero and the test
capability infinite. In assessing the capability of this test
in the presence of defects, short and open circuit defects

Table 7. Test capability figure for modified circuit.

Test, j
Defect 7.75V < V2 < 0.035V < V3 < Maximum
Number, i Defect Name V1 > 7.75V V1 < 8.25V 8.25V 0.045V capability
0 None -1.92 -1.72 -1.64 -2.33 -1.64
1 Open R1 258 -275 259 233 259
2 Open R2 -141 125 258 79700 79700
3 Open R3 -142 125 125 233 233
5 Short N1 + N2 -142 125 123 4.91 125
6 Short N1 + N3 -142 125 125 233 233
7 Short N1 + N4 -8.33 -8.33 125 26400 26400
8 Short N2 + N3 -1.82 -1.82 -1.82 233 233
9 Short N2 + N4 258 -275 258 233 258
10 Short N3 + N4 245 -261 258 9.00 258

Shaded cells indicate those tests which are not capable of detecting the corresponding defect.
 The Effectiveness of Test in Controlling Quality Costs 305

R3 20k R4 47k R5 3M3

C3
5V 10μ 5V

GND
R1 R6
18k 7M5
+ Vout
VSensor
_
R2 68k
C1 C2
10n 2n2

GND GND
Fig. 7. Signal conditioning circuit.

on each of the passive component were considered. Many
of these defects result in an output frequency which lies
far outside the specified range (most often zero Hz). In
order to identify these a test screening was performed
involving a small number of Monte Carlo simulations
under each defect condition. More extensive Monte Carlo
simulations were performed for those defects identified in
the screening simulations as having poor test capability.
From the results of these simulations the test capability
figures for each defect condition given in Table 8 were
calculated.
In a number of cases (for example a short circuit defect
on R1) the defect causes the circuit output to become
stuck either high or low, in which case the output
frequency is zero and the standard deviation of the
frequency is also zero, resulting in a Cpk(test) value of
infinity. Clearly, such defects are readily detected by the
proposed test. In other cases the result of the defect is a
small change in output frequency. For example an open
circuit defect in place of R1 causes the DC offset on the
input voltage to be altered and changes the limits of the
hysteresis provided by the comparator. This allows a
small number of large noise spikes to be counted causing
the output frequency to increase. The output frequency
lies somewhere in the region 100–104 Hz dependant on
the component values and the noise voltage profile.
Clearly these circuits would all pass the proposed test
and the test is not capable, as indicated by Cpk(test)<1.5.
Other defects cause a much greater change in output
frequency which is readily detected. For instance, a short
circuit on R2 reduces the filtering ability of the circuit,
causing noise signals to be counted as sensor pulses and
resulting in an output frequency in the range 1,900–2,130 Hz.
This gives a value of Cpk(test)=1.6, indicating that the
proposed test is capable of detecting that defect.
What is clear from this analysis is that the proposed test
is not sufficiently capable of detecting several of the
defects. One solution to this problem would be to intro-

Table 8. Test capability for proposed test regime.

Open Circuit Defects Short Circuit Defects
Component Cpk(test) Defect Component Cpk(test) Defect
Escapes Escapes
(DPMO) (DPMO)
R1 -5.6 106 R1 ∞ 0
R2 ∞ 0 R2 1.6 0.8
R3 -4.2 106 R3 ∞ 0
R4 -6.1 106 R4 ∞ 0
R5 ∞ 0 R5 -2.78 106
R6 -2.5 106 R6 ∞ 0
C1 -0.49 9.3x105 C1 ∞ 0
C2 2.04 10-4 C2 ∞ 0
C3 14.9 0 C3 -3.8 106

Shaded cells indicate those tests which are not capable of detecting the corresponding defect.
306 Gilbert and Bell
duce additional tests, such as in-circuit-testing, of these
components which are not covered by the functional test.
Clearly this has additional cost implications. The alter-
native of modifying the test signal was investigated. By
adjusting the signal and noise elements of the input it is
possible to make the test more sensitive to defects. This
can however have the detrimental effect of reducing the
test capability of defect-free circuits. For example, re-
placing the square wave input with a sinusoidal signal
with 1 V amplitude makes several of the previously un-
detectable defects detectable with C pk(test) values
in the range 1.4 to 2.0. This change in test input does
affect the test capability of the defect-free circuit, giving
Cpk(test)=2.7, implying a negligible yield loss. Other test
signals result in better defect coverage but also result in
greater yield loss. On the basis of the defect occurrence
rates and the implied quality costs the optimum balance
between the costs associated with yield loss and defect
escapes may be determined. For reasons of commercial
confidentiality, the defect occurrence and Impact (Severity)
rating information associated with circuit are not presented
here.
6. Evaluation
Providing feedback to a designer using test metrics has
always proved difficult to implement because results in
the form of large numbers of testability scores or
coverage figures are difficult for designers to interpret.
In digital test this is at least partly circumvented as
testability algorithms may now be embedded in powerful
test pattern generators and other tools. At present this is
not the case with analogue and mixed signal systems. Our
methodology provides results in terms of capability and
ultimately in terms of the financial implications of design,
test and manufacturing decisions. We do not aim to
provide a full economic analysis, but can present results
scaled in terms of cost impact, which facilitates compar-
isons between alternative implementations, and is com-
prehensible by both designers and managers. We have
typically applied our approach to our industrial partners_
processes in a design reviews context rather than as direct
feedback to designers. The reason for adopting this
approach is that the information derived allows the
tradeoffs between aspects of design, manufacture and
test, to be examined. The response to this information
thus requires input from several of areas.
There are a number of possible approaches to obtaining
test metrics for analogue circuits, including the sensitivity
analysis that is available in most simulators. Our
methodology is more useful than this approach for a
number of reasons. Firstly we are able to work with
multi-stage test processes which include non-electrical
tests; this is outside the domain of pure sensitivity
analysis. Use of a capability-based approach facilitates
the simultaneous processing of hard and soft defects by
providing a metric which is the same for both (instead of,
say, coverage percentage and sensitivity). Furthermore,
the use of capability and cost scaling allows test to be
considered along with manufacturing and design within
the same framework.
The complexity of modern designs is a challenge to any
automated analysis of quality or testability. However, our
methodology does not impose a specific detail level on
circuit models used, allowing complex systems modelled
at high level to be used along with detailed low level
models such a SPICE. In the context of test, high-level
fault simulation is not well developed at present, but there
is ongoing work in this area. Meanwhile, our approach is
flexible enough to target problem areas of a design even if
the complete system if beyond the capabilities of any
existing fault simulation or test analysis tool.
7. Conclusions
The trade offs between design, manufacture and test in
electronic systems manufacture are complex but under-
standing of these issues is of vital importance in
optimising company performance. We have presented a
methodology which places design, manufacture and test
capability in a common framework of quality costs based
upon the Conformability Analysis methodology. In order
to fit within this framework we have introduced the new
measure of test capability based on Cpk. The information
that this novel analysis methodology provides forms the
basis for a quality cost based fault ordering process which
optimises the use of testability analysis effort. The
information also allows the trade-off between component,
manufacture, test and quality costs to be explored and
directs design effort towards those areas where it is most
cost effective.
Acknowledgment
This work was supported by EPSRC Grant GR/M39855
and is in collaboration with TRW Automotive, Celestica
and The University of Greenwich.
References
1. R. Batchelor and K.G. Swift, BConformability Analysis in Support
of Design for Quality,^ Proc. I Mech E Part B-Journal of
Engineering Manufacture, vol. 210, No 1, pp. 37–47, 1996.
2. I.M. Bell and S.J. Spinks, BAnalog Fault Simulation for the
Structural Approach to Analog and Mixed-Signal Testing,^ Proc.
IMSTW, 1995, pp. 10–14.
3. S. Bittanti, M. Lovera, and L. Moiraghi, BApplication of Non-
Normal Process Capability Indices to Semiconductor Quality
Control,^ IEEE Trans. on Semiconductor Manufacturing, vol. 11,
No 2, pp. 296–303, May 1998.
 The Effectiveness of Test in Controlling Quality Costs
4. S.W. Field and K.G. Swift, Effecting a Quality Change, London,
UK: Arnold, 1996.
5. J.M. Gilbert, I.M. Bell, and D.R. Johnson, BCircuit Design
Optimization Based on Quality Cost Estimation,^ Qual. Reliab.
Eng. Int., vol. 21, No 4, pp. 367–386, 2005.
6. E.L. Grant and R.S. Levenworth, Statistical Quality Control, New
York: McGraw-Hill, 1988.
7. I.L. Huertas, BTest and Design for Testability of Analog and Mixed-
signal Integrated Circuits: Theoretical Basis and Pragmatical
Approaches,^ Proc. ECCTD Conf, 1993, pp. 75–156.
8. Z. Jaworski, N. Mariusz, and W. Kuzmicz, BExtension of inductive
Fault Analysis to Parametric Faults in Analog Circuits with
Application to Test Generation,^ Proc. 15th IEEE VLSI Test
Symposium, 1997.
9. D.R. Johnson, Conformability Analysis for the Control of Quality
Costs in Electronic Systems, Ph.D. Thesis, UK: University of Hull,
2004.
10. I.M. Bell, D.R. Johnson, and J.M. Gilbert, BConformability Analysis
Based Test Quality Cost Estimation,^ Proc. 9th IEEE Int. Mixed
Signal Testing Workshop (IMSTW03), June 2003, Seville, pp. 268–
273.
11. A. Kelly, Conformability Analysis for Electronic Products, MEng
Dissertation, UK: University of Hull, 1997.
12. L.C. Laranjeira, J. Machado da Silva, and J. Silva Matos,BA Tool
for Fault Extraction in PCBs,^ Proc. European Test Workshop
2000, Portugal: Cascais.
13. A.M.D. Richardson and A.P. Dorey, BReliability Indicators,^ Proc.
ESREF, Germany, October 1992, pp. 277–285.
14. M. Sachdev, BA Realistic Defect Oriented Testability Methodology
for Analog Circuits,^ J. Electron. Test: Theory and Applic., vol. 6,
pp. 265–276, 1995.
15. K. Hird, K.P. Parker, and B. Follis, BTest coverage: what does it
mean when a board test passes?,^ Proc. IEEE International Test
Conference, 2002, pp. 1066–1074.
16. J.P. Shen, W. May, and F.J. Ferguson, BInductive Fault Analysis
of MOS Integrated Circuits,^ IEEE Design & Test of Computers,
vol. 2, pp. 13–26, Dec 1985.
17. S.G. Shina, Six Sigma for Electronics Design and Manufacturing,
New York: McGraw-Hill, 2002.
18. S. Spence and R.S. Soin, Tolerance Design of Electronic Circuits,
London: Imperial College, 1997.
19. S.J. Spinks, I.M. Bell, C.D. Chalk, and M. Zwolinski, BGeneration
and Verification of Tests for Analog Circuits Subject to Process
Parameter Deviations,^ Proc. IEEE Symposium on Defect and
Fault Tolerance in VLSI Systems, Oct 1997.
307
20. K.G. Swift, M. Raines, and J.D. Booker, Designing Capable and
Reliable Products, Oxford, UK: Butterworth, 2001.
21. G. Taguchi, Introduction to Quality Engineering, New York:
UNIPUB/Quality Resources, 1986.
22. G. Tennant, Six Sigma: SPC and TQM in Manufacturing and
Services, Gower Publishing Limited, 2001.
23. D. Wood and S. Croxall, BFailure Mode and Effect Analysis,^ Proc.
Conference on Tools and Techniques in Quality Engineering
Manchester, October 1989.
James M Gilbert completed a BSc in Electronic Control and
Robot Engineering in the University of Hull in 1986 and completed
a Ph.D. in Robot Control at the same University in 1989. He was
appointed as a lecturer, and subsequently senior lecturer, in the
Department of Engineering at Hull University in 1989. Since then
he has been involved in research in electronic manufacturing
processes and design for manufacture of electronic systems.
Ian M. Bell received the BSc(Hons) degree in Electronic
Engineering from the University of Hull, Hull, England, in 1986.
From 1986 to 1987 he worked as an engineer in Centre for Applied
Electronics in Hull, and from 1987 to 1989 as Research Assistant
at the University of Hull, working on testability analysis. Since
1989 he has been a lecturer in the Department of Electronic at the
University of Hull. His research is focused on mixed signal circuit
testing and design for quality and manufacturability. This work
includes design of self-testing circuits, design and test of micro-
electrochemical lab on a chip systems, supply current based testing
of integrated circuits, modelling and simulation of faults in
electronic systems, and the analysis of testing issues in electronics
manufacture. He is member of the IEEE and an Associate Editor
of IEEE Transactions on Circuits and Systems, Part I and Part II
and a member of the programme committee of the IEEE Mixed
Signals Testing Workshop. He is also a member of the IEE.