Scribd Logo
Upload

Welcome to Scribd!

  • 20 views

    Clase TEEL 3231 Electrónica I JFETS Self Bias Y Voltage Divider Configurations 15 de Noviembre 2021

    Uploaded by

    Yarielies Cruz Arriaga
    This document provides an analysis of the self bias configuration of a JFET. It includes the following key points: 1) It presents the self bias configuration circuit of a JFET with a drain supply voltage VDD, drain resistor RD, and source resistor RS. 2) It derives the JFET drain current ID equation in terms of the pinch-off voltage Vp, drain-source voltage VDS, and gate-source voltage VGS. 3) It works through an example circuit with given parameter values to calculate the quiescent point voltages and currents, including VGS0, VDS, VS, and VD.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content

    You might also like

    Clase TEEL 3231 Electrónica I JFETS Self Bias Y Voltage Divider Configurations 15 de Noviembre 2021

    Uploaded by

    Yarielies Cruz Arriaga
    20 views12 pages
    This document provides an analysis of the self bias configuration of a JFET. It includes the following key points: 1) It presents the self bias configuration circuit of a JFET with a drain supply voltage VDD, drain resistor RD, and source resistor RS. 2) It derives the JFET drain current ID equation in terms of the pinch-off voltage Vp, drain-source voltage VDS, and gate-source voltage VGS. 3) It works through an example circuit with given parameter values to calculate the quiescent point voltages and currents, including VGS0, VDS, VS, and VD.

    Original Description:

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    This document provides an analysis of the self bias configuration of a JFET. It includes the following key points: 1) It presents the self bias configuration circuit of a JFET with a drain supply voltage VDD, drain resistor RD, and source resistor RS. 2) It derives the JFET drain current ID equation in terms of the pinch-off voltage Vp, drain-source voltage VDS, and gate-source voltage VGS. 3) It works through an example circuit with given parameter values to calculate the quiescent point voltages and currents, including VGS0, VDS, VS, and VD.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    20 views12 pages

    Clase TEEL 3231 Electrónica I JFETS Self Bias Y Voltage Divider Configurations 15 de Noviembre 2021

    Uploaded by

    Yarielies Cruz Arriaga
    This document provides an analysis of the self bias configuration of a JFET. It includes the following key points: 1) It presents the self bias configuration circuit of a JFET with a drain supply voltage VDD, drain resistor RD, and source resistor RS. 2) It derives the JFET drain current ID equation in terms of the pinch-off voltage Vp, drain-source voltage VDS, and gate-source voltage VGS. 3) It works through an example circuit with given parameter values to calculate the quiescent point voltages and currents, including VGS0, VDS, VS, and VD.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as pdf or txt
    of 12

    Clase TEEL -3231 15 Noviembtl 2021

    JFETS : SELF BIAS CONFIGURATION


    -

    Ana /isis DC
    '

    OVDD :

    {
    +
    ✓•DD IDSS

    ,=•a§¥É☐
    /
    RD ↳
    c- v0

    Éi-¥µ
    ±
    "

    [É¥É{Éɱs
    km

    Ra }
    £9s _I=±s
    VRs= IDRS

    IDq=IDss( ¥] 1-
    KUL
    -
    VGS -
    URS __ 0

    V65 VRS

    -I Z
    = -

    =I☐ss(
    V6s=-Ii
    1-
    Vp

    ID =
    Iiss ( +
    t→fg_)2
    A T

    :i÷÷:÷÷÷÷÷÷
    -
    D

    9 toss 65=0 IDs ⑦A


    , -
    -

    . '

    tf IDss/q
    -
    -
    i - -
    *

    l l
    l l l ✓ ID Rs
    Gsi -

    ←①-
    Vgs Vp VGS ftp.VGSA
    IDSSZRSZ
    VGSVgs
    -
    - =

    - -

    KUL ( desde ground a Urso )

    VRS ftp.s-VRD-VDD-0
    ✓ Ds =
    Vpp -
    Ups VRD - -
    UDD -
    Is Rs IDRD
    -

    ID = Is

    VDs=VDD-Io(Rs-R#T
    Us - ID Rs VG -
    - O =3 ID - Is
    - -
    -

    |VD=UDs-Vs=UDD-URT#
    Pa 's 429
    Example 7.2
    Determine a) Vaso b) Ioa ,
    c) Vds d) Vs e) Vg
    f) VD
    v
    •
    ZOU
    ) VGSQ
    A

    ID f I +
    Vgs -
    ID Rs
    { 3.31EUR
    =
    -
    ,
    VD
    Escojo
    #
    • D -

    8mA
    ID= 4mA
    G +
    Loss =
    ,

    Rafn
    .
    YDS
    1-
    Vas
    -
    • s Vp =
    -
    TeV Vas
    '
    = -
    ④ mA)G Kr )
    i'vs
    -

    = -
    4V
    -
    -

    TH
    " ID ID -
    - Swiss
    la 2
    El punto Q es
    a
    (8mA) ( )

    i i.io#.X
    intersession de c, Vass - l K
    amebas Curva's 2 -

    Dss V
    8mA = 8
    E
    -
    - - -
    - -

    ( ID2
    I ,

    Ya
    "

    l
    .
    :*
    Up/z= 6/2=-3V
    l ae - -

    Ii
    .-
    -

    \
    l
    r l l

    v.si:S: 'm "


    't:b "

    Vos q u¥¥¥ :3?m ¥ .


    b) El punto Q ( quiescent point )

    Vasai - 2.6 V Ig =
    2.6mA

    C) Vps = VDD -
    ID ( Rs t RD )
    = 20 V -
    (2.6mA)( 1kt 3.3k)

    = Zou - 11 . 18 V =
    8.82 V

    VDs=8.8€T
    d) Vs = I, Rs i G. 6mA) ( kn )
    Vsi
    es
    Vai OV

    f) VD VDS + Vs ⇐ 8.82 Vt
    2.60=1-1.42 V
    ✓D = Vsp -
    URD = 20 V -
    ( 2. lend)(3.3k)
    = Lov -
    8.58 V

    -11.422
    Enervate el
    Example 7.3
    Punto Q si

    a) Rs - loose
    +
    -
    D

    p
    b) Rs IO kn

    !.÷i÷¥
    -

    IDSS

    H
    oomf
    & g-
    - -
    - -

    -
    ID 4mA -

    I Q I
    i
    '
    •- Ipo,
    " ""
    .
    us:
    I go - il 7

    l:
    .-

    i Q i
    :
    Ips 8Mt
    1ms

    ÷
    '"
    iO Vsg , -
    (8nA) GOO
    -

    Vgj Vp
    f Voss 0.80
    IDQF 6.2nA

    ¥ Q

    "¥'
    Irs -
    - 4ms
    v.s.az - iv

    ftp.iqkrs-ioor
    ✓Gsi Cmd)(l0k)= lov
    -
    -

    T
    -
    D=

    i.QIDQ-0.SI
    §
    ID - 0.5ms

    Vagif B)( 10K)=


    6Sf=
    ' - su
    ✓
    Voltage Divider Configuration
    t ""

    fr
    ÷{
    ""

    R r,

    tianya.f.
    ae/IDTvo4Ya
    .
    ,

    R2
    { Rs Ics
    ± ÷ ±.

    ¥EI
    .
    ,

    q
    . r..

    ÷!¥÷:: : ÷÷:
    RD ✓
    ①A Rss Is Rs = ID Rs
    IGE f Io
    → KUL
    •
    AID

    ÷¥an÷÷
    • IDSS

    :3:
    t
    Igg
    " •
    -

    !
    -

    #•s . .

    VP VGSQ ⑦ +
    Vg Vgs
    -

    Ugg
    si
    -
    → Vast Va
    ✓ GS -

    -
    VG-IDRSID.am
    Vas VG - tf
    -

    Sif¢;?va VG i
    -

    ID Rs
    Iors

    ID
    -
    -
    Vulpes K
    Paige Example 7.4
    -

    VD D= 16 V
    A) IDQYVQSQ

    ÷i¥¥ee
    b) VT
    R,
    2-4 # R, aus

    8mA
    10mF IDs, =

    }
    5mF Vpi -
    4V
    Rz } 270k -1
    =zoµf d) VDS
    \ /
    i.5k Rs

    ¥ AT IT
    E) VDG

    a) Ip = IDs
    # 87,1 = - 2nd

    Vass Vp/z - i - zu

    Vai "z÷ %fE.to#oE


    -
    '
    -

    ✓
    Gsi Ug -
    ID Rs = 1.82 V -

    IDCI.sk)
    -
    -
    IDIOMS Vos I
    -71.82 V
    (

    VGSFOV Ug ID Rs

    t.IE?.ssIo=uei-?sTe
    --

    i÷
    Rs
    7

    -
    6
    Ips Z
    1.21mA

    - 5

    -
    4

    -• 1
    "

    •#.# Iml

    -4
    → z% O
    - 5 I
    '
    2 3 4 6

    Was ,

    IDQ? 2.5mA
    §
    4

    Voter '
    '
    b) VD I VDD -

    IDRD
    = 16 V -
    ( 2.5ms )( 2.4k)
    VD

    c) Vs =
    ID Rs
    -

    -
    (2.5ms)( 1. 5k)
    Vs t
    = 3.75 V

    d) VDS = VDD -

    Ig ( RDTRS)
    '
    -
    16N -
    2.5ms ( 2.4kt I - )
    5k

    VDS --6.25V_

    ✓ = VD -
    US = 10 V -
    3.75
    Ds

    ✓Ds=6.25#
    ¢ ) VDG = VD Vai
    -

    lov -
    1.82 V
    ✓ DG = 8.18 V
    -
    Asignacioni .

    # 6
    #a
    self-Bias-onf.gg . Pag 474
    475
    Prob 8 ,
    9
    ,
    11

    Voltagedivedercouf.gl
    3 ,
    14 ,
    15

    You might also like