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Siemens S7 Status Word - PLCdev
Siemens S7 Status Word - PLCdev
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GE Automation Siemens S7 Status Word
Allen-Bradley
Siemens
PDF Electric &
Supply In Siemens PLCs the Status Word is an internal CPU register used to keep
Do Supply track of the state of the instructions as they are being processed. In
Company order to use STL more effectively it is important to understand the Status
AX Control
Distcache Word and its functions.
Networking Each bit in the Status Word has a specific function to keep track of bit
Hardware
logic (RLO, STA), math (OV, OS), comparison operations (CC0, CC1) and
PLC Programming whether the logic should continue, be nested or start new (/FC, OR,
Handbooks BR). Only the first 9 of the 16 bits are used.
Allen Bradley
Bit Positions
Siemens
Modicon 8 7 6 5 4 3 2 1 0
0 Reset to "0"
Navigation
Book reviews 1 Set to "1"
Online books The status word can be seen by displaying the STATUS column while
Recent posts
monitoring in STL view. The RLO (bit 1) and the STA (bit 2) are also
About
displayed in the RLO and STA column.
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The Most Important Status Word Bits
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The RLO bit stores the running logic state of the currently processing
instructions. Certain bit logic and comparison instruction will turn the
RLO to a 1 when the condition is TRUE and write a 0 when the condition is
FALSE. Other instructions read the RLO (=, S, R) to determine how they
are to execute.
The STA bit reflects the state of the current Boolean address.
If you are used to ladder logic and struggling to understand the purpose
of the RLO and STA it may help to visualize a rung like below. The STA
is used to keep track of the state of the addresses. The RLO is used to
keep track of the state of the rung.
1. At the start the First Check bit (/FC) is zero so an And instruction
will logically mirror the Status bit (STA) over to the Result of Logic
Operation (RLO). In this case the address I0.0 is 1 so the STA is
one and the result of the logic (RLO) will be 1. The A instruction
writes a 1 to /FC.
2. On the second line, the /FC bit is now 1 indicating that this line
needs to use the RLO from the previous line. The address I1.1 is
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on so the STA = 1. The RLO from the last line is 1 and this is
‘anded’ with the current STA with a result of 1 in the current
RLO.
3. The same thing happens on the second line but this time 1 and 0
makes the current RLO = 0.
4. The fourth is the Assign instruction which takes the RLO and writes
it out to the corresponding address. In this case the final RLO = 0
so the output will be off. If M0.0 was 1 then the “Andâ€
operation will evaluate to true making the RLO = 1 which will then
turn on the output Q1.0.
OR (bit 3)
In the event of an overflow (OV bit 5) the OS bit will store the value even
after the OV bit has been reset. The following commands reset the OS
bit: JOS (Jump if OS=1), block call instructions, block end instructions.
The OV bit is set by a math instruction with floating point numbers after a
fault has occurred (overflow, illegal operation, comparison unordered).
The OV bit is reset when the fault is eliminated.
The Condition Code bits provide results for comparison and math
instructions.
Comparison Instructions
0 0 ACCU 2 = ACCU 1
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0 0 Result = 0
0 1 Result < 0
1 0 Result > 0
0 0 Gradual underflow
0 0 Result = 0
1 0 Result <> 0
onto the next instruction for reference. When the BR bit is 1 it enables
the output
of the block (ENO) to be TRUE and thus allow other blocks after it to be
processed. The SAVE, JCB and JNB instructions set the BR bit.
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PCS 7
my question are :
1 what is the difference between PCS7 and STEP7?
2. if the blocks functions are changed if I would use STEP 7 with the CFC
library ?
3. any person does you use the CM 104 gateway from SIEMENS ?
THANK YOU
IEC61850
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