Mounika.

M
+91-8712345673, mounika.morampudi60@gmail.com

EDUCATION
Program Institution %/CGPA Year
Btech in ECE and GITAM University 8.14 2015
Mtech in VLSI
XII Sri Chaitanya Girls college 86.7 2010
X The Sun School 90.0 2008

TOOLS ANDTECHNOLOGIES
Programming Languages
Layout Tools
Schematic Tools
Circuit Simulation Tools
Verification Tools
Process Technology
C, Verilog, Ocean scripting
Virtuoso Layout L & Layout XL
Virtuoso (version IC6.1.3.72, IC6.1.5.72) Schematic editor Cadence
ADE L & ADE XL
ASSURA, PVS, CALIBRE
TSMC28nm, TSMC40nm, GF28nm, TSMC65nm, GF14nm

WORK EXPERIENCE (1 year 8 months)

Gigacom Semiconductors pvt.ltd
Analog IC design Engineer (July 2015 – October 2016)
14nm Finfet Simulations
● Conducted pre and post simulations on multiple Amplifiers and Receiver Bias and analyzed results to extract
data needed by the client to meet the required specifications of the blocks.
● Calculating Gain and Bandwidth of all the amplifiers by AC analysis and check the frequency range where the
amplifiers are compatible to the client requirement.
● Power Supply Rejection Ratio (PSRR) of the amplifiers is calculated and the power wastage is documented for
the required frequencies.
● DC analysis was done to calculate the operating points of the finfets and assured that all the finfets were in
saturation region for block stability. DC power is also calculated and made sure power consumed by each
block across 121 corners was within range defined.
● Transient analysis for the frequencies within the range of operation was done to note down the delays for
amplifiers across all 121 corners.
10GBase-KR(28nm)
● Device characterization for all the available mosfets in technology library to select the mosfets that would be
compatible for project.
● Drafted development work scope proposals for submission to senior designers by running simulations (AC
and DC) for Bandgap reference with output voltage of 1.2V.
● Designed current mirrors for the current of 50uA, 25uA, 10uA with low power consumption and a deviation
of 2% across all 121 corners.
● Monte Carlo simulations for stability analysis for Bandgap reference was done to make ensure the output
voltage be 1.2V.
● Top level simulation for Receiver Termination block had been done and worked for a differential resistance
of 100 Ohms across PVT.

Ferventz Semiconductors pvt.ltd

Analog IC design Engineer(December 2018 – March 2019)
 Trained juniors with mosfet basics and helped them understanding its characterization.
 Taught juniors completely about the tool for designing and simulating.
Layout Projects (UMC LP Reciever -28nm)
 Floor plan for bandgap had been designed to make sure BJTs and resistors were matched providing guard
rings.
 Optimized layout had been done for low dropout regulator with current of 25mA using metal stacking to
match EM values and provide least resistance and save routing area.
 LVDS amplifier layout had been in half cell symmetry using cloning and half routing to save time.
 Comparator was designed with matching the current mirrors and differential pairs to get equal parasitics.
Analog and digital blocks were separately and put double guard rings to avoid noise from digital blocks to
reach analog diff pairs.

CUSTOM LAYOUT DESIGN SUMMARY

 Underwent intensive training in CUSTOM LAYOUT in designing 130 nm & 45 nm technology

using cadence tools from June in Core Circuit Semiconductors, Hyderabad
 Cadence Virtuoso layout editor-floor planning and routing
 Assura verification-DRC & LVS
 PVS verification- DRC & LVS
 Technology: TSMC 130nm & 45nm

Projects handled in Custom Layout Training

STANDARD CELLS DITIGAL LAYOUT DESIGNING

Tools: Virtuoso Layout Editor, Assura Verification (DRC, LVS)
Cells designed: INVERTER, NAND, AND, NOR, OR, MUX, EX-NOR, EX-OR
Targeted technology: TSMC 130nm
Challenges: Followed standard cell height i.e. 9 tracks, maintained cell width in multiples of contact
pitches, Maintained Half DRCs, Routing done using only metal1.
ANALOG BLOCKS
LEVEL SHIFTER DESIGN
Targeted technology: GPDK 40nm.
Challenges: Took care of PSUB2, antenna effect, and drew the layout in optimized way.
OPERATIONAL AMPLIFIER (OP-AMP)
Targeted technology: GPDK 40nm.
Challenges: Devices matching WRT PVT, Providing Dummy's to protect the critical devices, providing
guard rings, and drawing the layout in optimized way.
COMPARATOR
Targeted technology: GPDK 40nm.
Challenges: Matching is taken care for current mirrors and differential amp, Matched Differential pair
drain routes to get equal parasitics, Followed EM values for routings, separated digital and analog
devices, Guadrings are added for matched pairs.
BAND GAP DESIGN
Targeted Technology: GPDK 40nm.
Challenges: Applying matching techniques for BJT's and Resistors, providing guard rings, and drawing the
layout in optimized way.
LDO_TOP(25mA) DESIGN
Targeted Technology: GPDK 40.
Challenges: Maintaining EM as output current is 25mA. Metal stacking to provide least resistance and
save the routing area, Care taken on feedback route, followed matching for OPAMP devices.
 FINFET
Targeted technology: GPDK14nm
Challenges: Fins Alignment, Identification of layers, Understanding the DRC rules, Local interconnect or
Middle - Of – Line (MOL), Snapping, Matching.
Projects: Inverter, Delay amplifier

SKILL SET
 DC Analysis, Transient Analysis, AC Analysis, Stability Analysis across all corners (Pre and
Post layout)
 Device characterization for choosing devices to use on projects
 Documenting the results across all corners and analyzing them for troubleshooting
 Monte carlo simulations for bandgap
 Config view sch/pex extraction simulation
 Strong MOSFET basics and its operation.
 Layout Experience