An Incremental Zoom Sturdy MASH ADC

Ki-Hoon Seo, Il-Hoon Jang, Kyung-Jun Noh and Seung-Tak Ryu

Mixed-Signal Integrated Circuits Laboratory
School of Electrical Engineering, KAIST
Daejeon 31414, Republic of Korea
Email: {khseo, ilhoon0925, nkj0106, stryu}@kaist.ac.kr

Abstract— This paper introduces a speed-enhanced

incremental ADC architecture for high-resolution low-power 
sensor applications, incorporating a third-order sturdy MASH
 
modulator. Unlike previous sturdy MASH ADCs, owing to the   




properly modified loop filters in the 2-1 sturdy MASH, the
quantization noise of the first noise-shaping loop could be
cancelled out. The proposed ADC with a 4b coarse SAR ADC

and a 2-1 sturdy MASH modulator is designed for a 0.35um 
CMOS process. Simulation result achieved an 18b resolution in

conversion time of 606 us, consuming 161 uA current under a 3.3   


V supply.

Keywords—incremental ADC; Zoom ADC; sturdy MASH; Fig. 1. Sturdy MASH DSM [8].
delta-sigma modulator; switched-capacitor modulator


I.
INTRODUCTION  

 



 
As various applications such as Internet of Things (IoT)
require power-efficient sensing capability, demand for low-
power high-resolution analog-to-digital converters (ADCs) also
increases. Owing to the advantages of area- and power-
efficiency, SAR ADCs have been utilized as a popular solution
for moderate-accuracy readout purpose in many sensing

applications [1-2]. On the other hand, when high DC accuracy
and high signal-to-noise ratio (SNR) are required, incremental
ΣΔ modulator (IDSM) has often been a best choice [3-6].
However, due to the limited conversion speed, IDSMs are
utilized mostly for very slow applications. For expansion of
IDSM’s application for higher sampling rate, several design
choices can be considered such as higher-order loop filter
design. In order to reduce the performance degradation of a
high-order Multi-stAge noise-Shaping (MASH) architecture [6,
7], sturdy MASH (SMASH) architecture [8] can be chosen to
eliminate the need for matching between analog and digital
filter characteristics. While the remaining quantization error of
the first stage modulator in the original SMASH architecture
limits the noise performance, the delay-based noise-canceling
SMASH in [9] showed a possibility of complete cancellation of
quantization noise of the first stage, but with a remaining issue
of very tight timing requirement for actual implementation. As
an alternative approach for high performance sensing, a zoom
ADC architecture consisting of a power-efficient high-speed
coarse ADC and a fine IDSM have shown possibility of
application expansion with IDSM [10].
In this paper, we introduce a new architecture of IDSM,
incremental zoom SMASH architecture for fast conversion and
low power consumption. It employs power-efficient zoom
978-1-5090-6389-5/17/$31.00 ©2017 IEEE




 
Fig. 2. Delay-based noise cancelling SMASH DSM [9].
architecture and high-order SMASH architecture. While the
zoom ADC architecture reduces the output swing the of
integrators, the SMASH architecture alleviates the opamp gain
requirement for them. With these two features, fast and low-
power high resolution ADC is implemented.
II.
INCREMENTAL ZOOM SMASH ARCHITECTURE
A.
Improvement of DNC SMASH Architecture
Fig. 1 shows the original SMASH architecture in [8]. By
combining analog outputs from the cascaded two loop filters,
SMASH DSM achieves high-order noise-shaping characteristic
as (1) describes.
YSMASH = STF1X + NTF1(1-STF2)q1 – NTF1NTF2q2 (1)
Unless 1-STF2 = NTF2 or STF2 = 1, however, overall noise
performance of SMASH will still be limited by q1, which is a
drawback of SMASH architecture. In order to solve this
problem, a Delay-based Noise Canceling (DNC) SMASH
structure was introduced in [9], as shown in Fig. 2. Contrary to
1013
the original SMASH structure, DNC sturdy MASH structure B.
System Level Design of Incremental Zoom SMASH
leaves only shaped q2 by eliminating q1. By combining the zoom and SMASH structures, an
YDNC = z-1STF1X + NTF1(z-1 – STF2)q1 – NTF1NTF2q2 (2) incremental zoom sturdy MASH structure is proposed as
depicted in Fig. 4. It consists of a 4bit coarse SAR ADC and
Since it is not easy to set STF2 = 1 in discrete-time domain fine 2-1 SMASH DSM with ± 2LSB redundancy of coarse
implementation without any delay, STF2 = z-1 is implemented resolution. With the reduced swing requirement by virtue of the
by adding a delay (z-1) to NTF1. In order to avoid the excess zoom characteristic, the amplifier gain requirement is much
delay problem arisen by the added delay term in the loop, a fast relaxed, resulting in low-power realization.
path around the input of the first stage quantizer is constructed.
However, there still is a timing issue: the 2nd stage output The signal transfer function (STF) and noise transfer
feeds to the 2nd stage input without any delay. This no delay function (NTF) of the first loop are defined as (3) and (4),
causes a timing issue on discrete-time domain implementation. respectively.
To realize a timing-issue-free DNC SMASH structure in
discrete-time domain, a new structure is proposed in this paper, 2 z −1 − 3z −2 + 1.5 z −3 (3)
as Fig. 3 illustrates the development procedure. The original STF1 =
1 − z −1 + 0.5 z −3
delay compensation path from the output is disconnected and a
new local compensation path is added (Fig. 3a). NTF1 remains
as the same before, but the transfer function of the second stage z −1 (1 − z −1 )2 (4)
to the final output (NTF1’) changes to (1+z-1)NTF1’, making NTF1 =
1 − z −1 + 0.5 z −3
the overall loop unstable. In order to solve this problem, the
feedback gain of the second-stage loop is doubled as shown in NTF1 shows a second-order noise-shaping with a single
Fig. 3b. By doing this, STF2 and NTF2 acquire additional term delay. The transfer functions of the second loop are calculated
of (1+z-1) in their denominator. Owing to this modified transfer as
functions, the additional term of (1+z-1) cancels out completely
at the final output. Consequentially, only noise-shaped q2 z −1 , 1 − z −1
STF2 = NTF = (5)
appears at the final output. 1 + z −1 2
1 + z −1
As explained earlier, the 1+z-1 term in the denominator is

from the feedback gain of 2 in the second loop. NTF2 has a first
order noise-shaping characteristic. The transfer function from
  the output of the second loop to the final output is
     

(1 + z −1 )(1 − z −1 )2 (6)
NTF1 ' =
 1 − z −1 + 0.5 z −3
  

Note that the NTF1’ shows a second-order noise-shaping


 
characteristic with an additional term of (1+z-1) due to the local
  compensation path. Including SAR decision result, overall
transfer function is
(a) Y = DSAR + Dstage1 – Dstage2
(1 − z −1 )3 (1 − z −1 )3
 = X+ −1
q −
−3 1
q3 (7)
1 − z + 0.5 z 1 − z −1 + 0.5 z −3
 
     

The quantization noise from the SAR conversion, q1, is
multiplied by 1-STF1. Because 1-STF1 implies third-order
 noise-shaping, q1 is shaped in third order. The quantization
  

 noise from the first loop, q2, is cancelled by the proposed DNC

 technique. Lastly, q3, the quantization noise of the second loop,
 
 
is multiplied by both NTF1’ and NTF2, resulting in third-order
 noise-shaping. As a result, third-order shaped noises of q1 and
  q3 and the non-modulated input signal X appear at the final
 
output. Owing to the feature of third-order noise-shaping, high
  
resolution is achieved with improved conversion speed.
 

(b) III.
CIRCUIT IMPLEMENTATION

Fig. 3. Proposed DNC SMASH architecture. Fig. 5 shows the circuit implementation of the proposed
incremental zoom SMASH ADC with the operating timings.
For simplicity, single-ended circuits are described. The 4b
coarse SAR ADC shares the input capacitors with the IDSM.

1014

 




   
 

 

z −1

z −1

  
1 − z −1 1 − z −1  




 
 
 







 

 

z −1

1 − z −1

Fig. 4. Proposed incremental zoom sturdy MASH ADC.

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Fig. 5. (a) Implementation of Incremental zoom sturdy MASH modulator and (b) timing diagram.

During the coarse SAR conversion, the integrating frequency. The high frequency chopping ripple is eliminated
capacitors of DSM are initialized. Coarse conversion consists by the final digital decimating filter.
of 5 clock cycles including sampling phase and four decision
phases. With the coarse decision result, 2-1 SMASH DSM For quantization error extraction from the first loop (q2),
subtraction operation is needed. Since accurate subtraction in
works. Sampling capacitors sample their input signal and each
analog domain requires high-gain opamp, it will lead to power
stage generates output during phase1 (φ1), and integration is
burden. By recognizing that the output of the subtraction is
conducted in phase2 (φ2). This DSM operation is conducted given to the second loop, instead of using a dedicated opamp
for the designed number of cycles for the target accuracy. The for subtraction, in this work, the amplifier for the integrator in
final output is generated by combining both the SAR decision the second loop is shared in alternating manner. During the
result and the filtered DSM result. For DC offset and 1/f noise, subtraction phase (for q2 extraction), the feedforwarded input
chopper stabilization is applied to the first amplifier. The signal, two output signals from the two integrators in the first
frequency of chopper stabilizer is half of the sampling

1015
loop and the feedback DAC (DAC3) signals are added on the
summing node while other capacitors are reset except for the
integrating capacitor. In the following phase, the added signal
in the previous phase and the signal from the feedback DAC of
the second loop (DAC4) are integrated in the feedback
capacitor. By separating capacitors for summing and
integrating, q2 extracting and integration for the second-loop
could be realized with a single opamp.
Since SMASH architecture has a relaxed opamp gain
requirement, low gain single-stage amplifiers can be utilized.
Based on simulation result, the first and second opamps are
designed to have a gain higher than 35 dB to fulfill SQNR
higher than 120dB. From this, all three amplifiers for
integrators are designed in a single-stage configuration.
IV.
SIMULATION RESULTS
The proposed incremental zoom sturdy MASH was
designed for a 0.35um CMOS technology. For 110dB SNR
performance from KT/C thermal noise consideration, the input
sampling capacitor of the first integrator was designed to be
5.2pF. The clock frequency is 1MHz and the conversion time is
606 us. The ADC
draws a total of 161 uA current from a 3.3
V supply. The input signal range is 6.6Vpp, and the design
target of 110 dB SNR were achieved. Fig. 6 shows the FFT
simulation result. The linearity of the ADC is estimated as 4
ppm level and the Figure of Merit (FoM) is 171.9dB, achieving
relatively high performance in comparison of other ADCs. In
Table I, the performance of the designed ADC is summarized
and compared with previously reported incremental ΣΔ ADCs.
Although the same sampling frequency as in Agnes’ work is
used for fast conversion, this work consumes significantly less
power because the requirements of the opamps are relaxed by
applying zoom and sturdy MASH architecture.
1016
Fig. 6. FFT simulation (DSM mode).
ACKNOWLEDGMENT
This work was supported by the Institute of Civil-Millitary
Technology Cooperation, and the CAD tools were supported
by the IDEC of KAIST.
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