1506 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 13, NO.

6, DECEMBER 2019

A 769 µW Battery-Powered Single-Chip SoC With

BLE for Multi-Modal Vital Sign Monitoring
Health Patches
Shuang Song , Member, IEEE, Mario Konijnenburg , Member, IEEE, Roland van Wegberg,
Jiawei Xu , Senior Member, IEEE, Hyunsoo Ha , Member, IEEE, Wim Sijbers ,
Stefano Stanzione, Member, IEEE, Dwaipayan Biswas , Member, IEEE, Arjan Breeschoten, Peter Vis,
Chris van Liempd, Chris van Hoof, Member, IEEE, and Nick van Helleputte , Member, IEEE

Abstract—An all-in-one battery powered low-power SoC for
measuring multiple vital signs with wearables is proposed. All func-
tionality needed in a typical wearable use case scenario, including
dedicated readouts, power management circuitry, digital signal
processing and wireless communication (BLE) is integrated in a
single die. This high level of integration allows an unprecedented
level of miniaturization leading to smaller component count which
reduces cost and improves comfort and signal integrity. The SoC
includes an ECG, Bio-Impedance and a fully differential PPG
readout and can interface with external sensors (like an IMU). In a
typical application scenario where all sensor readouts are enabled
and key features (like heart rate) are calculated on the chip and
streamed over the radio, the SoC consumes only 769 µW from the
regulated 1.2 V supply.
Index Terms—Bio-impedance, Electrocardiogram, low power,
Photoplethysmogram, readout frontend, SAR-ADC, SoC.
I. INTRODUCTION
ONTINUOUS vital sign monitoring is of paramount im-
C portance in remote health monitoring for chronic diseases.
Medical grade wireless and wearable bio-sensor systems with
high user comfort and low cost that can be used at home pose
a much more attractive solution than hospital-based monitor-
ing systems. For a number of chronic diseases like congestive
heart failure, obstructive sleep apnea, and chronic obstructive
pulmonary disorder and other cardio-pulmonary disorders, such
systems should be able to asses key vital signs including heart
Manuscript received July 16, 2019; revised September 6, 2019; accepted
September 25, 2019. Date of publication October 2, 2019; date of current version
December 31, 2019. This paper was recommended by Associate Editor H. Jiang.
(Corresponding author: Shuang Song.)
S. Song, W. Sijbers, D. Biswas, C. van Hoof, and N. van Helleputte
are with the imec, 3001 Heverlee, Belgium (e-mail: shuang.song@imec.be;
wim.sijbers@imec.be; dwaipayan.biswas@imec.be; chris.vanhoof@imec.be;
nick.vanhelleputte@imec.be).
M. Konijnenburg, R. van Wegberg, J. Xu, H. Ha, S. Stanzione, A.
Breeschoten, P. Vis, and C. van Liempd are with the Holst Centre, imec,
5656AE Eindhoven, The Netherlands (e-mail: mario.konijnenburg@imec.nl;
roland.vanwegberg@imec.nl; jiawei.xu@imec-nl.nl; hyunsoo.ha@imec-nl.nl;
stefano.stanzione@imec-nl.nl; arjan.breeschoten@imec-nl.nl; peter.vis@imec-
nl.nl; chris.vanliempd@imec-nl.nl).
Color versions of one or more of the figures in this article are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TBCAS.2019.2945114
rate, respiration rate, body water composition, actimetry and
blood oxygenation. Multiple signal modalities i.e., electrocar-
diograph (ECG), bioimpedance (BIOZ), and photoplethysmo-
gram (PPG) are necessary to determine such physiological
parameters, where ECG is for heart signal analysis and heart
activity measurements, BIOZ is to measure respiration and
different kinds of fluids in the human body, and PPG is for pulse
oximetry (SpO2) and blood pressure.
A very small form factor while still maintaining excellent
signal quality and reliability is critical for a good wearable,
especially for medical purposes. Low power consumption is key
to achieve this, since the battery size is usually the biggest and
heaviest part. Additionally, a high degree of integration reduces
the component count which reduces the cost as well as the weight
and bulkiness of the device. The latter are important since this
helps to reduce (motion) artefacts and improves patient comfort.
A typical wearable application, like a health patch or wristband
needs to implement several functionalities. Next to the obvious
sensor readouts, and wireless connectivity, there is generally a
need for digital signal processing as well as a microcontroller
to run the application. Local digital signal processing allows
to calculate basic features and asses alarm situations reducing
the need to stream data continuously over the radio which
reduces overall system power. Moreover, on-the-node security
functionality should also be included. This not only refers to data
(privacy) security, but also other security features like multi-level
authentication and secure booting. Finally, these devices will all
be battery-powered, so power management circuitry is required
as well.
Currently available SoC solutions for wearable devices have
not reached the desired level of integration. Konijnenburg et al.
[1] proposed a battery powered multiparameter recording SoC
for concurrent ECG, BIO-Z, GSR, and PPG. However, having
the power management unit on a separate chip, the limited pro-
cessing capability (ARM M0) and only wired communication
limit the usability and the options for miniaturization. Schönle
et al. [2] reported a solution including up to 9 channels of ECG, 4
channels of PPG, power management unit and micro processing
unit (MCU), without wireless communication capability. One
of the major reasons for this limited level of integration is the

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SONG et al.: 769 µW BATTERY-POWERED SINGLE-CHIP SoC WITH BLE
Fig. 1. (a) A low-cost single-use health patch using the SoC and (b) The
high-level architecture of the SoC.
rather conventional technology node (180 nm [1], 130 nm [2])
chosen for the analogue frontend. These nodes are not efficient
for high performance on-chip (digital) signal processing.
We propose an all-in-one battery-powered SoC designed for
low-cost single-use health patches (as shown in Fig. 1) allowing
continuous monitoring in a home setting. This SoC is imple-
mented in a 55 nm technology node to allow the integration
of MCU, Bluetooth and digital signal processing accelerators
together with biomedical readout frontends (ECG, BIOZ and
PPG). As a proof of concept, this SoC was integrated in a
disposable health patch shown in Fig. 1. The low number of
components on the PCB, next to the SoC is clearly visible.
The external components include the electrodes, two LEDs, and
photodiode on the flexible patch. The PCB integrates the BLE
(Bluetooth Low Energy) antenna, matching circuit, crystals, (de-
coupling) capacitances and safety resistors. The patch operates
on two ZincAir coin cells.
The remainder of this paper is organized as follows. In
Section II the system architecture is described in detail. In
Section III the two-stage fully differential PPG readout topology
is presented and discussed. In Section IV the operation modes
of the PPG channel are explained to provide a good power-noise
optimization. In Section V, the 13b SAR-ADC with randomiza-
tion dynamic element matching is discussed. Implementation
results are presented in Section VI, and conclusions are drawn
after benchmarking in Section VII.
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1507
II. SYSTEM ARCHITECTURE
The architecture of the SoC and the readout frontend are
explained separately as follows. Fig. 2 shows the block dia-
gram of the SoC. The readouts in SoC include general-purpose
digital interfaces to enable interfacing with COTS sensors (e.g.,
accelerometer or temperature) and dedicated optimized analog
readouts for several biomedical signal modalities that are often
of interest. The proposed SoC has two ECG readouts with
lead-on/off detection, a multi-frequency BioZ readout [3] and
a PPG readout, which is discussed in detail in Section III. After
conversion to digital by means of a 13-bit low-power low-noise
SAR-ADC (discussed in Section V), the data is filtered by means
of a CIC decimation filter together with a low-pass FIR filter and
stored in a FIFO register bank. The FIFO generates an interrupt
signal when a pre-defined sample threshold is exceeded, trigger-
ing the processor or DMA module to capture the FIFO data and
to store in memory.
On the digital side, the SoC features high-performance pro-
cessing capabilities concentrated around the AMBA-AHB (Ad-
vanced High-performance Bus) multi-layer bus interface. It
covers an ARM Cortex M4f processor that supports both fixed-
point and floating-point calculation features. A 192 kB freely
addressable SRAM memory can be used both for program data
as well as other data (such as sample data). Additional memory is
supported by means of an external flash connected to a dedicated
SPI hardware interface for fast read and write operations. The
ARM M4f processor is off-loaded by means of custom hardware
accelerators to support critical features relevant for biomedical
sensor applications. A Direct Memory Access (DMA) module
that allows the system to copy/move data from a register/ mem-
ory source to any register/memory destination. Typically, the
DMA is used to collect data samples from the on- or off-chip
readouts and store directly into memory. The accelerators ‘FFT’,
‘Matrix Processor’ (MP) and the ‘Sample Rate Converter’ (SRC)
[1], [4] perform operations that are often needed in sensor nodes.
The SRC allows the system to make the sample rate of data
streams from (especially) external COTS sensors compatible
with other (internal) sample rates. This eases the development of
advanced algorithms that makes use of samples of many different
data streams. The MP implements vector and matrix operations
allowing to perform efficiently additions and multiplications
on data-streams. The FFT accelerator supports data sizes up to
4096 samples covering both FFT and inverse-FFT operations.
The hardware module ‘Synchronization timestamps’ (STS) [1],
[4] guarantees precisely timed data streams, essential for being
accurate while performing correlation functions. As data is being
collected from a number of signal modalities and even including
data from external sensors, it is critical to be able to properly and
efficiently timestamp the data so that postprocessing algorithms
can adequately handle the various data streams. The STS module
is connected to the AMBA-APB (Advanced Peripheral Bus) bus
structure. This bus is accessible from the AHB master modules
(like the processor and DMA) via the bridge. Many modules are
connected to the APB allowing the master modules to control
those modules.
1508 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 13, NO. 6, DECEMBER 2019

Fig. 2. The proposed SoC integrating readouts, signal processing, interfacing, security, and power management.

On digital interfacing several options are available: Bluetooth
4.2 radio for wireless connections. USB 2.0 for wired connec-
tions, next to a broad list of standard digital interface modules.
Security in wireless sensor nodes is gaining a lot of attention
[5], [6]. Security in medical wireless sensor nodes is even more
important. The SoC supports hardware security [7] for secure
boot, user authentication (symmetric or asymmetric) and data
encryption. These security features are supported by SRAM-
PUF hardware [8] that guarantees a chip-unique key for security
operations.
The chip has been designed in a modular approach. Each
module, analog or digital, has a standard digital interface. This is
AHB and/or APB. Developing a new chip would be more-or-less
an exercise to connect modules to the AHB and/or APB bus,
reducing the chip development time and eases the development
of derivatives.
The chip is implemented in 55 nm technology. Traditionally
analog readout hardware is designed in older technologies such
as 180 nm [1], [9], [10]. Compared to ‘modern’ technologies they
have lower noise, better matching, better leakage performance
and cheap. However, these technologies are not suitable for
advanced RF modules and high-performance digital modules.
The power consumption of those modules would be too high
and the area too large. 55 nm technology has been selected as
being a good compromise between the analog ‘friendly’ older
technologies and high performance, digitally scaled modern
technologies. It allows to integrate powerful processors and
accelerators to be used at lower power ranges and consuming
less chip area. The digital scaling allows to integrate much more
logic and memory. Although the dynamic power is much lower
compared to the older technologies, the leakage power can be
significant. Therefore, power switches have been introduced on
the chip to power off those modules which are not used. In the
SoC each of 6 memory banks can be disabled. The accelerators
and security modules can be disabled when not in use, saving
leakage power. To low the dynamic power during active use
clock gates have been heavily used.
The power management circuitry consists of two LDOs.
One LDO generates 1.2 V supply for the analog front end,
the PLL, the SRAM and the radio circuitry. The other LDO
generates programmable 0.6 V to 1.2 V for the digital core
for future power minimization. The overall efficiency of the
LDOs is around 80%. The high voltage nodes including the
supply for the IO and LED drivers are connected directly to the
battery. The development of a single inductor multiple outputs
converter that improves the overall power efficiency is under
development.
The readout frontend consists of 2 channels of ECG, 1 channel
of multi-frequency BioZ and 1 channel of PPG readout together
with 4 LED drivers. Each readout channel includes dedicated

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SONG et al.: 769 µW BATTERY-POWERED SINGLE-CHIP SoC WITH BLE
Fig. 3. The ECG channel with lead off detection, lead bias, right leg driven (RLD) and body bias circuitry.
frontend amplifier(s) and a SAR-ADC. In addition, the low
power bandgap reference and bias current generation circuitry
provides all bias current for the AFE.
The ECG readout frontend architecture is similar to the one
used in our prior work [9] but now designed in 55 nm. It employs
a current feedback topology with two parallel branches for one
amplification channel, achieving an excellent trade-off between
power, noise, high input impedance and electrode DC offset
rejection. As shown in Fig. 3, a complete set of lead on/off detec-
tion, lead bias, and right leg driving (RLD)/body bias circuitry is
included to fulfill the medical grade signal quality and reliability.
For high performance ECG monitoring, the RLD mode should
be chosen, which improves the common mode rejection ratio.
The RLD loop reduces the common mode component coupled
to the input by the gain of the feedback amplifier. In case of basic
ECG monitoring for heart rate detection only, a lead bias mode
is used, requiring only two electrodes.
The BioZ readout frontend employs a baseline impedance
cancellation technique together with Dynamic Element Match-
ing (DEM) of the excitation current sources to reduce the noise
component [3]. The BioZ channel enables a 2-electrodes BioZ
measurement, improving the user comfort and the usability.
While the ECG and BioZ channel consumes 40 μW and 74 μW,
respectively, the power consumption of the frontend system is
dominated by the PPG channel, especially by the LEDs power
which can be as high as several mW. Therefore, the power
optimization of the system is focus on the PPG channel. A
fully differential two stage PPG readout frontend is proposed to
reduce the LEDs power while achieving the required dynamic
range requirement.
III. THE PPG READOUT CHANNEL
In the section, existing PPG readout frontend architectures
are compared and analyzed together with their limitations. As a
result, a fully differential two stage readout frontend topology
is proposed and discussed in detail.
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1509
A. Existing Topology and Design Considerations
The power consumption of the PPG system is usually dom-
inated by the LED power that can be as high as several mW.
A pulsed LED synchronized to the readout reduces the power
consumption. The signal amplitude of PPG is determined by the
peak current and the input referred noise of readout channel is
largely dependent on the pulse repetitive frequency of the LED
pulses, which will be explained further in Section IV. Therefore,
the only design parameter can be used to reduce power while
keeping the same signal quality is the pulse-width and thus short
pulses and fast readout should be used to reduce LEDs power
consumption.
To meet the stringent requirement on power consumption and
dynamic range, intensive work has been done in optical readout
circuitry for PPG monitoring, resulting in several designs with
mainly two types of topology: single-ended and fully differen-
tial. As shown in Fig. 4, single-ended and fully differential topol-
ogy can apply either resistor or capacitor as gain components
(resistor is used in transimpedance-TIA mode, capacitor is used
in integration-INT mode) with different ambient cancellation
techniques. Namely, in the TIA mode, the ambient component
can be removed by correlated double sampling, and in INT mode,
the ambient is cancelled by swapping the integration capacitor
[4], [11], [12].
The allowed minimum pulse-width is usually determined by
closed-loop input impedance of the readout frontend RF /A0
and the parasitic capacitance of the photodetector (CPD ), τ =
CP D · (RF /A0 ), within the bandwidth of the core amplifier.
It can be observed that the gain should be kept high in a
wide bandwidth, which can lead to high power consumption
of the readout frontend. Spending more power in the readout
frontend is usually beneficial, because the reduction of LED
power resulted from a shorter pulse overwhelms the power rise in
the frontend circuitry. Finally, reducing CP D allows a narrower
pulse-width without any additional power in the frontend, and
thus worth exploration.
1510 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 13, NO. 6, DECEMBER 2019
Fig. 4. Existing PPG readout topologies (a) single-ended (b) fully differential with feedback (c) fully differential with 3 opamps.
Fig. 5. The proposed fully differential PPG readout frontend.
In the single ended topology in Fig. 4(a), a DC bias voltage
is applied to the PD, reducing the CP D . The capacitance can be
reduced by up to 30% by a 0.6 V bias voltage as describe in
Eq. 1, where Si is the silicon dielectric constant, A is the
junction area, μ is the mobility of electrons, ρ is the silicon
resistivity, Vbi is the built-in voltage and VP D is the bias voltage
of PD.
Si 0 A
C=
2Si 0 μρ (Vbi + VP D )
The fully differential topology (Fig. 4(b)) provides 6 dB
more dynamic range than the single-ended one, but the bias-
ing voltage of the PD is usually 0V, which is not desired. A
discrete component-based solution shown in Fig. 4(c) allows
fully differential operation and DC biasing, however the DC
biasing voltage will appear in the output voltage. An AC coupled
second stage amplifier can be used to remove the biasing voltage.
This solution has high power consumption and cannot be used
for SpO2 applications, since the DC part of the PPG signal is
affected. As a conclusion, a fully differential topology with the
DC biasing capability is needed, which motivates the proposed
readout topology.
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B. The Proposed Topology
Fig. 5 shows the proposed fully differential PPG readout
frontend. This topology provides the PD a DC bias voltage,
which is not present in the output voltage and thus achieves a
high DR. This PPG readout includes a current sensing stage,
a transimpedance stage and a DC cancellation current DAC
(IDAC).
In the first stage, the signal current is absorbed by the current
(1) source transistors M1 and M2. This current is copied to the
output stage via voltage N1 and N2. The sub-amplifiers A1 and
A2 consist the local feedback loops, which keep the voltage
on both nodes of the PD to the desired value, set by VBIASP
and VBIASN , respectively. Up to 0.6 V DC bias voltage can
be provided at a supply voltage of 1.2 V. Moreover, the input
impedance is reduced by both the local feedback loop (shown
by orange arrow in Fig. 5) and the main feedback loop (shown
by gray arrow in Fig. 5) in the current sensing stage, resulting
in a <100 Ω input impedance in the unity gain bandwidth. The
sensed current is copied to the second stage and converted to a
voltage on the output transimpedance.
The noise of M1/M2 transistors and I1/I2 current sinks con-
tribute directly to the input referred current noise, therefore, the
SONG et al.: 769 µW BATTERY-POWERED SINGLE-CHIP SoC WITH BLE 1511

Fig. 7. The constant on mode (a) and pulsed mode (b) of the IDAC.
Fig. 6. Measured readout frontend output with a 10 µS settling time.

transistors are degenerated, as well as the ones in the output

stage. Regarding the stability of the current sensing stage, the
local feedback loop keeps the pole from the large capacitance
of CP D at high frequency and the dominant pole located at the
nodes N3/N4. A ∼1 MHz bandwidth is realized, which allows
for a power efficient 10 μs level LED pulse-width (see Fig. 6
[4]), compared to ∼100 μs pulses [13].
In the output stage, a cross-coupled common mode feedback
(CMFB) circuit is implemented to stabilize the CM voltage. The
output voltages are buffered and divided before connected to the
CMFB to improve the linearity. The readout frontend consumes
a current of 112 μW (179 μW including Reference/Bias genera-
tion and ADC), which allows for 25 μA input current without the
IDAC. A low current mode reduces the total power consumption
to 54 μW (121 μW including Reference/Bias generation and
ADC) by switching off part of the current branches in the first
stage, providing a maximum input current of 5 μA, which is
suitable for transmissive mode finger sensors. The DC cancella-
tion IDAC can cancel the DC component of the PPG signal and
further increase the DR, which is explained in Section IV.
IV. OPERATION MODES OF THE PPG CHANNEL
The operation mode of the DC cancellation IDAC and the
sampling scheme on one LED pulse is discussed. The former
increases the input current range and the later reduces the noise,
resulting in an improved DR.
A. IDAC Operation and Measurements
The AC/DC of the PPG signal can be as low as 0.05% depend-
ing on the measurement position. Usually a higher AC/DC ratio
is present on the finger and wrist, a lower ratio can be measured
at on the arms and chest. Moreover, the motion artifact can be as
high as several times of the DC component, putting even higher
requirement on the dynamic range of the readout. Therefore, a
current DAC is used to cancel the DC component from the signal
and allows a higher gain in the amplifier, improving the dynamic
range [12], [14]. There are two operations modes of the IDAC,
the constant on mode and pulsed mode as shown in Fig. 7.
In constant on mode, the IDAC is always on when the PD ac-
tive signal is on (Fig. 8), and the current value is set to around half
of the signal amplitude. Thus, the input current amplitude needs
to be absorbed by the readout frontend is reduced (Fig. 7(a)),
taking advantage of the fully differential topology. For example,
Fig. 8. Timing diagram of the proposed readout frontend.
the input current range can be increased from 25 μA to 50 μA
by a 25 μA constant on current of IDAC. If the frontend is
designed for 50 μA input current, both currents in I1 and I2
needs to be doubled. Moreover, the additional 1/f noise of the
IDAC can be cancelled by correlated double sampling (Fig. 8)
[15]. In DC cancellation mode, the IDAC is synchronized to the
LED pulse, and it is used to cancel the DC component of the
PPG signal. In this mode, the current needs to be absorbed by
the readout frontend is reduced significantly, allowing the use of
a high gain. On the other hand, the IDAC noise is added to the
total input referred current noise of the readout frontend. This
mode is suitable for large PDs with a high signal current together
with a high noise current.
B. Multiple Sample per Pulse Operation
The timing diagram of the PPG channel is shown in Fig. 8.
The correlated double sampling scheme includes one ambient
sample and several signal samples. The multiple sample per
pulse operation is used to reduce noise folding at ADC sampling,
which is unavoidable. Assuming the closed loop bandwidth of
the readout frontend is 1 MHz, the pulse repetitive frequency
(PRF) is usually chosen to be 4 kHz/8 KHz/16 kHz to reduce the
power consumption of the LED. Thus, the noise folding factor
can be as high as several hundred, resulting in noise increase
and a limited DR.
By taking multiple samples per LED pulse at a sampling
rate of 500 kHz and averaging them in digital domain, the
noise folding effect can be reduced effectively. This averaging
operation provides a low pass filtering for the samples obtained
from a pulse. As shown in Fig. 9, for 8/16/32 samples per
pulse, the −3dB bandwidth is 27.0 kHz, 13.5 kHz and 6.7 kHz
respectively [15]. With a pulse frequency (one PPG channel)

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1512 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 13, NO. 6, DECEMBER 2019
Fig. 9. Equivalent frequency response of averaging samples.
TABLE I
THE fs AND POWER OF THE SAR-ADC IN DIFFERENT CHANNELS
of 8 kHz, the noise folding factor is approximately 7, 3.5 and
1.5 respectively, comparing to a factor of 125 in case of only
1 sample per pulse is taken (calculated by 500 Hz bandwidth
and 8 kHz sampling frequency). Increasing the PRF can reduce
the noise folding factor too, however it will increase the power
consumption significantly.
V. DIGITAL ASSISTED SAR-ADC
A 13-bit SAR-ADC (Fig. 10) is reused in ECG, BIOZ and
PPG channels, exploiting its flexibility in exchanging power for
resolution via oversampling. The BIOZ and PPG channel with
a low BW of interest require a larger DR than ECG, and hence
different oversampling ratios are employed, as shown in Table I.
The ADC consists of the sampling switch, the comparator, the
DAC including capacitor array and drives, the SAR logic and
the encoder.
The main design challenge in this SAR-ADC is to increase the
ENOB. While the in-band quantization noise can be reduced by
the oversampling, the harmonic distortion due to nonlinearity of
the DAC cannot be improved [16]. Therefore, the capacitor array
in the DAC employs randomization dynamic element matching
(DEM) in the 6 MSBs by a Pseudo-Random Number Generator
(PRNG) controlled thermometer coded elements, as shown in
Fig. 10. The PRNG consists of linear-feedback shift registers
generating 28b pseudo random number. This number is then
fed to the encoder and generate in every sampling/comparison
cycle a different grouping of the 64 physical capacitors for the 6
MSBs as shown in Fig. 10, by means of an example of 3bits. This
technique turns the harmonic distortion into a noisy spectrum in
the Nyquist band.
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Apart from quantization noise, the sampling noise and non-
linearity of the DAC, the comparator thermal noise also con-
tributes to the total noise spectrum. The low power dynamic
pre-amplifier and latch-based comparator in [17] as shown in
Fig. 10(a) suffers from time-varying and limited gain (8–12X;
Fig. 11-left). The CM voltage of the decision point (Node 1, 2
in Fig. 10(a)) is difficult to set during comparison. Namely, for
the latch it should be low to guarantee high gain, but for the
pre-amplifier it should be high enough to keep the input devices
in saturation to reduce IRN. Fig. 10(b) shows the proposed high
gain comparator. By inserting cascode transistors MN4/MN5
and cross-coupled gain boosting transistors MN6/MN7, the gain
of the dynamic preamp is increased to 52X and less time depen-
dent (Fig. 11-right). A high gain reduces the noise contribution
of capacitors at node 1, 2 and the latch. As a result, the IRN of
the comparator is reduced (2–3X) compared to [17] for the same
power consumption.
In addition, the speed of the SAR ADC is improved by a
modified latch as shown in Fig. 10(b). A complementary driven
push-pull topology increases the gain and the latching speed.
Compared to the conventional dynamic comparator structure,
the proposed preamplifier and the latch reduces the comparison
time of one cycle from ∼0.4 nS to ∼0.2 nS in simulation, which
is beneficial to allow a maximum sampling rate of 1 MHz. In
typical operation condition, the SAR-ADC consumes 0.9 μW
for an ENOB of 12.8b in a BW of 0.5-to-150 Hz at a sample
frequency of 32 kS/s (OSR = 64).
VI. IMPLEMENTATION RESULTS
The proposed single-chip SoC IC is implemented in a standard
55 nm CMOS process. The readout frontends for ECG, BioZ,
PPG, the power management circuitry, LED drivers, SRAMs the
Radio and USB interface are shown on the die-photo (Fig. 12).
The whole system occupies a total area of 18.66 mm2 .
A. Channel Measurement
The full ECG channel consumes 40.0 μW while achieving
917/807/733 nVrms noise in 0.5-to-150 Hz BW at gain of
40/80/160, respectively. A CMRR of 105 dB, PSRR of 100 dB,
an input impedance of >500 Mohm at 50 Hz are measured. The
IA itself consumes 19.2 μW and has an input referred noise of
600 nVrms in a BW of 0.5-to-150 Hz and a THD of < 0.2 %
for 30 mVpp input signal. The IA can reject up to 350 mV DC
electrode offset. Fig. 13 shows the on-body measurement with
dry electrodes when the RLD circuit is enabled and disabled,
respectively. It can be observed that the RLD circuit reduces the
common mode component coupled to the signal.
The PPG channel consumes 179 μW/121 μW power while
achieving 151 pArms/28 pArms input noise in 0.1 to 20 Hz
BW together with DR of 90 dB/94 dB in high power mode
and low power mode, respectively. With the DC cancellation
IDAC enabled, the dynamic range can be increased up to 111 dB.
The performance of the PPG channel is summarized in Table II,
where the PRF is 4 kHz, 32 samples are taken and averaged on
one LED pulse, the final data rate is 128 Hz and a FIR filter limit
the bandwidth to 40 Hz. The input referred noise spectrum is
SONG et al.: 769 µW BATTERY-POWERED SINGLE-CHIP SoC WITH BLE 1513

Fig. 10. The proposed digital assisted SAR-ADC with a gain boosting dynamic comparator (b) compared with a conventional comparator (a).

Fig. 11. the operation of the proposed comparator compared to a conventional

comparator.

Fig. 13. Measurement of the ECG channel.

TABLE II
THE ACHIEVED NOISE AND DR PERFORMANCE OF THE PPG CHANNEL

Fig. 12. Die photo of the SoC. The size is 4320 µm × 4320 µm.

shown in Fig. 14(a). On body measurement with a finger sensor

with red and IR PPG and on-chip calculated SpO2 is given in
Fig. 14(b). In a heartbeat detection mode, a 26 μS wide (10 μS
transient + 16 μS for 8 samples per pulse) 12 mA peak current

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1514 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 13, NO. 6, DECEMBER 2019
Fig. 14. Measurement of the PPG channel.
Fig. 15. Power consumption distribution health-patch and SoC.
is used with a PRF of 256 Hz, resulting in a 205 μW total LED
power and a 326 μW total power including the readout frontend.
B. System Level Measurement
The PCB of the health-patch system as shown in Fig. 1(a) has
been used to perform system level measurements. The system
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Fig. 16. The Interface showing PPG, ECG. BioZ and ACC waveforms together
with derived HR and SpO2.
TABLE III
THE POWER BREAKDOWN
operates on two ZincAir coin cells. Next to ECG, BIOZ and PPG
sensors also an accelerometer sensor is connected. The data can
be stored in an external flash.
The application executed on the chip performs concurrent
and synchronous data collection of ECG (1 channel), BIOZ,
PPG and accelerometer. For PPG two LEDs, red and infrared
are used, resulting into two streams of data. The data is on-chip
processed by the M4f processor supported by the accelerators.
Four algorithms are executed in parallel: (1) Calculation of the
heart-rate from ECG data; (2) Calculation of the respiration
rate from BIOZ data; (3) Calculation of SpO2 level from the
PPG data streams and (4) Calculation of the heart-rate from
PPG, with motion artefact reduction using the accelerometer
data [18], [19]. The algorithms make use of the accelerators:
FFT is used by SpO2. Sample-rate-conversion is performed on
SONG et al.: 769 µW BATTERY-POWERED SINGLE-CHIP SoC WITH BLE
TABLE IV
BENCHMARK SOC
TABLE V
BENCHMARK SAR-ADC
the accelerometer data to make sure that it matches with the
sample-rate of the PPG data. Matrix operations are performed
in all algorithms using the MP. The calculated numbers are sent
via BLE to a PC. To reduce the power consumption the PPG
readout (and depending calculation of SpO2 and heart rate) are
duty cycled (10% active time). Similarly, the data is transmitted
over the BLE link in burst mode and the radio is put into sleep
mode in between bursts. On average the BLE radio is active 5%
of the time.
To visualize the waveforms there is a wired connection be-
tween the sensor system and a PC. Fig. 16 shows the waveforms
of the PPG, ECG, BioZ and Accelerometer (ACC). Table III
shows the power consumption of the health-patch system and the
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1515
TABLE VI
BENCHMARK OF THE PPG CHANNEL
SoC. The total average power consumption of the SoC is 769 μW
excluding the LDOs. The digital core is operating at 0.8 V, the
remainder of the SoC operates at 1.2 V. The full health-patch
system consumes on average ∼2 mW from the battery of which
∼1 mW is consumed by the SoC and the remainder by the LEDs,
accelerometers and other supporting electronics. The system
uses two 630 mAh ZincAir batteries, which results in more than
3 weeks of operation time. power consumption of the BLE radio
is due to the duty cycling. The BLE consumes up to 7 mW when
active.
VII. BENCHMARKING AND CONCLUSION
In conclusion, an all-in-one, low-power SoC is proposed for
low-cost miniaturized wearable bio-medical applications. The
SoC integrates readouts for ECG, BIOZ, and PPG, a powerful
processor (M4f) and accelerators, and standard interfacing tech-
nology such as USB and Bluetooth (BLE 4.2). The high level of
integration allows low-cost applications such as demonstrated
by means of the disposable health-patch but does not sacrifice
on signal quality. The improved comparator in the SAR-ADC
for all readouts, and specifically the differential PPG readout,
assures medical standard signal quality for ECG, BIOZ and PPG
(Benchmarking Tables IV for the SoC, V for SAR-ADC and VI
for PPG). An average power consumption of 769 μW for the
SoC is achieved for a typical health-patch application which
continuously monitors heart-rate, respiration-rate, activity, and
SpO2 level for up to 3 weeks on 2 ZincAir batteries.
REFERENCES
[1] M. Konijnenburg et al., “A Multi(bio)sensor acquisition system with
integrated processor, power management, 8x8 led drivers, and simulta-
neously synchronized ECG, BIO-Z, GSR, and two PPG readouts,” IEEE
J. Solid-State Circuits, vol. 51, no. 11, pp. 2584–2595, Nov. 2016.
[2] P. Schönle, F. Glaser, T. Burger, G. Rovere, L. Benini, and Q. Huang,
“A Multi-Sensor and parallel processing SoC for miniaturized med-
ical instrumentation,” IEEE J. Solid-State Circuits, vol. 53, no. 7,
pp. 2076–2087, Jul. 2018.
1516 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 13, NO. 6, DECEMBER 2019

[3] H. Ha et al., “22.5 A Bio-Impedance readout IC with Digital-Assisted
baseline cancellation for 2-Electrode measurement,” in Proc. IEEE Int.
Solid- State Circuits Conf., San Francisco, CA, USA, 2019, pp. 368–370.
[4] M. Konijnenburg et al., “22.1 A 769 µW Battery-Powered Single-Chip
SoC with BLE for Multi-Modal vital sign health patches,” in Proc.
IEEE Int. Solid- State Circuits Conf., San Francisco, CA, USA, 2019,
pp. 360–362.
[5] A. Rani and S. Kumar, “A survey of security in wireless sensor networks,”
in Proc. 3rd Int. Conf. Comput. Intell. Commun. Technol., Ghaziabad,
India, 2017, pp. 1–5.
[6] J. Grover and S. Sharma, “Security issues in wireless sensor network —
a review,” in Proc. 5th Int. Conf. Reliabil., Infocom Technologies Optim.
(Trends Future Directions), Noida, India, 2016, pp. 397–404.
[7] Silex Insight, Mont-Saint-Guibert, Belgium. 2017. [Online]. Available:
https://www.silexinsight.com/product_categories/security
[8] Intrinsic ID, Eindhoven, The Netherlands. 2017. [Online]. Available: https:
//www.intrinsic-id.com/resources/white_papers
[9] N. Van Helleputte et al., “A 345 µW Multi-Sensor biomedical SoC with
Bio-Impedance, 3-Channel ECG, motion artifact reduction, and integrated
DSP,” IEEE J. Solid-State Circuits, vol. 50, no. 1, pp. 230–244, Jan. 2015.
[10] M. Zamani, Y. Rezaeiyan, O. Shoaei, and W. A. Serdijn, “A 1.55 µW
Bio-Impedance measurement system for implantable cardiac pacemakers
in 0.18 µm CMOS,” in IEEE Trans. Biomed. Circuits Syst., vol. 12, no. 1,
pp. 211–221, Feb. 2018.
[11] E. Winokur, T. O’Dwyer, and C. G. Sodini, “A Low-Power, dual wave-
length photoplethysmogram (PPG) SoC with static and Time-Varying
interferer removal,” IEEE Trans. Biomed. Circuits Syst., vol. 9, no. 4,
pp. 581–589, Aug. 2015.
[12] J. Xu et al., “A 665 µW silicon Photomultiplier-Based NIRS/EEG/EIT
monitoring ASIC for wearable functional brain imaging,” IEEE Trans.
Biomed. Circuits Syst., vol. 12, no. 6, pp. 1267–1277, Dec. 2018.
[13] A. Sharma et al., “A Sub-60-µA multimodal smart biosensing SoC with
>80-dB SNR, 35-µA photoplethysmography signal chain,” IEEE J. Solid-
State Circuits, vol. 52, no. 4, pp. 1021–1033, Apr. 2017.
[14] B. Lin, M. Atef, and G. Wang, “14.85 µW Analog Front-End for Pho-
toplethysmography Acquisition with 142-dBO Gain and 64.2-pArms
Noise,” Sensors, vol. 19, 2019, Art. no. 512.
[15] Carminati and M. Tartagni, “Noise limits of CMOS current interfaces for
biosensors: A review,” IEEE Trans. Biomed. Circuits Syst., vol. 8, no. 2,
pp. 278–292, Apr. 2014.
[16] H. Xin, M. Andraud, P. Baltus, E. Cantatore, and P. Harpe, “A 0.1-
nW-1-µW energy-efficient all-dynamic versatile capacitance-to-digital
converter,” IEEE J. Solid-State Circuits, vol. 54, no. 7, pp. 1841–1851,
Jul. 2019.
[17] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. A. M.
Klumperink, and B. Nauta, “A 10-bit charge-redistribution ADC con-
suming 1.9 W at 1 MS/s,” IEEE J. Solid-State Circuits, vol. 45, no. 5,
pp. 1007–1015, May 2010.
[18] D. Biswas, N. Simões-Capela, C. Van Hoof, and N. Van Helleputte, “Heart
rate estimation from Wrist-Worn Photoplethysmography: A Review,”
IEEE Sensors J., vol. 19, no. 16, pp. 6560–6570, Aug. 2019.
[19] Y. Zhang et al., “Motion artifact reduction for Wrist-Worn photoplethys-
mograph sensors based on different wavelengths,” Sensors, vol. 19, 2019,
Art. no. 673.
[20] Q. Lin et al., “A 196 µW, Reconfigurable Light-to-Digital converter with
119 dB dynamic range, for wearable PPG/NIRS sensors,” in Proc. Symp.
VLSI Circuits, Kyoto, Japan, 2019, pp. C58–C59.
[21] S. Fateh, P. Schönle, L. Bettini, G. Rovere, L. Benini, and Q. Huang,
“A reconfigurable 5-to-14 bit SAR ADC for battery-powered medical
instrumentation,” IEEE Trans. Circuits Syst. I, Regular Papers, vol. 62,
no. 11, pp. 2685–2694, Nov. 2015.
Mario Konijnenburg (M’08) received the M.S. de-
gree in electrical engineering in 1993 from Delft Uni-
versity of Technology, Delft, The Netherlands, where
he received the Ph.D. degree in automatic test pattern
generation for sequential circuits, in 1999. He joined
Philips Research/NXP Semiconductors and worked
on methodologies to improve design testability. He
is currently permanent member of technical staff, be-
ing system architect at imec-Netherlands, Eindhoven,
The Netherlands where he works on development of
ultralow power designs for biomedical applications.
Roland van Wegberg received the M.Sc. degree in
electrical engineering from the Eindhoven University
of Technology, Eindhoven, The Netherlands, in 1997.
In 1998, respectively. He joined Philips Semiconduc-
tors/NXP as an IC Design Engineer. Since 2013, he
has been a Mixed-Signal IC Design Engineer with
the Analog Design Group, imec-Netherlands, where
he is involved in the design of ultralow power IA,
PGA, SAR-ADC, and Sigma-Delta ADCs for the
amplification and digitization of biomedical signals
for wearables and implantables.
Jiawei Xu (M’15–SM’19) received the M.Sc. and
Ph.D. degrees in electrical engineering from the Delft
University of Technology, Delft, The Netherlands,
in 2006 and 2016, respectively. From 2006 to 2018,
he was a Senior Researcher with imec-Netherlands,
Eindhoven, The Netherlands, where he developed
several ICs for medical-grade wearable devices, in-
cluding EEG, ECG, BioZ and fNIRS. In 2018, he
joined the State Key Laboratory of ASIC & System
at Fudan University, Shanghai, China, as a Professor
and Principal Investigator, leading the R&D activities
of biomedical and sensor interface ASIC. He has authored and coauthored
more than 30 peer-reviewed publications, including a book on noninvasive brain
monitoring ICs. He was a recipient of the IEEE SSCS Predoctoral Achievement
Award (2014) and the Scientific Excellence Award of imec (2014).
Hyunsoo Ha (M’19) received the B.S. and Ph.D.
degrees in electrical engineering from the Pohang
University of Science and Technology, Pohang, South
Korea, in 2008 and 2014, respectively. He was a Vis-
iting Scholar with the University of Michigan, Ann
Arbor, MI, USA, from 2012 to 2013. He joined imec-
Netherlands, Eindhoven, The Netherlands in 2014 as
a Researcher for analog circuit design. His research
interests include circuit design of analog front-end for
bio-medical applications and sensor interfaces.

Shuang Song (S’12–M’16) received the B.S. and

M.S. degree in electrical engineering from Zhejiang
University, Hangzhou, China, in 2006 and 2008, re-
Wim Sijbers received the M.S. degree in electrical
spectively, and the P.D.Eng. and Ph.D. degrees from
engineering from KU Leuven University, Leuven,
Eindhoven University of Technology, Eindhoven,
The Netherlands, in 2010 and 2015, respectively. In Belgium, in 2011. Since then, he has been working
at imec, Leuven, Belgium as an analog design engi-
2008, he moved to Eindhoven, The Netherlands. In
neer. Since 2017, he is part of the connected health
March 2015, he moved to Leuven, Belgium, where he
solutions group, working on ultralow power sensor
is currently a Senior Researcher in biomedical inte-
interfaces for biomedical applications.
grated circuit design with imec. His research interests
include low-power analog and mixed signal circuits
and systems for biomedical applications, readout circuits for optical sensors,
interface circuits for MEMS device, and low-power power management circuits.

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SONG et al.: 769 µW BATTERY-POWERED SINGLE-CHIP SoC WITH BLE
Stefano Stanzione received the M.S. and the Ph.D.
degrees from the University of Pisa, Pisa, Italy, in
2006 and 2010, respectively. His Ph.D. work fo-
cused on the analog building blocks of autonomous
UHF RFID tags. He joined the Holst Centre/imec,
Eindhoven, The Netherlands, in 2010, where he is
currently an Analog Design Engineer. His current
research interests include ultralow-power circuits for
energy harvesting and battery management. He has
been a member of the Analog Technical Program
Subcommittee of ISSCC between 2014 and 2018.
Dwaipayan Biswas received the M.Sc. degree in
system on chip and the Ph.D. degree in electrical
engineering from the University of Southampton
(UoS), Southampton, U.K., in 2011 and 2015, respec-
tively. He was a Postdoctoral Research Fellow with
UoS, from 2015 to 2016. In 2016, he joined imec,
Leuven, Belgium, where he has been a Researcher
on digital IC design for biomedical applications. He
has authored 11 journals, more than 20 conference
publications, and three book chapters. His research
interests include low-power VLSI design, biomedical
signal processing, machine learning, brain computer interface, and computer
architecture.
Arjan Breeschoten received the B.Sc. degree in com-
puter technology from HTS Windesheim, Zwolle,
The Netherlands, in 1994. Until 2008, he worked
within the semiconductor industry, and involved in
research and development for ASICs in the Security,
WiFi, WiMax, and DECT application domains. In
2009, he joined the imec-Netherlands, Eindhoven,
The Netherlands, where he focused on system inte-
gration and project management for ultralow-power
communications solutions.
Peter Vis received the B. Eng. degree in electri-
cal engineering from the AVANS University of Ap-
plied Sciences, ‘s-Hertogenbosch, The Netherlands,
in 2005. He joined NXP semiconductors in 2008
and later Synopsys Inc. where he worked on the
development of interface IP. Since 2018, he joined
imec-Netherlands, Eindhoven, The Netherlands, as a
Digital R&D engineer. His research interests include
the design of low-power analog mixed signal designs
for biomedical and RF applications.
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1517
Chris van Liempd received the M.S. degree in elec-
trical engineering from Technical University Eind-
hoven, Eindhoven, The Netherlands, in 1978. Since
2009, He has been a Senior Researcher with Holst
Centre. He joined Philips Medical systems in 1978
where he worked on analog frontend systems respec-
tively for Patient Monitoring, Computed Tomogra-
phy, Ultrasound and Magnetic Resonance. In 1998,
he became part of the Philips Optical Storage group
and played a major role as system architect in several
projects in this group. He has more than 30 years’
experience in analog electronics engineering. His current research interests
include ultralow power and high efficiency power management circuits for
mobile solutions and energy harvesting. He holds 9 patents.
Chris Van Hoof (M’91) received the Ph.D. degree in
electrical engineering from the University of Leuven,
Leuven, Belgium, in 1992. He is the Senior Direc-
tor of Connected Health Solution at imec, Leuven,
Belgium and also imec Fellow. He has a track record
of more than 25 years of initiating, executing, and
leading national and international contract R&D with
imec. His work resulted in five startups (four in the
healthcare domain). He has authored or coauthored
more than 700 papers in journals and conference pro-
ceedings and given more than 100 invited talks. His
research interests include highly diverse technical fields (sensors and imagers,
MEMS and autonomous microsystems, wireless sensors, body-area networks,
patient monitoring solutions, digital phenotyping). He is also a Full Professor
with the University of Leuven, Belgium.
Nick Van Helleputte (M’07) received the M.S.
degree in electrical engineering in 2004 from the
Katholieke Universiteit Leuven, Leuven, Belgium,
where he received the Ph.D. degree in 2009 (MI-
CAS research group). His Ph.D. research focused on
low-power ultrawideband analog front-end receivers
for ranging applications. He joined imec in 2009 as
an Analog R&D Design Engineer. He is currently
team leader of the biomedical circuits and systems
team. He has authored or coauthored more than 50
papers in journals and conference proceedings. His
research interest includes ultralow-power circuits for biomedical applications.
He has been involved in analog and mixed-signal ASIC design for wearable
and implantable healthcare applications. He is SSCS member and served on the
technical program committee of VLSI circuits symposium and ISSCC.