3/16/22, 11:21 PM Designing Bandgap Reference Sources with Cadence Virtuoso IC617 - Programmer Sought

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Designing Bandgap Reference with Cadence Virtuoso IC

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foreword
This article is my own study notes, which belong to the advanced part of the Cadence Virtuoso series. The
software version used is Cadence Virtuoso IC617. For other articles, please click above to see the content of
the Cadence Virtuoso column I produced.

This article investigates the use of a bandgap reference to generate a temperature-independent voltage
reference for use in the circuits studied later.

Band gap reference

In practical circuit applications, a temperature-independent reference is essential. How to generate a
temperature-independent quantity?

Theoretical principles
In common electronic components, a single component has either a positive temperature coefficient or a
negative temperature coefficient, so a single electronic component cannot produce a constant output, and we
need to make some changes.

If a positive temperature coefficient value is added to a negative temperature coefficient value while giving them
a specific weight, then we get a zero temperature coefficient value.

circuit principle
As early as the 1960s, some researchers found that the temperature coefficient of bipolar transistors is better,
showing a negative temperature coefficient. At the same time, if different currents are applied to the two bipolar
transistors, their voltage difference is proportional to the absolute temperature, showing a positive temperature

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coefficient. Using these two, an output with zero temperature coefficient can be produced.

The operation between the two can be realized by an operational amplifier, which has better performance, and
at the same time, a current mirror is used to realize the current replication.

A parameter that measures the temperature performance of a circuit is temperature drift, in ppm/°C, on the
order of 10e-6, obtained by the following formula. Among them, ppm less than 20 means the circuit is available,
and ppm less than 10 means the circuit performance is better.

Vm a x − Vm i n
× 1 06 pp m / ° C
​ ​

Va v g ( Tm a x − Tm i n )
​

​ ​ ​

designing process
Select SMIC 0.18um process. At the beginning, the number of PNP transistors must be selected. For the
convenience of layout design, we generally design the value of Q1:Q2:Q3 to be 1:7:1, which is to adjust the
Multiplier value corresponding to the transistor. In this way, we can get a 3*3 PNP triode array layout, in which
Q1 will be placed in the middle.

Secondly, combined with the power consumption requirements, determine the current of each branch. Here I
choose the current of each branch to be 10uA. A piece of chicken… focus on 5 2 56 Column Directory

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op amp design
At the same time, the choice of op amp is also important. High gain can improve the accuracy of the reference
source and power supply voltage suppression performance, high bandwidth can improve the range of the
reference source operating frequency, and high-speed op amps can quickly handle crosstalk to stabilize the
output.

But we know that the design of op amps is actually a compromise process. The cost of improving performance
is the increase of chip area and power consumption. We do not want to design a reference source with better
performance but power consumption. up to a few milliwatts.

Among the several op amp indicators mentioned above, for the bandgap reference source, the most important
thing is the gain of the op amp, we only need to increase the area of ​some input transistors (mainly increase the
gate length L), without the need for Add too much power, and you can get a high gain op amp, which is still
more cost-effective.

A folded cascode op amp is used, where gm/id=18 for the input tube and gm/id=6 for other transistors. The gate
length of the current mirror is L=4um. The designed Av is about 58dB, and under the load of 4.8pF,
GBW=3MHz. Others will not repeat the design process.

Determining P-MOS Dimensions

There are three P-MOSs in the schematic diagram , and the currents of their branches are designed to be the
same 10uA, so their sizes can be designed to be equal. Through the gm/id design method, while reducing noise
interference, take gm/id=6 to suppress the channel length modulation effect, take L=2um, and directly obtain W
from the corresponding id/W value. The value result is as follows.

P-MOS

W 5.57u

L 2u

Multiplier 1

Determine R1

R1 mainly determines the current of the branch, our goal is to design the current of the branch to be 10uA.
Select Parametric Sweep, sweep R1 in the range of 1K to 100K, and take 10 points.

Get the relationship between the output current and the resistance of R1, here we determine that the range of
R1 is around 4.6K.

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Modify the scanning range from 3K to 6K, and approach it successively.

The range is probably around 5K. Repeat the above steps, and finally get, when the branch current is 10uA,
R1=5.056K.

Determine R2
Resistor R2 mainly determines the temperature coefficient of the circuit, because at this time, the output voltage
will definitely not change with the power supply voltage, so it will no longer be scanned. If you are interested,
you can verify it yourself.

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Set the scan to DC scan and the scan value to be temperature.

As above, the sweep parameter is R2.

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Get the approximate range of R2.

Reduce the scanning range and approach successively.

Get R2 to be about 38.5K. The final result is R1=38.7K.

Simulation results
Write the values ​obtained earlier into the circuit parameters to simulate the circuit. Simulating the power supply
characteristics, in the range of 2V to 4.5V, it can be seen that the maximum and minimum deviation rate is about
0.67%. This circuit has a disadvantage, that is, in the second half of the curve, when VDD is large, the output

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curve has a downward trend.

Simulate temperature characteristics. The average voltage Vavg is about 1.1595V, the temperature drift is
2.6ppm, and the performance is good. Note that after drawing the post-simulation of the layout, this value will
become worse, so the matching of the layout is also very important.

Let's talk about how to check the power supply rejection ratio. First, add a 1V AC signal at the DC voltage
source that controls VDD.

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After adding the AC scan, click Simulate, and after the results come out, select Result output.

Select as follows. Then click the connection line of the reference voltage output with the mouse.

The obtained power supply rejection ratio is close to 60dB, and its performance is roughly the gain of the
designed op amp. Of course, this indicator is not good enough, generally 100dB and above are considered

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excellent.

start circuit
As with the current reference mentioned in the previous article, there is a degeneracy point at VDD power-up.
So a startup circuit needs to be introduced.

This part will be added later. If it is used for the principle of the simulation verification book, this part is not
necessary. If it is to be taped, it must be added.

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foreword

Band gap reference

Theoretical principles

circuit principle

designing process

op amp design

Determining P-MOS Dimensions

Determine R1

Determine R2

Simulation results

start circuit

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