S912 Datasheet Revision 0.

Bits(s) R/W Default Description

6 RW 0 ctrl_axi_rd_urgent:
0=DDR read request not urgent;
1=DDR read request urgent.
5:4 RW 0 ctrl_ahb_wr_burst_size:
0=AHB write request burst size 4x128-b;
1=AHB write request burst size 8x128-b;
2=AHB write request burst size 12x128-b;
3=AHB write request burst size 16x128-b.
3:2 RW 0 ctrl_ahb_rd_burst_size:
0=AHB read request burst size 4x128-b;
1=AHB read request burst size 8x128-b;
2=AHB read request burst size 12x128-b;
3=AHB read request burst size 16x128-b.
1 RW 0 ctrl_sw_reset:
0=No reset;
1=Reset RDMA logics except its own register interface.
0 RW 0 ctrl_free_clk_enable:
0=Enable clock gating;
1=No clock gating, enable free clock.

RDMA_STATUS
Bits(s) R/W Default Description
31:24 R 0 rdma_done_flag: interrupt status. 8-bit,
bit, one bit for each RDMA source.
[0] Manual src 0 RDMA done intr status.
[1] Auto src 1 RDMA done intr status.
[2] Auto src 2 RDMA done intr status.
[3] Auto src 3 RDMA done intr status.
[4] Auto src 4 RDMA done intr status.
tatus.
[5] Auto src 5 RDMA done intr status.
[6] Auto src 6 RDMA done intr status.
[7] Auto src 7 RDMA done intr status.
23 R 0 Reserved.
22 R 0 err_axi_wrfifo_undflow
21 R 0 err_axi_wrfifo_ovrflow
20 R 0 err_axi_rdfifo_ovrflow
19:18 R 0 axi_w_st:
AXI write data status:
0=Idle;
1=Wait Data;
2=Req;
3=Wait BRSP.
17:16 R 0 axi_aw_st:
AXI write address status:
0=Idle;
1=Req;
2=Wait RDY.
15:14 R 0 axi_ar_st:
AXI read address status:
0=Idle;
1=Wait FIFO;
2=Req;
3=Wait Done.
13:11 R 0 rdma_id_curr
10:8 R 0 rdma_id_pipe

347/554 AMLOGIC, Inc. Proprietary

 S912 Datasheet Revision 0.1

7:0 R 0 req_latch:
Requests that are yet to be serviced. E.g.:
00000000=No request;
00000001=Req 0 waiting;
00001100=Req 2 and 3 waiting;
10000000=Req7 waiting.

RDMA_STATUS2
Bits(s) R/W Default Description
31:30 R 0 Reserved.
29:24 R 0 axi_wrfifo_cnt. FIFO count for buffering VCBus read data to sent to AXI.
23:22 R 0 Reserved.
21:16 R 0 axi_rdfifo_cnt. FIFO count for buffering data read from AXI.
15:14 R 0 Reserved.
13:8 R 32 axi_wrfifo_room. FIFO room for buffering VCBus read data to sent to AXI.
7:6 R 0 Reserved.
5:0 R 32 axi_rdfifo_room. FIFO room for buffering data read from AXI.

RDMA_STATUS3
Bits(s) R/W Default Description
31:24 R 0 Reserved.
23:8 R 0 axi_b_pending
7:0 R 0 axi_aw_pending

348/554 AMLOGIC, Inc. Proprietary

 S912 Datasheet Revision 0.1

27.4 HDMI
S912 has Built-in HDMI 2.0 transmitter including both controller and PHY with CEC and HDCP 2,2, 4Kx2K@60 max resolution
output.
This section -level registers only. HDMITX module instantiates two IPs HDMI TX Controller and
HDCP2.2 Controller. These two IPs internal registers are specified by the correspond

Register Description
HDMITX Top-Level and HDMI TX Contoller IP Register Access
Accessing HDMITX Top-Level and TX Controller IP registers is by indirectly accessing two memory addresses, one of the
addresses is mapped to register address, the other one is mapped to read/write data. There is also an extra address for access
control. See Table below.

Table IV.29.4 HDMITX Top-Level

Level and TX Controller register access ports
Absolute Address Mnemonic Bit(s) Default Description
Address
0xda83a000 HDMITX_ADDR_PORT [31:0] 0 Map to register address.
0xda83a004 HDMITX_DATA_PORT [31:0] 0 Map to register read/write data.
0xda83a008 HDMITX_CTRL_PORT [31:0] 0x3ff Register access control. See Table1.1.

Table IV.29.5 HDMITX Control Port for register access

Bit(s) R/W Default Description
31:16 R 0 Reserved.
15 RW 0 err_en:
0=No limit on PREADY wait time;
1=Enable APB access PREADY watchdog timer.
14 W 0 stack_err_clr.
1=Clear stack_err.
Always read back 0.
13 R 0 stack_err.
1=Stack over/underflow.
12 RW 0 stack_enable.
Control whether to stack the indirect reg access sequence, in case register access is interrupted by an interrupt
that also indirectly access HDMITX.
0=Old behaviour that does not support interruption;
1=Enable stack function.
11:0 RW 0x3ff max_err:
If err_en=1, maximum number of APB clock cycle wait time for PREADY assertion, before it asserts APB access
error.

Table IV.29.6 HDMITX sub-module base address

Base Address Module Name Description
0x00 dev_offset_top Device address offset for AmLogic top-level wrapper that instantiates the IPs.
0x10 dev_offset_dwc Device address offset for HDMI TX Controller IP module.

To write to a Top-level register:

*((volatile uint32_t *) (HDMITX_ADDR_PORT+dev_offset_top)) = addr;
*((volatile uint32_t *) (HDMITX_DATA_PORT+dev_offset_top)) = data;

To write to a TX controller IP register:

349/554 AMLOGIC, Inc. Proprietary

S912 Datasheet Revision 0.1

*((volatile uint32_t *) (HDMITX_ADDR_PORT+dev_offset_dwc)) = addr;

*((volatile uint32_t *) (HDMITX_DATA_PORT+dev_offset_dwc)) = data;

To read from a Top-level register:

*((volatile uint32_t *) (HDMITX_ADDR_PORT+dev_offset_top)) = addr;
data = *((volatile uint32_t *) (HDMITX_DATA_PORT+dev_offset_top));

To read from a TX controller IP register:

*((volatile uint32_t *) (HDMITX_ADDR_PORT+dev_offset_dwc)) = addr;
data = *((volatile uint32_t *) (HDMITX_DATA_PORT+dev_offset_dwc));

HDCP2.2 IP Register Access

Table IV.29.7 HDCP2.2 IP register base address
Absolute Address Mnemonic Description
Address
0xd0044000 ELP_ESM_HPI_REG_BASE Address base to HDCP2.2 IP register access.

To write to an HDCP2.2 IP register:

*((volatile uint32_t *) (ELP_ESM_HPI_REG_BASE+addr)) = data;

To read from an HDCP2.2 IP register:

data = *((volatile uint32_t *) (ELP_ESM_HPI_REG_BASE+addr));

Table IV.29.8 HDMITX Top-Level

Top Level Registers
Addr Name RW Function
0x000 HDMITX_TOP_SW_RESET RW Software reset sub-modules.
0x001 HDMITX_TOP_CLK_CNTL RW Clock gating and inversion.
0x002 HDMITX_TOP_HPD_FILTER RW HPD input glitch filter.
0x003 HDMITX_TOP_INTR_MASKN RW Interrupt mask.
0x004 HDMITX_TOP_INTR_STAT RW Interrupt status.
0x005 HDMITX_TOP_INTR_STAT_CLR W Interrupt clear.
0x006 HDMITX_TOP_BIST_CNTL RW Build-In Self Test(BIST) control.
0x007 HDMITX_TOP_SHIFT_PTTN_012 RW Shift pattern for BIST.
0x008 HDMITX_TOP_SHIFT_PTTN_345 RW Shift pattern for BIST.
0x009 HDMITX_TOP_SHIFT_PTTN_67 RW Shift pattern for BIST.
0x00A HDMITX_TOP_TMDS_CLK_PTTN_01 RW TMDS clock pattern for generating /10 or /40 rate clock.
0x00B HDMITX_TOP_TMDS_CLK_PTTN_23 RW TMDS clock pattern for generating /10 or /40 rate clock.
0x00C HDMITX_TOP_TMDS_CLK_PTTN_CNTL RW TMDS clock pattern for generating /10 or /40 rate clock.
0x00D HDMITX_TOP_REVOCMEM_STAT RW Revocmem status
0x00E HDMITX_TOP_STAT0 RW Status.
0x010 HDMITX_TOP_SKP_CNTL_STAT RW SKP interface control for HDCP2.2.
0x011 HDMITX_TOP_NONCE_0 W Nonce[31:0] for HDCP2.2.
0x012 HDMITX_TOP_NONCE_1 W Nonce[63:32] for HDCP2.2.
0x013 HDMITX_TOP_NONCE_2 W Nonce[95:64] for HDCP2.2.
0x014 HDMITX_TOP_NONCE_3 W Nonce[127:96] for HDCP2.2.
0x015 HDMITX_TOP_PKF_0 W PKF[31:0] for HDCP2.2.
0x016 HDMITX_TOP_PKF_1 W PKF[63:32] for HDCP2.2.
0x017 HDMITX_TOP_PKF_2 W PKF[95:64] for HDCP2.2.
0x018 HDMITX_TOP_PKF_3 W PKF[127:96] for HDCP2.2.
0x019 HDMITX_TOP_DUK_0 W DUK [31:0] for HDCP2.2.
0x01A HDMITX_TOP_DUK_1 W DUK [63:32] for HDCP2.2.
0x01B HDMITX_TOP_DUK_2 W DUK [95:64] for HDCP2.2.
0x01C HDMITX_TOP_DUK_3 W DUK [127:96] for HDCP2.2.
0x01D HDMITX_TOP_INFILTER RW DDC and CEC input glitch filter control.

350/554 AMLOGIC, Inc. Proprietary