Proceedings of the 31st International Symposium on Power Semiconductor Devices & ICs

May 19-23, 2019, Shanghai, China

Integrated High-Speed Over-Current Protection

Circuit for GaN Power Transistors
Han Xu, Gaofei Tang, Jin Wei and Kevin J. Chen
Department of Electronic and Computer Engineering, The Hong Kong University of Science and Technology, Hong Kong
Phone: +852-23588530, Fax: +852-23581485, Email: hxuaw@connect.ust.hk eekjchen@ust.hk

Abstract—In this work, a new desaturation-based over-

current protection circuit is proposed and monolithically
integrated with GaN power HEMTs. Compared to traditional
desaturation techniques, this new design features separated
sensing branch and blanking time controller. Such a separation
allows immediate sensing of over-current (OC) event, while the
blanking time can be modified without considering the sensing
speed. To mimic real situations in power applications, the
circuit was systematically characterized under different
operating conditions. It can deliver an accurate OC threshold
voltage and fast response without affecting the switching
characteristics. These properties will contribute to a more
robust and reliable high-speed GaN power systems.

Keywords—Over-current protection, gate driver, integrated

circuits, GaN power HMETs

I. INTRODUCTION
GaN power HEMTs are promising to bring higher
efficiency and higher power density in power conversion
systems, owing to their superior characteristics including
high switching speed, low ON-state resistance and high
breakdown voltage [1-2]. To improve system-level
ruggedness, robust and high-speed over-current protection
of the power transistors is of great importance. Compared to
Si-based power devices, GaN power devices are much
smaller in size for the same RDS-ON and has to endure much
higher current density. Thus, they are more vulnerable to
over-current events. A report shows that GaN power
HEMTs may survive less than 1 µs at high saturation
current levels under its rated voltage [3]. Traditional discrete
implementations of over-current protection either degrade
system performance by adding extra inductance and
resistance, or compromise sensing accuracy and response
speed for GaN power device. Therefore, it is of great benefit
to develop monolithically integrated high-speed over-
current protection solutions with fast response time to
protect the GaN power transistors.
For Si-based power transistors, several OC protection
schemes have been developed [4-5]. The most
straightforward method is the resistor-based current sensing
that uses a current shunt. However, accurate current shunt
with low inductance is costly and will also generate
additional power loss. Another approach is based on current
sensing of a dummy transistor in close vicinity of the power
transistor, which may have limited sensing ratio and
accuracy [6]. To address these issues, desaturation
techniques have been developed using a sensing diode to
monitor the power transistor’s drain-to-source voltage VDS
This work is supported by Guangdong Science and Technology
Department under Grant 2017B010113002
Fig. 1 Schematic of the proposed over-current protection circuit. (1) the
sensing branch; (2) blanking controller; (3) driving controller. All
components are integrated except the load.
[4], [7]. This OC protection scheme has the benefits of
simple configuration and low cost, and requires no extra
components in the power loop. However, it is challenging to
directly implement this scheme in high-speed GaN power
switches due to the relatively long delay time required to
prevent the false judgment of a large OFF-state VDS.
In this work, a high-speed over-current protection circuit
was realized on an all-GaN platform, on which the
protection function block is monolithically integrated with
the gate driver and power HEMTs [8-10]. The circuit
improves the response speed by separating the sensing
branch and blanking time controller. Compared to
traditional discrete implementations of OC protection, this
integrated protection delivers a fast response time (40 ns)
and high sensitivity. The schematic and working principle
were illustrated in detail while its functionality was
systematically validated under different operating conditions.
II. CIRCUITS DESIGN AND OPERATING PRINCIPLE
The new desaturation-based over-current protection is
constructed in a simple but delicate method as shown in
Fig. 1. It consists of a sensing branch, a blanking time
controller and a driving signal controller. The current
information of the power switch is represented by its drain-
to-source voltage VDS, which is then further transferred to VS
by the sensing branch. When VDS is below a threshold value
(VOCT), VS = L (low); otherwise VS = H (high). As illustrated
in Fig. 2(a), if VDS is smaller than VOCT in the ON-state, the
OC protection circuit generates an enable signal (VOCE = L),
so a PWM signal of “H” could be fed to the power transistor

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 (a) Normal situation (b) OC situation (a) (b)
VBUS + Load
VDD Drain pad
5V SS+5V SS+VDD VDR
Source Pad
SS VGTAE
Gate Driver & Power
VDR Isolator OC Protection (c)
HEMT
SS M1

VBUS - Current shunt

Fig. 2 Illustration of basic waveforms in the over-current protection. (a)

Normal situation when ON-state current is below the critical point. (b) OC Fig. 3 (a) Schematic circuit of the double pulse tester. (b) Pad information
event with protected Gate signal. Area between dash lines is the designed of the integrated circuits. (c) Photo of the PCB with chip on it.
blanking time.

(M1) to maintain the ON-state. In the OFF-state, VS is (a)

blocked from the gate driver by the PWM signal of “L”, so
M1 can remain at the OFF-state. For M1 to switch from
OFF to ON, the switching transient is completed within the
blanking time, during which VS is still blocked from the
driver circuit, so the influence of the high OFF-state VDS is
obviated. For an OC event [Fig. 2(b)], VDS will be larger
than VOCT once M1 is turned on. VS (= H) is fed to the gate
driver after the blanking time. Then, VOCE = H, and M1 is
turned off irrespective of the PWM signal. The current
situation is checked every cycle by the pulsed gate signal
(VGATE) during the blanking time and an error information
can be reported by processing VS and driving signal VDR. (b)
In traditional desaturation techniques mentioned above,
current information is stored as a capacitor voltage while the
blanking time is also controlled by this capacitor. To turn on
the switch with high VDS, the charging speed must be
restricted by a large RC constant to ensure that the capacitor
voltage stays below the critical voltage and the protection is
not triggered. Therefore, when over-current situation (e.g. a
sudden increase of current) occurs, long response time is
expected due to the large RC constant. By separating the
sensing branch and blanking time controller, as described in
this new design, protection can be triggered immediately
during ON-state or after the designed blanking time.
III. EXPERIMENT VALIDATION Fig.4 Experiment validation on basic protection capability. (a) Driving
signal is fixed at high level. (b) Driving signal is a PWM signal.
To verify the functionality of the proposed protection,
the circuit was tested in different conditions according to will be shut down to zero, even though VDR is fixed at “H”
real application situations. Some circuits and chip [Fig. 4(a)] or fed with a PWM signal [Fig. 4(b)]. This is the
information were presented in Fig. 3. expected protection situation where VDS is an indication of
current. A threshold voltage (1V) can be obtained from this
A. Basic protection behavior experiment and VGATE will be regulated when VDS exceeds
As described in last section, this protection circuit works this threshold.
by preventing the driving signal from getting into the gate
driver and the final result is the regulated VGATE , as shown in B. Protection under switching operation
Fig. 2. To test the basic protection capability, the protection In real applications, over-current protection must work
logic and gate driver were integrated as special function properly under switching operations. To characterize this
blocks (without power switch). They were tested on a probe property, the new design was tested by a double-pulse test
station to validate its operating logic. circuits, which refers to previously reported scheme in [8].
VDD and GND were connected to DC power supply while The schematic circuit is presented in Fig. 3(a) and the
a variable voltage can be applied to mimic the drain-source designed IC was mounted on the printed circuit board with
voltage of the power switch. This voltage (VDS) will silver epoxy and bonding wires. By changing the load to an
significantly influence the output of the gate driver (VGATE), inductor or power resistor, different conditions in real power
as plotted in Fig. 4. When VDS sweeps to about 1V, VGATE applications can be realized.

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 (a)

(b)

Fig. 5 Resistive switching waveforms. (a) Low current levels and normal Fig. 6 Inductive switching waveforms (a) Lower voltage with protection at
situation (b) Higher current level with protection triggered. (c) Zoomed-in the onset of the turn-on transient. (b) High voltage with the protection in
turn-on transient for normal switching operation. (d) Zoomed-in turn-on the conduction period.
transient for over-current situation.

To address the situation where a sudden or unusual

increase of current happens (e.g. short circuits), resistive-
load switching was characterized. Different current levels
were achieved by changing the value of the load resistor.
The bus voltage is fixed at a low level (10V) in order to
observe the ON-state drain-source voltage (VDS-ON).
Switching waveforms under different current levels are
presented in Fig. 5. A significant increase of VDS-ON can be
observed as the current levels rises. When the VDS-ON
exceeds the threshold of 1V(VOCT), the gate voltage of M1
will be pulled to 0V irrespective of the driving signal.
Zoomed-in pictures of the turn-on transient are also
Fig. 7 Static voltage transfer curves of an inverter. The inset is a typical
presented in Fig. 5. Voltage spike induced by ringing may circuits schematic of direct-coupled FET logic.
exceed VOCT at the beginning of the turn-on transient, but its
influence could be blocked by the designed blanking time transient [Fig. 6(a)] or in the duration of the conduction
and a false judgment will be avoided during normal period [Fig. 6(b)].
switching. The blanking time of 30 ns is adopted in this Different triggered current levels in Fig. 6 can be
design and the total response time for protection is explained by the different bus voltages and the dynamic RON
controlled within 40 ns. in GaN HEMT [11], [12]. When the bus voltage is high, the
In some cases, over-current happens in a mild way. For device is stressed for a long time before the driving signal
instance, when a light load is changed to a heavier load in a was fed to the driver. Under such a circumstance, the RON
buck converter, the feedback system will change the duty will increase to 1.1~1.2 of its original value when bus
cycle of the power switch. If fault occurs in the output stage voltage is around 50 V. VDS is the product of RON and the
and the output voltages drops, the feedback loop will current ID and therefore, the current level for two conditions
continuously increase the duty cycle until the current are different.
reaches the limit. To validate the new design in such The middle state in Fig. 6(b) is induced by the inverter in
situations, the load was changed to an inductor. By varying the sensing branch. The inverter is a direct-coupled FET
the bus voltage, pulse numbers and pulse duration, the logic and its transfer curve is plotted in Fig. 7 [13].
protection can start to function at the onset of a turn-on Although two stages of inverter were used, VDS will have a

277

(a)
(b)
Fig. 8 Combined turn-on and turn-off transient. (a) Circuits with proposed
protection. (b) Circuit without protection.
small range of values, where VS and VGATE are in the middle
stage, as shown in Fig. 4. When the continuously increasing
VDS reaches the critical point, the power device will move to
semi-ON state and the sudden increase of VDS may cause
VGATE (in middle state) to swing through CGD. By deploying
more stages (e.g. four stages) of inverters with different
transfer curves in the sensing branch, VDS will be digitalized
completely and the middle state of VS and VGATE will be
eliminated.
C. Influence on switching performance
Another concern related to desaturation techniques is its
influence on switching performance. the sensing diode could
add additional capacitive load to the main switch, leading to
poor switching speed and higher switching loss. However, in
this new design, a low capacitive sensing diode (<1% in
width compared to M1) is adopted in the OC protection
circuit. Switching performance with and without the
protection were compared in Fig. 8. They were tested in the
same condition and the minor difference is introduced by
different PCB traces or chip-to-chip variation. Therefore, it is
concluded that implementation of the OC protection circuit
cast inappreciable influence on the switching speed of the
power transistor.
IV. CONCLUSIONS
In this work, a high-speed over-current protection circuit
was realized on an all-GaN platform. Traditional over-
current protection circuits either degrade system
performance by adding inductance and resistance to the
power loop, or compromise sensing accuracy and/or
278
response speed. The new design features a simple
architecture and a quick response, and has been
systematically validated at quasi-static conditions as well as
switching operations. Superior switching characteristics of
the GaN power transistor is maintained, indicating
negligible parasitic have been introduced by the
implementation of the over-current circuit. Thus, it provides
a simple and effective approach to prevent over-current
induced failure in GaN power integrated circuits.
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