Computer Architecture – test questions 1

1. What is a byte?
2. Why should we use binary, not decimal multiples to express the size of primary memory of
a computer?
3. Why the memory resources of contemporary computers have hierarchical structure?
4. Which two memory hierarchy layers are implemented using the same physical device? What
device is that?
5. How does the connection of instruction memory hierarchy and instruction processor differs
from the connection of data memory hierarchy and data processor in Skillicorn's taxonomy?
6. What is the difference between “loosely coupled” and “tightly coupled” multiprocessor in
Skillicorn's taxonomy?
7. Why the Harvard architecture makes it impossible to write the new program to memory
during normal operation of a computer?
8. What is the “von Neumann bottleneck”?
9. What is the weight of the most significant bit of a 16-bit integer number in two's
complement notation?
10. Determine binary pattern of an 8-bit word representing the given number in integer two's
complement, ones' complement and biased coding with the bias value of 127. (-120, -64,
-21, -10, -5, -1)
11. Which numeric codes have more than one representation of zero?
12. Why it isn't necessary to store an integer part of significand in IEEE754 floating/point
notation?
13. Determine binary patterns corresponding to a given number in IEE754 binary32 floating
point format (-256, -19, -10.125, -0.75, 0.625, 10, 15.5, 16.5)
14. How can one change the sign of a two's complement number using only single-argument
logic and arithmetic operations?
15. How can overflow be detected while adding unsigned/two's complement binary numbers?
16. What is a “size-alignment”?
17. Draw the layout of a given C structure and determine the value of sizeof operator,
assuming natural sizes of data types for a 32-bit processor with 8-bit bytes. (The answer may
be checked by writing a short C program displaying values of sizeof for a structure and
offsetof for each field).
18. Draw a layout of application's address space in one or more OSes based on values of
addresses of objects from various memory sections displayed by a C program.
19. Based on the map from the previous question estimate the possible limits of stack and heap
sizes imposed by a given operating system.
20. What does the PC register point to during instruction execution (after fetch is completed)?
21. Describe the order of actions while executing PUSH and POP instruction, assuming “full
descending” stack implementation.
Computer Architecture – test questions 2

22. Describe the order of actions while executing PUSH and POP instruction, assuming “empty
ascending” stack implementation.
23. Describe the operation of a CALL instruction.
24. What assembly instructions are used by the compiler to implement division of unsigned and
signed numbers by powers of 2 of unsigned and signed numbers?
25. Determine the decimal value of the result of performing on a given 8-bit two's complement
number (-66, -12, 130) (a) left logical, (b) right logical, (c) right arithmetic shift by one bit.
26. What is the difference between x86 SUB (subtract) and CMP (compare)?
27. What is the proper way of (a) setting the register to 0 (b) checking if register contains 0 in
x86 architecture assembly programming? Why?
28. Why is it more convenient to use the frame pointer rather than stack pointer for stack frame
addressing?
29. Draw the layout of a stack frame conforming to x86 C calling convention and determine the
addresses of arguments and possible addresses of local variables relative to the frame
pointer, given the function's declaration.
30. Which addressing modes are necessary for the implementation of a high-level language?
31. Determine the names of addressing modes used in a given x86 assembly instruction.
32. What information is recorded by parity flag?
33. Determine the x86 flag values after addition/subtraction/logic operation given the arguments
or result value and operation size.
34. What is the orthogonality of instructions versus addressing modes?
35. What is a typical usage of processor registers by HLL compilers in CISC & RISC
architectures?
36. Why the memory footprint of a program for a RISC processor is usually bigger than the
footprint of an equivalent program for a CISC processor?
37. Why is it impossible for a RISC processor to implement an instruction loading a 32-bit
immediate constant to a register? What other methods may be used to implement this
action?
38. Why the RISC instruction sets usually do not contain register to register copy instruction?
39. Explain why most RISC architectures do not have dedicated subroutine return instruction.
What instruction is used to return from a procedure in these architectures?
40. What is the difference in binary encoding and execution between a relative branch and
absolute jump instruction?
41. What characteristics of processor's programming model is required to implement the
processor as a single-cycle structure.
42. What is the role and operation of ALU during execution of load and store instructions in
single-cycle and simple pipelined processors?
Computer Architecture – test questions 3

43. Write an instruction sequence generating Read-After-Write hazard.

44. Why is it better to remove RAW hazard using bypasses rather than in other ways?
45. Explain why bypasses cannot resolve load-use penalty without delays.
46. What is the source of branch penalty problem in pipelined processors?
47. What is a “delayed branch”?
48. Why delayed branches are not used in superpipelined processors?
49. Outline two methods of a pipelined implementation of CISC processors?
50. What processor architectures use instruction transcoder and what is its purpose?
51. Describe the conditions under which a superscalar processor may simultaneously issue two
or more instructions to execution pipelines.
52. In what kind of architectures WAR and WAW hazards may be present?
53. Write an example of an instruction sequence generating WAR/WAW hazard.
54. Explain why the branch penalty and load-use penalty have so strong influence on efficiency
of contemporary superpipelined, superscalar processors.
55. What is an “instruction fusion”, implemented in contemporary x86 processors.
56. What is a cache line?
57. Which address bits are used for set selection/tag check in a cache of given capacity,
associativity and line size (ex. 24 KiB, 6, 32 B)?
58. Cache hit ratio depends on …
59. Write the formula for average access time of memory hierarchy containing single cache and
main memory.
60. What is the average access time of a memory hierarchy containing L1 and L2 caches and
main memory of given access times and hit ratio.
61. What data transfers occur in a 2-level exclusive cache system when an L1 cache miss is
followed by L2 hit/miss.
62. Describe the functionality of a program fragment causing WB/WA cache to yield lower
efficiency than WB/NWA.
63. Describe the situations causing incoherency of a memory hierarchy.
64. What are the functions of a memory management system?
65. What fields are contained in a segment/page descriptor?
66. How is the linear address generated in segmentation unit?
67. What is the meaning of Accessed and Dirty bits in a page descriptor. When and by what
means (software/hardware) are they set to 0/1?
68. When does the segmentation/paging unit signal a segmentation/paging error?
69. Why are page descriptor stored in tree-of-tables structures rather than in vectors?
Computer Architecture – test questions 4

70. What is a “table walk”?

71. Why does the table walk introduce significant delay?
72. Why is it important for computer's security to differentiate between data read and instruction
fetch memory access?
73. What is an exception?
74. Describe the kinds/classes of exceptions, give few examples of exceptions of each class.
75. What is the difference in service between interrupts and other kinds of exceptions?
76. Which PC vale is stored on entry to service of exceptions of various kinds?
77. Why the operating system services must be called using exception mechanism, not the
ordinary procedure call mechanism?
78. What is the difference between procedure return and exception service return?
79. How is the interrupt sensitivity level modified during entry to interrupt service?
80. What should be the relation between the processor's priority level and incoming interrupt's
priority to enter the interrupt service?
81. Explain the difference between processor's privilege level and priority level.
82. What information must be stored during entry to page fault service?
83. What is an “instruction restart” used during entry to error service?
84. What is the result of executing “return from exception” instruction by an application
program?
85. What hardware mechanisms must be supported by the processor to enable implementation
of a virtual memory system?
86. Describe the role of various hardware and software components in the implementation of
virtual memory.
87. When a page allocated to the process by the OS may have invalid descriptor?
88. What is a “lazy allocation” of memory?
89. Why in contemporary computers i/o devices are generally not serviced using polling?
90. What is the characteristics of devices that must be serviced using DMA?
91. List the control registers of a DMA channel and describe how the OS programs them while
preparing for a DMA transfer.