SYLLABUS

Name: Computer Architecture

Information on course:
Course offered by department: The Faculty of Electronics and Information Technology
Course for department: The Faculty of Electronics and Information Technology
Default type of course examination report:
Exam
Language:
English
Short description:
The target of the course is to introduce the students to the structural and logical concepts of contemorary computers in the way which is
appropriate for both programmers and hardware designers.The lecture cover basic definitions and taxonomies of computer architectures,
application programming model, structure of execution unit and memory hierarchy, system topics - principles and implementation of
resource protection and management and basic information on the structureof contemporary computers.
Description:
The target of the course is to introduce the students to the structural and logical concepts of contemorary computers in the way which is
appropriate for both programmers and hardware designers.The lecture cover basic definitions and taxonomies of computer architectures,
application programming model, structure of execution unit and memory hierarchy, system topics - principles and implementation of
resource protection and management and basic information on the structureof contemporary computers.

Lecture contents
• Introduction, basic definitions, computer architecture taxonomies (2h).
• Memory hierarchy, von Neumann machine - Harvard and Princeton variants. Data representations and formats - characters, numbers,
sounds, images (2h).
• Memory organization - addressing, Big- and Little Endian (1h).
• Application programming model - register set organizations, addressing modes, model of conditional operations, instruction set. CISC
and RISC approach (4h).
•
• MIPS R3000 programming model (1h).
• Basic x86 programming model in linear 32-bit environments (2h).
• MIPS Instruction execution in single-cycle datapath (1h).
• Multicycle (microcoded) processors - structures, bottlenecks, optimization. Prefetch queue, branch penalty. (2h).
•
• Pipelined execution unit - basic structure, RAW dependency, Load-Use penalty, branch penalty - problems and solutions. (3h).
•
• Superpipeline. CISC pipeline (1h).
• Superscalars: pseudo (i860), in-order execution, in-order issue, out-of-order completion, out-of-order execution. Dependencies and
hazards in superscalars - WAW, WAR (3h).
•
• Relaxing and avoiding dependencies - register renaming, data forwarding (2h).
•
• CISC implementations using instruction transcoding - principles and examples (2h).
•
• Reducing the branch penalty - branch prediction schemes - static and dynamic. Return stack. Speculative execution (2h).
• Principle of locality. Caches: organizations, efficiency model (3h).
•
• Reponse to write cycles. Victim (exclusive) caches. Cache coherency(2h).
• Resource protection and management in OS - principles. Memory manegement - functions, implementation -segmentation and
paging. Optimization of paging mechanism (5h).
•
• Exceptions - interrupts, traps, erors. Exception priorities. Exception service (4h).
• Structure of computer - bus. Structure of PC - buses and point-to point connections (2h).
•
• Tests (2h).
•

Laboratory contents
Assembler programming on SPIM (MIPS R3000 simulator) platform (2+4h). Hybrid programming of x86 processors in Windows or
Linux environment - C and assembler (2+4h).
 3. IA-32 Intel Architecture Software Developer`s Manual, Intel Corp., the last version available at developer.intel.com.
4.
5. MIPS32 Architecture for Programmers, MIPS Technologies, the last version available at www.mips.com.
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