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Fdmc6679Az: P-Channel Powertrench Mosfet
Fdmc6679Az: P-Channel Powertrench Mosfet
November 2013
FDMC6679AZ
P-Channel PowerTrench® MOSFET
-30 V, -20 A, 10 mΩ
Features General Description
Max rDS(on) = 10 mΩ at VGS = -10 V, ID = -11.5 A The FDMC6679AZ has been designed to minimize losses in
load switch applications. Advancements in both silicon and
Max rDS(on) = 18 mΩ at VGS = -4.5 V, ID = -8.5 A package technologies have been combined to offer the lowest
HBM ESD protection level of 8 kV typical(note 3) rDS(on) and ESD protection.
Top Bottom
Pin 1 D 5 4 G
G
S
S D 6 3 S
S
D 7 2 S
D
D
D D 8 1 S
D
MLP 3.3x3.3
Thermal Characteristics
RθJC Thermal Resistance, Junction to Case 3.0
°C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 53
Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = -250 μA, VGS = 0 V -30 V
ΔBVDSS Breakdown Voltage Temperature
ID = -250 μA, referenced to 25 °C 29 mV/°C
ΔTJ Coefficient
VDS = -24 V, -1
IDSS Zero Gate Voltage Drain Current μA
VGS = 0 V, TJ = 125 °C -100
IGSS Gate to Source Leakage Current VGS = ±25 V, VDS = 0 V ±10 μA
On Characteristics
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = -250 μA -1 -1.8 -3 V
ΔVGS(th) Gate to Source Threshold Voltage
ID = -250 μA, referenced to 25 °C -7 mV/°C
ΔTJ Temperature Coefficient
VGS = -10 V, ID = -11.5 A 8.6 10
rDS(on) Static Drain to Source On Resistance VGS = -4.5 V, ID = -8.5 A 12 18 mΩ
VGS = -10 V, ID = -11.5 A, TJ = 125 °C 12 15
gFS Forward Transconductance VDS = -5 V, ID = -11.5 A 46 S
Dynamic Characteristics
Ciss Input Capacitance 2985 3970 pF
VDS = -15 V, VGS = 0 V,
Coss Output Capacitance 570 755 pF
f = 1 MHz
Crss Reverse Transfer Capacitance 500 750 pF
Switching Characteristics
td(on) Turn-On Delay Time 12 21 ns
tr Rise Time VDD = -15 V, ID = -11.5 A, 14 25 ns
td(off) Turn-Off Delay Time VGS = -10 V, RGEN = 6 Ω 63 100 ns
tf Fall Time 46 73 ns
Qg Total Gate Charge VGS = 0 V to -10 V 65 91 nC
Qg Total Gate Charge VGS = 0 V to -5 V VDD = -15 V, 37 52 nC
Qgs Gate to Source Charge ID = -11.5 A 8.7 nC
Qgd Gate to Drain “Miller” Charge 17 nC
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %.
3. The diode connected between the gate and source servers only as protection against ESD. No gate overvoltage rating is implied.
32 4
VGS = -10 V PULSE DURATION = 80 μs
24
3
VGS = -4 V
NORMALIZED
VGS = -3.5 V VGS = -3.5 V
16
VGS = -3 V 2 VGS = -4.5 V
VGS = -4 V
PULSE DURATION = 80 μs 1
DUTY CYCLE = 0.5% MAX VGS = -6 V VGS = -10 V
0
0 1 2 3 0 8 16 24 32
-VDS, DRAIN TO SOURCE VOLTAGE (V) -ID, DRAIN CURRENT (A)
1.6 50
ID = -11.5 A PULSE DURATION = 80 μs
DRAIN TO SOURCE ON-RESISTANCE
ID = -11.5 A
SOURCE ON-RESISTANCE (mΩ)
VGS = -10 V DUTY CYCLE = 0.5% MAX
1.4 40
rDS(on), DRAIN TO
NORMALIZED
1.2 30
1.0 20
TJ = 125 oC
0.8 10
TJ = 25 oC
0.6 0
-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10
TJ, JUNCTION TEMPERATURE (oC) -VGS, GATE TO SOURCE VOLTAGE (V)
32 40
PULSE DURATION = 80 μs
-IS, REVERSE DRAIN CURRENT (A)
VGS = 0 V
DUTY CYCLE = 0.5% MAX 10
-ID, DRAIN CURRENT (A)
24 VDS = -5 V
1 TJ = 150 oC
TJ = 25 oC
16
0.1
TJ = 25 oC TJ = -55 oC
8
0.01 TJ = -55 oC
TJ = 150 oC
0 0.001
1 2 3 4 0.0 0.2 0.4 0.6 0.8 1.0 1.2
-VGS, GATE TO SOURCE VOLTAGE (V) -VSD, BODY DIODE FORWARD VOLTAGE (V)
10 10000
-VGS, GATE TO SOURCE VOLTAGE (V)
ID = -11.5 A
8 Ciss
CAPACITANCE (pF)
VDD = -15 V
6
VDD = -10 V VDD = -20 V
1000 Coss
4
Crss
2 f = 1 MHz
VGS = 0 V
0 100
0 10 20 30 40 50 60 70 0.1 1 10 30
Qg, GATE CHARGE (nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)
50 60
-IAS, AVALANCHE CURRENT (A)
10 Limited by Package
o
RθJC = 3.0 C/W
1 0
0.001 0.01 0.1 1 10 100 25 50 75 100 125 150
o
tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE ( C)
100 10
-2
VGS = 0 V
-Ig, GATE LEAKAGE CURRENT (A)
-3
10
-ID, DRAIN CURRENT (A)
10
1 ms
-4
10
10 ms
1 THIS AREA IS 10
-5
Figure 11. Forward Bias Safe Figure 12. Igss vs. Vgss
Operating Area
1000
VGS = -10 V
P(PK), PEAK TRANSIENT POWER (W)
100
10
SINGLE PULSE
o
RθJA = 125 C/W
1
o
TA = 25 C
0.3
-3 -2 -1
10 10 10 1 10 100 1000
t, PULSE WIDTH (sec)
2
DUTY CYCLE-DESCENDING ORDER
1
D = 0.5
0.2
NORMALIZED THERMAL
0.1
IMPEDANCE, ZθJA
0.05
0.1 0.02
PDM
0.01
t1
0.01 t2
NOTES:
DUTY FACTOR: D = t1/t2
SINGLE PULSE PEAK TJ = PDM x ZθJA x RθJA + TA
o
RθJA = 125 C/W
0.001
-3 -2 -1
10 10 10 1 10 100 1000
t, RECTANGULAR PULSE DURATION (sec)
3.30+0.10 A
0.10 C (3.40)
B 2.37
2X 8 5
0.45(4X)
2.152
(1.70)
3.30+0.10
(0.402)
KEEP OUT
AREA
(0.648)
0.70(4X)
PIN#1 QUADRANT
0.10 C 1
TOP VIEW 4
0.65 0.42(8X)
2X
1.95
0.8 MAX
0.10 C
(0.20) RECOMMENDED LAND PATTERN
0.08 C 0.05
0.00
2.27+0.05
PIN #1 IDENT
(0.79) A. DOES NOT CONFORM TO JEDEC
1 4 REGISTRATION MO-229
0.50+0.05
B. DIMENSIONS ARE IN MILLIMETERS.
(4X)
(1.15) (0.35) C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. LAND PATTERN RECOMMENDATION IS
R0.15
2.00+0.05 BASED ON FSC DESIGN ONLY
0.30+0.05
(3X) E. DRAWING FILE NAME : MKT-MLP08Srev2
F. FAIRCHILD SEMICONDUCTOR
8 5
0.65 0.35+0.05 (8X)
0.10 C A B
1.95 0.05 C
BOTTOM VIEW
DISCLAIMER
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RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY
PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY
THEREIN, WHICH COVERS THESE PRODUCTS.
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Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I66