Module 2

Specification of a typical 300 mm wafer used in

fabrication
Metallurgical Grade Silicon (MGS)
Impurities in MGS after submerged arc electric
process
 Contd.
• Starting material – Sand
Conversion from MGS to EGS
Contd.
Siemens process
Impurities in EGS after purification from MGS
 Single crystal SI manufacture
• Czochralski technique
• Float zone technique
Czochralski technique
Single crystal Si ingot
Float zone technique
Wafer slicing
IC fabrication
Wafer showing individual dies
Wafer components
Wafer
components
1 - Chip
2 - Scribe line
3 - Test die
4 - Edge chips
5 - Wafer crystal plane
6 - Flats/notches
 Basic processing steps
• Layering
• Patterning
• Doping
• Heat treatment
 Layering
• Adding thin layer to surface of wafer
• Layer – different or same material
• Broadly classified:
oGrown: Wafer material is consumed

oDeposited: New layer is added on top

MOSFET cross section showing different layers
 Chemical Vapor Deposition (CVD) process
• Growth of epitaxial layer
• Epitaxial layer – same or different material
 Layering techniques – Contd.
• Physical vapor deposition techniques:
oMaterial (in final form) is deposited on wafer
oEx -
❑Evaporation
❑Sputtering
oUsed for metals, oxides, nitrides and other types of layers
• Electroplating:
oCopper deposition
oCopper – interconnects in IC
 Patterning
• Other name – lithography
• Selectively mask or expose portions of surface
• Pattern smaller wafer regions – more devices in chip
• Highly defect sensitive at smaller sizes
Effect of defect particles on patterning
Patterning process -
overview
 Doping
• Impurities are added through openings on wafer surface
• Dopant materials – n-type or p-type
• Form devices like transistors, conductors, diodes
• Two techniques:
oThermal diffusion
oIon implantation
Thermal diffusion
Ion implantation
NMOS Fabrication
Step - 1
Step - 2
Step - 3
Step - 4
 Step – 5
• Remaining photoresist is removed
• Thin SiO2 layer is grown
• Polysilicon is added for gate formation
• Why polysilicon is preferred?
oHigh melting point
oSimilar properties as that of SiO2
Step - 6
 Step - 7
• SiO2 and photoresist is again deposited on source and drain terminals
Step - 8
CMOS Fabrication
 Steps involved
• Wafer
• Oxidation of wafer
• Photoresist deposition
• N-well mask
• Oxide Etch
• N-well formation
• Oxide removal
• Gate formation
N-well formation
 Steps involved
• Poly patterning
• Diffusion pattern
• Creating area for source and drain
• N-diffusion regions
• P-diffusion
• Field oxide
• Metal formation
Diffusion pattern
N-diffusion regions
P-diffusion
Field oxide
Metal formation
Twin-tub Fabrication
CMOS Isolation Techniques
Local Oxidation of Silicon (LOCOS)
Shallow Trench Isolation (STI)
Design rules
 Introduction
• Complex processes - difficult to understand intricacies of fabrication
process
• Solution: define set of design rules
• Design rules – specifies geometric constraints on layout
 Scalable design rules
• Defined in terms of lambda
• Portable design as technology scales with time
• Usage of absolute design rules – deep submicron design
 Layouts representation
• Symbolic layout:
oSchematic drawing showing rectangles corresponding to objects
oUse color coding convention
• Stick diagram:
oCompact representation
oEvery object is shown as line
oDesign rules tells width and spacing between lines
n-channel MOS transistor
n-channel transistor layout
p-channel MOS transistor
Fabrication layers
Color Convention
General design rules
Width/Spacing Rules (MOSIS)
Poly-diffusion interaction
Contact spacing
M2 contact (via)