2010 23rd International Conference on VLSI Design
An Efficient Design of a Reversible Barrel Shifter
Irina Hashmi
Department of Computer Science & Engineering
University of Dhaka
Dhaka, Bangladesh
irina.hashmi@gmail.com
Abstract
The key objective of today’s circuit design is to increase the
performance without the proportional increase in power
consumption. In this regard, reversible logic has become an
immensely promising technology in the field of low power
computing and designing. On the other hand, data shifting and
rotating are required in many operations such as arithmetic
and logical operations, address decoding and indexing etc. In
this consequence, barrel shifters, which can shift and rotate
multiple bits in a single cycle, have become a common design
choice for high speed applications. For this reason, this paper
presents an efficient design of a reversible barrel shifter. It
has also been shown that the new circuit outperforms the
previously proposed one in terms of number of gates, number
of garbage outputs, delay and quantum cost.
1. Introduction
Reversible system does not allow information to be erased.
Thus the reversible gates have the same number of inputs and
outputs which means that the input stage can always be
retained from the output stage. Landauer [1] pointed out that in
an irreversible system, erasure of a single bit generates kTln2
joules of heat energy where k is Boltzmann’s constant of
1.38x10-23 and T is the absolute temperature of the
environment. Based on this observation, Bennett [2] showed,
for a reversible computer the heat dissipation is exactly kTln1
which is logically zero. Thus reversible computation is a highly
potential field for upcoming low power/high performance
computing. For this reason, designing different reversible gates
and combinational circuits has gained considerable importance
than ever before.
1063-9667/10 $26.00 © 2010 IEEE
DOI 10.1109/VLSI.Design.2010.35
Hafiz Md. Hasan Babu
Department of Computer Science & Engineering
University of Dhaka
Dhaka, Bangladesh
hafizbabu@hotmail.com
Designing reversible circuits using reversible gates have
several constraints [3]:
a. The fan-out of every signal is equal to one.
b. Loops are not permitted in a strictly reversible system.
On the other hand, data shifting and rotating is important
and frequently used in arithmetic operations, variable-length
coding, bit-indexing and many more. In this consequence,
barrel shifters which are capable of performing n-bit shifting
and rotating of data in a single cycle, are normally used in
embedded processors such as: digital signal processors [4] and
high performance processors [5], high-speed/low-power
applications [6] etc. However, only one paper [7] has been
proposed so far on reversible barrel shifter. Thus this research
focuses on designing an efficient barrel shifter and then
evaluates several significant parameters for this reversible
circuit design.
The structure of the paper is as follows: Section II provides
the necessary background on reversible logic as well as the
definitions of some commonly used reversible logic gates.
Several irreversible barrel shifters are described in Section III.
Section IV presents the existing reversible barrel shifter as well
as our proposed one and discusses about some properties of the
proposed circuit. Then it compares the novel shifter to the
existing one. Lastly, the conclusions and further studies are
discussed in Section VI.
2. Basic Definitions
In this, section we present some definitions on reversible
logic for future reference. Then we formally illustrate the
commonly used reversible logic gates and mention their
quantum cost.
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 Definition 1. A Reversible Gate is an n-input, n-output
(denoted by n * n) circuit that uniquely maps the output vector
Ov to the corresponding input vector Iv where Iv = (I0, I1, I2 … Ik-
1, Ik,) and Ov = (O0, O1, O2 … Ok-1, Ok) [8].
Definition 2. To maintain the reversibility property of
reversible logic gates several dummy output signals are needed
to be produced in order to equal the number of input to that of
output. These signals are commonly known as Garbage
Outputs. For example, for reversible Exclusive-OR operation
Feynman gates are used which produce an extra dummy output
along with its principal output signal to preserve reversibility.
The garbage output is denoted by P in Figure 1.
A P=A
Feynman
Gate
B P = A⊕B
Figure 1. Garbage output of Feynman Gate
Definition 3. The calculation of quantum cost (QC) has
several approximations. Firstly the quantum cost of every 2*2
gate is the same [9] and it is 1. Secondly, since each 1*1 gate
can always be included to any 2*2 gate that precedes or follows
it, the quantum cost of the 1*1 gate is considered to be zero.
Thus every reversible gate is a combination of 1x1 or 2x2
reversible gate. So the quantum cost of a reversible circuit
calculates the total number of 2*2 gates used.
Definition 4. The delay of a logic circuit is the maximum
number of gates in a path from any input line to any output
line. The definition is based on the following two assumptions
[9]:
a) Each gate performs the computation in one unit time.
b) All inputs to the circuit is known before the
computation begins.
From the above definition the delay of the logic circuit in
Figure 1 is obviously 1 as this is the only gate from any input
to output line.
Now we will define some popular reversible gates which
will be needed in our work.
Definition 5. The input vector, Iv and output vector, Ov for
2*2 Feynman Gate (FE) [10] is defined as follows: Iv = (A, B)
and Ov = (P = A and Q=A ⊕ B). Figure 1 shows the block
diagram of the reversible Feynman gate. Feynman gates are
typically used as copying gates. If Iv = (A, B=0) then Ov = (P =
A and Q=A). The quantum cost of FE is 1.
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Definition 6. The 3*3 Toffoli gate (TG) [11] is defined as
follows: input vector Iv = (A, B, C) and output vector Ov = ( P
= A, Q = B and R = AB⊕ C). The block diagram for 3*3
Toffoli gate is shown in Figure 2. The quantum cost of Toffoli
gate is 5 [9].
A P=A
Toffoli
B Gate Q=B
C R = AB⊕C
Figure 2. Block diagram of a 3*3 Toffoli Gate.
Definition 7. The input and output vector for 3*3 Fredkin
gate (FR) [12] are defined as follows: Iv = ( A, B, C ) and Ov =
(P=A, Q= AB ⊕ AC and R = AC ⊕ AB ). Figure 3 shows the
block diagram of a 3x3 Fredkin gate. The quantum cost of FR
is also 5 [9].
A P=A
Fredkin
B Gate R = A'C ⊕ AB
C Q = A'B ⊕AC
Figure 3. Block diagram of a 3*3 Fredkin Gate.
3. Barrel Shifter
A barrel shifter is a combinational circuit which has n-input
and n-output and m select lines that controls bit shift operation.
Since multiple and variable bit shifting are more desirable than
single bit operations several irreversible barrel shifters have
been proposed in that consequence. Barrel shifters can be
unidirectional which performs the shift/rotate operation to left
(or right) or bidirectional that are capable of shifting/rotating to
the both directions.
In [13], an irreversible shifter has been described. This
shifter shown in Figure 4 consists of several transmission paths
which are built from simple n-type transistors. The control lines
operate vertically, the input lines rise diagonally and the output
lines run horizontally. At a time exactly one control line is set
which turns on all the switches in a single column. The length
of the shifting is determined by the position of the selected
column. Thus all the inputs are shunted to the output lines. This
shifter is very simple in design and transmission delay is
minimal while the circuit requires large area.
 parameters include total number of gates to be used in the
design, garbage outputs, delay and quantum cost of the circuit.

4. Reversible barrel shifter

In this section we will discuss about the existing
reversible barrel shifter and then we will propose the new one.
After that, we will prove some properties of the proposed
shifter and then make a comparative study between the
existing and the proposed one.

Figure 4. Section of a Barrel Shifter [13] 4.1. Existing Reversible Barrel Shifter

The existing shifter is a unidirectional logarithmic shifter

Another design choice for multiple data shifting is
logarithmic barrel shifter as shown in Figure 5. An n-bit
logarithmic barrel shifter has a total of log2 (n) stages. Each
stage determines whether to shift or not to shift the input data.
If the control bit sk ( where k = 0, 1, … (log2(n)-1) ) is set to 1
then the stage k will shift the input 2k times otherwise the input
will remain unchanged. Logarithmic shifter is more efficient in
terms of design as well as area but delay cost is large [7].
consists of multiplexers. A 3x3 Fredkin Gate works as simple
(2:1) multiplexers. Feynman gates are used for producing fan
outs. The shifter with n-bit data value and k-bit shift value will
require the following number of gates according to [7]:
Number of Fredkin Gates f = (2k-1) x n
Number of Feynman Gates g = n x (2k-1)
Number of Garbage Outputs GO = f + k = k + [(2k-1) x n]

The shifter from [7] with 4-bit data value and 2-bit shift value
Input
is shown in Figure 6.
n

s0 20 Shifter

n
1
s1 2 Shifter
.
.
. n
.
k-1
sk-1 2 Shifter

n
Left/ Right
Output

Figure 5. (n, k ) Logarithmic Barrel Shifter Figure 6. Reversible (4, 2) Barrel Shifter proposed in [7]

Several other complex design patterns for irreversible
shifter have also been proposed. Barrel shifter using
multipliers [14], MUX based data reversal barrel shifter and
shifter/rotator with overflow flag have also been discussed in
[15]. But only one paper [7] has been published so far on
reversible barrel shifter. In the next section we will discuss
about this existing one and then propose our novel reversible
circuit. Then we will also make a comparative study between
these two based on several designing parameters. The
The existing shifter is complex in design and requires
large number of gates. As a result the total number of garbage
outputs is high. Thus there is great room for improving the
circuit complexity, total number of gates and garbage outputs,
delay and quantum cost.
4.2. Proposed Reversible Barrel Shifter
For efficient designing of a reversible circuit several criteria
are needed to be considered:

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 a. Minimize the number of gates as possible.
b. Minimize the quantum cost of the circuit.
c. Total number of garbage outputs and usage of
constant inputs should be minimized.
By maintaining the above parameters and observing the
previous design, we have proposed a novel logarithmic
Reversible Barrel Shifter. The proposed barrel shifter is a left
rotating shifter which uses Fredkin gates for reversible (2:1)
multiplexing and Feynman Gates for producing fan outs.

4.3. Design procedure of the proposed shifter

In this section we will first present the algorithm for
shift/rotate operation of an (n, k) reversible barrel shifter. Then
we will explain the shifter with the example and appropriate
diagram of a (4, 2) shifter.
Algorithm: Shift/Rotate operation of an (n, k) barrel
shifter.
Input: Data Input Set I (io, i1 … in-1), n = total number of
data input bit.
Control input Set S (s0, s1, … sk), k = log2 (n).
Output: Desired shift/rotate output set O (o1, o2, … oi).
begin
Step 1: for k <- 0 to log2(n)
Step 2: do if sk = 1
Step 3. then left shift /rotate I 2k times
Step 4. else I remains same
end.
The circuit works as follows: Each stage of Fredkin gate
shifts the input according to the control value of sk. Suppose, to
design a (4, 2) shifter which takes i0, i1, i2, i3 as data inputs and
s0s1 = 11 as select input. So the input will be shifted 20 + 21 = 3
times to the left. Thus the sequence of the shift/rotate operation
will be i1i2i3 i0 for the first stage and then i3i0i1i2 for the next. On
the other hand, for the select input s0s1 = 00, the input sequence
will remain same for both stages of multiplexing.
Thus, each Fredkin gate chooses between two input lines it
receives and performs the appropriate operation according to
the select input of that particular stage. Hence, for the first
stage (Stage 0) of above (4:2) shifter, the first Fredkin gate will
either select input i0 or i1, the second one will do either i1 or i2
and so on. All other stages perform the selection task in the
same way.
Figure 7. Proposed Reversible (4, 2) Barrel Shifter
Based on the above idea, a (4, 2) logarithmic barrel shifter
has been illustrated in Figure 7. The circuit uses a total of 6
Fredkin gates, 4 Feynman gates and produces 6 Garbage
outputs. The Quantum cost of the circuit has also been
evaluated according to [9]. The calculation shows that the
Quantum Cost of the proposed (4, 2) circuit is 34. According to
the definition 5, the unit delay of the above circuit is 6 as there
exists maximum of 6 gates between any input to any output
line.
4.4. Properties of the proposed Reversible Barrel
Shifter
From the above explanation and designing procedure we
will now present several important properties of the proposed
(n, k) reversible barrel shifter.
Theorem 1. A unidirectional reversible barrel shifter with
n-bit data input and k-bit shift value can be realized with at
least fr number of Fredkin Gates for multiplexing where,
fr = n(k-1) + n/2
Proof: The proposed barrel shifter requires n Fredkin gates
for each stage except the last stage of multiplexing. For the
design pattern, the last stage of multiplexing requires n/2
numbers of Fredkin gates. Thus if the total number of stages is
k, then a (k-1) number of stages will have a total of n(k-1)
Fredkin Gates. So the circuit can be realized with at least
n(k-1) + n/2 number of Fredkin gates.
Theorem 2. Let n be the total number of data input bits
and k be the shift value bit of a unidirectional reversible shifter.
Let fe be the total number of Feynman Gates for producing fan
outs, then
fe = n(k-1)

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 Proof: Each Feynman gate produces two copies of single GO 244 52
input as described in Section 4. For the proposed n-bit barrel D 132 28
shifter each stage requires copying each input twice, but for the
fr 992 144
design pattern the last stage of the shifter does not need the
copying circuits. So the circuit can be realized with at least (32, 5) fe 992 128
n(k-1) number of Feynman Gates for fan out operations. GO 997 133
D 517 52

Theorem 3. Let n be the total number of data input bit and fr = Total number of Fredkin gates
k be the shift value of a unidirectional reversible barrel shifter. fe = Total number of Feynman gates
Let GO be the total number of garbage outputs of the proposed GO = Total number of Garbage Outputs
shifter, then D = Total Delay of the circuit
GO = n(k-1) + k
Proof: The number of Garbage output is proportional to
the number of Fredkin gates as each Fredkin gate except the Table 2. Comparison of the quantum cost of the barrel
last one of each stage produces at least one garbage bit. The shifters
last Fredkin gate of each stage adds an extra garbage bit to the Existing Design [7]
(n, k) Proposed Design
shifter. On the other hand, for the last stage of shifting
operation the cascaded Fredkin gates produces only one extra (4, 2) 72 34
bit. Thus the (k-1) number of stages produce a total of n(k- (8, 3) 336 116
1)+(k-1) Garbage bits and last stage adds only one garbage bit. (16, 4) 1440 328
Thus, the proposed shifter produces n(k-1) + (k-1) + 1 which is
n(k-1)+ k number of garbage outputs. (32, 5) 5952 848

4.5. Comparative study between the reversible barrel 5. Conclusion

shifters

Comparing with the existing barrel shifter to the proposed In this paper, an efficient novel logarithmic reversible
one, we observe the result shown in Table 1 and Table 2. From Barrel Shifter has been proposed. Then based on reversible
Table 1 we can see that the proposed circuit requires less circuit designing criteria several theorems have been proposed
number of gates, produce less garbage outputs. The delay costs for total number of gates required by the combinational circuit.
(D) of the two circuits have also been calculated according to The Garbage outputs, delay and quantum cost have also been
the definition [4]. The quantum cost of the circuit, calculated estimated. At last a comparison study between the only existing
according to the [9], is also shown in Table 2 which proves that circuit and the proposed one has been shown. At present, the
the present circuit performs much efficiently than the previous proposed barrel shifter is capable of left shift/rotate. Future
one. The performance improves as the size of the circuit grows. enhancements include bi-directional shift and shift/rotate
operations, logical or arithmetic shift operations. In that case,
more control inputs are needed to be added in the circuit.
Table 1. Comparative study of the reversible barrel
shifters
Existing Proposed
6. References
Criteria
(n, k) Design [7] Design
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(4, 2) Computing Process," IBM Journal of Research and Development,
fe 12 4
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GO 14 6
D 10 6 [2] C.H. Bennett, Logical reversibility of computation, IBM J. Res.
fr 56 20 Dev. 17 (1973) 525-532.
(8, 3) fe 56 16
59 19 [3] Hafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja
GO
Chowdhury and Syed Mostahed Ali Chowdhury, “Reversible Logic
D 35 14 Synthesis for Minimization of Full-adder Circuit”, IEEE Conference
fr 240 56 on Digital System Design 2003, Euro-Micro’03, Belek, Antalya,
(16, 4) Fe 240 48 Turkey, 2003, pp. 50-54.

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