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The LC3 Datapath (Chapter 5, Appendix B, C)
The LC3 Datapath (Chapter 5, Appendix B, C)
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LC3 Datapath – from Logic to Processor Data Path
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LC-3 Data Path – The complete datapath
PC is initialized to point to
the first instruction. Clock
is enabled, and the
control unit takes over.
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A Useful Analogy
• The datapath corresponds to the tracks in a railway
o pathways that allow you to move information around the CPU
• The control signals control the switches that connect tracks
o Signals that setup the pathways so data can flow through CPU
•Memory
• Control and data registers for memory and I/O devices
• memory: MAR, MDR (also control signal for read/write)
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LC-3 Data Path- Components
Memory interface:
MAR
MDR
Read/Write
control
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Data Path Components
•ALU
• Accepts inputs from register file
and from sign-extended bits from IR (immediate field).
o Bit 5 of LC3 instruction determines this
• Output goes to bus.
o used by condition code logic, register file, memory
• Function to apply: determined by opcode – need 2 bits ALUK
•Register File
• Two read addresses (SR1, SR2), one write address (DR)
• Input from bus
o result of ALU operation or memory read
• Two 16-bit outputs
o used by ALU, PC, memory address
o data for store instructions passes through ALU
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Data Path Components
• PC and PCMUX
• Three inputs to PC, controlled by PCMUX
1. PC+1 – FETCH stage
2. Address adder – BR, JMP
3. bus – TRAP (discussed later)
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LC-3 Data Path
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16
16
8
gatePC 16
3
Control LD.PC PC
DR REG
PCMUX +1 FILE
2 LD.REG
PCMUX
SR2 SR1 3
16 3
SR2 OUT OUT SR1
components in 16
the Datapath
Processor
FINITE SR2MUX
STATE
MACHINE B A
2
R ALU
LD.IR IR
gateALU
16
16
16 GateMDR 16
INPUT OUTPUT
16
KBDR DDR
LD.MDR
MDR MEMORY MAR LD.MAR
KBSR DSR
MEM.EN, R.W
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Instruction Processing Cycle – implementation of
LC3 Datapath
Six phases of the complete Instruction Cycle
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LC3: Instruction Fetch
gatePC 1
LD.PC PC 1
16
PCMUX +1 Control signals:
Logic needed 2 • LD.PC
PCMUX
for branch & jump 16
• gatePC
+ • PCMUX
ADDR2MUX
• LD.MAR
• MEM.EN,R
2
ADDR2MUX ADDR1MUX ADDR1MUX • GateMDR
16
• LD.CC
Branch inst: 16 16
PC+Offset 0 • LD.IR
• (ADDR2MUX
[8:0] SEXT
FINITE • ADDR1MUX)
STATE
2
N Z P LD.CC MACHINE
R
LD.IR IR LOGIC
16 16
16 GateMDR 16
3
16
LD.MDR LD.MAR
MDR MEMORY MAR
MEM.EN, R.W 21
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Instruction Processing Cycle- Remaining steps
• After Instruction fetch and decode, the next cycles are
evaluate address, operand fetch, execute, store.
• To design datapath and control unit:
• What are the logic devices needed to execute instructions
• What control signals should be generated by the control unit
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Register mode:
Operands are in registers ADD:
Dst= Src1 + Src2
R2= R1 + R3
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ADD/AND (Immediate) this one means “immediate mode”
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Control signals: 3
• SR1, SR2, DR
DR REG
FILE
• LD.REG LD.REG
• SR2MUX
SR2 SR1
• ALUK SR2
3
OUT OUT
3
SR1
• gateALU
16 16
0
16
SEXT
[4:0]
FINITE SR2MUX
STATE
MACHINE 2
B A
ALU
LD.IR IR
gateALU
16 16
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26
13
LD (PC-Relative)
abcd
1004
abcd
offset
1004
gateMARMUX gatePC 16
3
MARMUX
MARMUX LD.PC PC 1 DR REG
16
PCMUX +1 FILE
16 16 2 LD.REG
PCMUX
SR2 SR1 3
16 3
ZEXT SR2 OUT OUT SR1
2 +
ADDR2MUX
[7:0]
2
ADDR1MUX
ADDR2MUX ADDR1MUX 16 16
16
16 16 16 16
[10:0] 16
SEXT
0
16
SEXT
[8:0] [4:0]
SEXT
1 FINITE SR2MUX
STATE
[5:0] SEXT
N Z P LD.CC MACHINE B A
2
R ALU
LD.IR IR LOGIC
gateALU
16 16 16
16 GateMDR 16
4 16
3
LD.MDR
MDR MEMORY MAR LD.MAR
INPUT OUTPUT
MEM.EN, R.W 30
30
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LD Instruction steps and control signals
• Signals to add PC+offset & load into MAR MAR <- PC+offset9
• ADDR1MUX
• ADDR2MUX
• MARMUX
• gateMARMUX
• LD.MAR
• Signals to Read R MDR <- M[MAR]
• MEM.EN, R
• LD.MDR
• Signals to store into DestReg & CC
• GateMDR DestReg <- MDR
• DR bits Set CC registers
• LD.REG
• LD.CC
Go to Fetch
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The Instruction Cycle as FSM
A simplified state diagram
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Complete FSM for LC3
Control Unit
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Control Unit, Data Path, and Memory -
Interactions
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Microprogrammed Implementation
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Datapath Summary
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