ICSE2010 Proc.
2010, Melaka, Malaysia
A study for Optimum Productivity Yield in 0.16µm
mixed of Wafer Fabrication Facility
Mohd Azizi Chik, Ve Chun Yung, Puvaneswaran Balakrishna, Uda Hashim, Ibrahim Ahmad & Bashir Mohamad
Institute of Nanoelectronic Engineering of Universiti Malaysia Perlis, Universiti Tenaga Nasional and Silterra Malaysia Sdn Bhd
mohd_azizi@silterra.com
Abstract- This research is to study the opportunity to achieve
optimum productivity yield in 0.16µ µm product mixed through
understanding the impact of loading utilization towards the capac-
ity. The study is important to model the overall strategy of product
loading planning to get highest achievable product output at re-
spective time like monthly or yearly. The product mixes target
used in this analysis includes 0.20um to 0.13um for high voltage,
logic CMOS and also mixed signal RF. Input in analysis are list of
process flow for various technologies and products, major manu-
facturing activities and equipment configuration that is based on
actual wafer fabrication facilities systems. Part of the complexities
of the research is its long cycle time process from 45minutes to 9
hours, for respective same processing step that drives from varies
technology and process equipment capable. Overall cycle time is
from 30 days to 90 days that is various comparing product-to-
product requirements. Further added to the complexity is the
equipment used for this analysis that is more than 100 difference
equipment configurations. More than 50% of the equipments are
with difference configuration. Most products experienced re-
entranced more than 85% times to same equipment type. This
analysis done on generic semiconductor fab modeled using indus-
tries software, AutoSchedAP. The fab model configured intensive-
ly so match with exactly operation of the fab, with equivalent al-
most 100% manufacturing operation, product loading and tool
configuration. The results have been successfully developed into a
curve an equation shows the optimum product loading and gives
opportunity of improvement in revenue and also overall efficiency
of more than 10%. Further results of this study also summarized
ranges of fab utilization versus cycle time that support overall
product delivery. Other impacts are also discussed in the sum-
mary.
Index Terms—Cycle Time, Simulation, Work In Progress
(WIP).Silicon Wafer Manufacturing Plan (Fab).
I. INTRODUCTION
The study to get the optimum yield for productivity in wafer
fabrication is critical in order to determine optimum product
allocation of the capacity available. The results then can be
used to translate commitment of product volume to delivery
date to the customer at optimum productivity yield. The opti-
mum productivity yield is critical target to exercise for every
opportunity available as wafer fabrication is capital-intensive
978-1-4244-6609-2/10/$26.00 ©2010 IEEE
investments that a full wafer fabrication facility can be easily
cost more than USD one billion dollars [1].
Till today the closest research regards optimum productivity
yield is only been focus on the cycle time optimization to ob-
tain the Cycle Time Versus Throughput curve (CT-TH) [2].
Most of this study is related to understand the queue time mag-
nitude and variability. Proved that reducing the inherent varia-
bility of a manufacturing operation improves the overall cycle
time [7]. Nevertheless, the new variability introduces as high
volume output fabout thus can be reduced in term of cycle time
improvement [3]. However, none of this further study of the
related reveals the productivity yield in optimum fabout. This is
due to the requirement to enhance the study required longer
time period versus more configurations towards the equipment
WIP profiling validation and intensive time effort [4]. Thus,
another study is required.
II. METHODOLOGY
This study is been done using AutoSched AP (ASAP) and
Advanced Productivity Family (APF) software. This software
was widely used in the semiconductor wafer fabrication indus-
tries [6]. List of company that used the software include Intel,
AMD, Global Foundry, Silterra Malaysia, and many others [1].
The software was configured and integrated with current the
respective automation systems to get the accurate information
automatically. The automation is needed since the study is
based on the actual loading of the product for start of the simu-
lation period. The information that was configured into the
model are WIP, equipment utilization, setup time, preventive
maintenance, process efficiency, recipe availability, dispatching
method at respective equipment and process, lot on hold trend
for future hold, current lot on hold and release timing, manufac-
turing efficiency on traveling or transferring and loading to
unloading the equipment, future loading plan and also possible
seasonal interruptions [5]. This is needed to compensate time
taken to remodel the complexity of wafer fabrication processes
that do re-entrance for photolithography processes. Fig. 1
shows overall wafer fabrication process flow complexity. Fig. 2
illustrates overall architecture of the input data into the simula-
tion model. After the model was configured with the foundry
requirements, it was tested to validate its accuracy.
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 ICSE2010 Proc. 2010, Melaka, Malaysia
In the simulation model, the station is consists of equip-
ments, equipment groups and dispatching rules criteria to select
product priorities. A total of 521 equipments were configured
in the model to tailor existing dispatching rules in the real man-
ufacturing operation. Equipment recipes dedication and capa-
bility were also automatically integrated in the model. Each
product process flow was integrated with real production route
that consists of more than 100 routes or process flows, which
ranges from 300 to 900 steps for each product process flow.
The step cycle time was also integrated with each product. The
production plan was created for duration of 2 years, equipment
calendar for future maintenance; WIP priority and historical
hold trend were well integrated into the model. After the simu-
lation modeling was completed, verification process was done
to ensure the AutoSched AP (ASAP) model run accordingly.
Fig. 1. Overall processing step, a complexity arouse in re-entrance to same
equipment for wafer fabrication operation.
Fig. 2. The element factors in simulation model.
During the simulation run, all events were traced properly
into respective database that allowed verification steps could be
conducted properly such as lot through steps and to check if
there was any error. During the preparation mode, many trial
runs were conducted to validate specific equipment configura-
378
tion accuracy. After the verification process, the simulation
results were validated to ensure they were adequately
representing normal wafer fabrication operations indices. The
actual data set such as stage Moves, production out or known as
wafer out, WIP level, tool efficiency and utilization data was
analyze.
It took almost 8 months to fill up respective gaps compared
to actual. The analysis performed to compare wafer moves had
successfully identified major gaps for the throughput, equip-
ment availability, and manufacturing efficiency. In earlier veri-
fication stage, the results only achieved 75% of the accuracy
compared to actual. Further improvements in equipment confi-
guration; have led to the average of 96% model configuration
matched with the benchmarking wafer fabrication operation.
Fig. 3 and 4 show the comparison analysis between the actual
moves versus forecasted moves, which achieved the average of
96% accuracy today.
Fig. 3. Overall move forecast vs actual
Fig. 4. Move forecast vs actual by wafer fabrication area
III. RESULTS AND DISCUSSION
More than 100 simulation runs were done with different
loading percentages that take up month of simulation run to
complete. Fig. 5 and 6 shows the breakdown of the loading
 ICSE2010 Proc. 2010, Melaka, Malaysia
volume at respective utilization percentage yield trends of the
productivity yield and overall productivity yield by month. A
quick view shows that a cumulative number for a year for prod-
uctivity yield line for 100% capacity utilize is lower compared
to 80% capacity utilize line. However, for 2 years comparison,
it does give the highest overall productivity yield.
The results show that if the product volume is above 83%
percentage, wafer out monthly will be in wave shape instead of
linear line. 83% product loading yield gives more output com-
pared to 100% product yield in yearly period. A verification
towards queue time established comparing to the cycle time.
Fig. 7 shows the curve where the cycle time increases at an
exponential rate when the capacity utilization reaches 100%.
Fig. 5. Monthly wafer out behavior analysis
The results obtained from the simulation model had revealed
the cycle time behaviors when the wafer Fab is running under
different utilization rate.
Fig. 6. Extended Chart for Monthly wafer out behavior analysis
vs the loading percentage
This trend for the average total product cycle time versus
product loading utilization is quite similar with the generics
results published [2]. However, the difference density of the
curve is due to the product mixes used and different type of
capacity or equipment types.
The results show that if the product volume is above 83%
capacity utilize percentage, wafer out monthly will be in wave
shape instead of linear line. This result raised interesting topic
to understand further regards the relationship between cycle
time and equipment utilization.
Fig. 7. Cycle Time Vs. Utilization Rate
IV. CONCLUSION
A study for optimum productivity yield in 0.16mm mixed of
wafer fabrication facility had given an insight idea for overall
planning for wafer foundry. For the high mixed of product re-
quirement, 100% capacity loading can help to maximize the
equipment utilization or assets utilization. However, it does not
give good contribution towards product, cycle time and maxi-
mum throughput for overall monthly or yearly. Therefore for
this analysis, 100% loading to the capacity limit does not give
the maximum output for period of a year. The production vo-
lume gain for capacity utilization rate at 83% is 10.3% more
output in first year compared to 100% utilize. However for
second year the volume for 100% loading recovered. As com-
pany work for yearly based annual report and high demand
product needed in shortest possible period, this analysis needed
to be reviewed.
Results also explained in the queue time chart figure 7. How-
ever, the significant results can be seen twice yearly. Neverthe-
less, most of the company does financial yearly and do not
guaranteed product for next following year. Further study to-
wards this results to be explored In this analysis, a good num-
ber to reach better control of stabilization is at 83% utilizations.
More studies like an impact of dispatching rule may lead to
higher stabilized capacity utilization rate. Further study in this
same topic and difference scope analysis is in progress where
more comprehensive results to understand the WIP and equip-
ment utilization behaviors can be further discussed.
V. ACKNOWLEDGEMENT
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 ICSE2010 Proc. 2010, Melaka, Malaysia
Authors would like to thanks Silterra Managements and In-
dustrial Engineering, for their continued supports in this re-
search.
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