TRUTH TABLE

INPUTS OUTPUTS
A B Cin S Cout
0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

K MAP SIMPLIFICATION

SUM COUT
BCin
BCin 00 1 01 00 01 11 10
11 01 11 10

1 1 1

A A
1 1

1 1

0 0

1 1

LOGIC EXPRESSION

SUM = A' B' Cin+AB' Cin'+A' BCin'+ABCin

= A'(B'Cin+B Cin')+A(B' Cin'+BCin)
= A'(B ⊕ Cin)+A(B ⊕ Cin) '
= A ⊕ B ⊕ Cin
CARRY = AB+BCin+ACin
S=A ⊕ B ⊕ Cin Cout=AB+BCin+ACin

FULL ADDER LOGIC

FULL ADDER OUTPUT

EXP:1 a) FULL ADDER

AIM

To Design and implement a fulladder using Xilinx tool and verify the truth table and logic gates

SOFTWARE REQUIRED

Xilinx ISE Design Suite v14.7

THEORY

Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs are A
and B and the third input is an input carry as C in. The output CARRY is designated as Cout and the
normal output is designated as S which is S UM.A full adder logic is designed in such a manner that can
take eight inputs together to create a byte-wide adder and cascade the carry bit from one adder to the
another.

SUM (S)= A ⊕ B ⊕ Cin CARRY(Cout)= AB+BCin+ACin

APPLICATIONS

 The Basic building block of on-chip applications

 Configured according to desired complexity of arithmetic and numeric computations
 In processors and other kinds of computing devices,adders are used in ALU’s
 To calculate addresses,table indices and similar operations
 In Ripple carry adder ,it adds n-bit at a time
 In instruction counter, which keeps track of the next instruction to be executed.
SOURCE CODE

module fulladd(input A,B,Cin,output S,Cout);

wire u,v,w;

xor G1(u,A,B);

and G2(v,u,Cin);

and G3(w,A,B);

xor G4(S,u,Cin);

or G5(Cout,v,w);

endmodule
RESULT

Thus the design and implementation of full adder has been successfully done using Xilinx tool and
truth table ,logic gates are verified
 TRUTH TABLE

INPUTS OUTPUTS

Y3 Y2 Y1 Y0 A0 A1 V

0 0 0 1 0 0 1

0 0 1 x 0 1 1

0 1 x x 1 0 1

1 x x x 1 1 1

0 0 0 0 x x 0

1 1 1 1

1 1 1 1

1 1 1 1

x 1 1

1 1 1 1

1 1 1 1

K MAP SIMPLIFICATION
A0 A1
Y1Y0 Y1Y0
00 01 11 10 00 01 11 10
Y3Y2 Y3Y2

00 00

01 01
00

11 11
 Y1Y0 V
00 01 11 A1=Y1Y2
10
Y3Y2
1 1 1
00

1 1 1 1
01

1 1 1 1
11

1 1 1 1
10

LOGIC EXPRESSION
A0=∑(2,3)

=∑( Y3'Y2+Y3)

=∑(Y3+Y2)

A1=∑(1,3)

=∑( Y3' Y2'Y1+Y3)

=∑( Y2'Y1+Y3)

V =∑( Y3' Y2' Y1'Y0+ Y3' Y2'Y1+ Y3'Y2+Y3)

00
=∑( Y3' Y2' Y1'Y0+ Y3' Y2'Y1+ Y2+Y3)

=∑( Y3' Y2' Y1'Y0+ Y1+ Y2+Y3)

=∑( Y0+ Y1+ Y2+Y3)

PRIORITY ENCODER LOGIC

 A0

u
w A1

4:2 PRIORITY ENCODER OUTPUT

 PRIORITY ENCODER

AIM

To Design and implement a priority encoder using Xilinx tool and verify the truth table and logic gates

SOFTWARE REQUIRED

Xilinx ISE Design Suite v14.7

THEORY

A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number

of outputs. The output of a priority encoder is the binary representation of the original number starting from
zero of the most significant input bit. They are often used to control interrupt requests by acting on the
highest priority interrupt input.The 4:2 priorityencoder has 2^N input lines ,one status pin V which is 0
when all inputs are 0’s else 1 for all.It has two output lines A0,A1 with input lines Y0,Y1,Y2,Y3.

A0=Y3+Y2 A1=Y1 Y2'+Y3 V=Y3+Y2+Y1+Y0

APPLICATIONS

 Priority encoders can be used to reduce the number of wires needed in a particular circuits or
application that have multiple inputs
  In magnetic positional control as used on ships navigation or for robotic arm positioning 
 Some priority encoders  include detecting interrupts in microprocessor applications to allow
peripheral devices such as the disk drive, scanner, mouse, or printer to communicate with it
SOURCE CODE

module priorityenc(input [3:0]Y,output [1:0]A,output V);

wire u,w;

not G1(u,Y[2]);

and G2(w,u,Y[1]);

or G3(A[0],Y[3],Y[2]);

or G4(A[1],Y[3],w);

or G5(V,Y[3],Y[2],Y[1],Y[0]);

endmodule

RESULT

Thus the design and implementation of priority encoder has been successfully done using Xilinx tool
and truth table ,logic gates are verified