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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1

Time-Interleaved and Circuit-Shared Dual-Channel

10 b 200 MS/s 0.18 µm CMOS
Analog-to-Digital Convertor
Hyo-Jin Kim, Tai-Ji An, Sung-Meen Myung, Student Member, IEEE, and Seung-Hoon Lee, Member, IEEE

Abstract— This paper proposes a 10 b 200 MS/s pipeline

analog-to-digital convertor (ADC) for high-quality video systems
based on double-channel and op-amp sharing schemes to min-
imize power consumption and channel mismatch. The double
channel time-interleaved scheme reduces the required operating
speed of amplifiers in the sample-and-hold amplifier and multi-
plying digital-to-analog (D/A) converters by 50%. The switched
and shared op-amp with two input pairs amplifies each channel
signal without extra series switches while minimizing the gain,
bandwidth and offset mismatches between channels. The low-
jitter sampling clock with a 50% duty cycle improves the dynamic
performance of the wideband input signals significantly. The
Flash ADCs employ a differential difference amplifier type pre-
amp to continuously process dual-channel outputs. The prototype
ADC in a 0.18 µm CMOS technology demonstrates the measured
differential nonlinearity and integral nonlinearity within 0.62 and
0.99 LSB, respectively. At 200 MS/s, the ADC shows a maximum
Fig. 1. Video signal chain of an HDTV system.
SNDR of 52.8 dB and a maximum SFDR of 60.4 dB. The ADC
with an active die area of 1.28 mm2 consumes 54.0 mW at
1.8 V.
Index Terms— Analog-to-digital converter (ADC), channel mis- at a sampling rate exceeding 165 MS/s for low jitter, high
match, circuit sharing, dualchannel, pipeline, time-interleaved. image quality, and wide enough bandwidth. In addition, the
ADCs in the video decoder require a 10 b resolution to digitize
I. I NTRODUCTION video analog inputs such as Pr, Y, and Pb into Cr, Y, and Cb.
The video signal Y is a brightness portion while the Pr and

H IGH-DEFINITION televisions (HDTVs) offer a vastly

improved quality compared with the existing signal stan-
dards such as National Television System Committee, Phase-
Alternating Line, and Sequential Color with Memory. Two
commonly employed HDTV systems, 720p and 1080i of the
progressive and interlaced scanning types, respectively, ensure
at least five times improvement of quality compared to the
conventional analog approaches. Recently, with the increas-
ing demand for high-quality imaging systems, the required
specifications for the system analog front ends (AFEs) have
become more and more strict and thus the analog-to-digital
converter (ADC) is one of the most critical building blocks.
The typical video signal chain of an HDTV system is
illustrated in Fig. 1. The ADC in front of the main signal
processor needs 8–10 effective number of bits while operating
Manuscript received April 27, 2012; revised October 3, 2012; accepted
November 6, 2012. This work was supported in part by the IDEC of KAIST,
the Ministry of Knowledge, Economy, Korea, under the University ITRC
Program NIPA-2012-H0301-12-1007 supervised by the National IT Industry
Promotion Agency, and the Basic Science Research Program of the National
Research Foundation funded by the Ministry of Education, Science and
Technology under Grant 2012-000-2297.
The authors are with the Department of Electronic Engineering, Sogang
University, Seoul 121-742, Korea (e-mail: hoonlee@sogang.ac.kr).
Digital Object Identifier 10.1109/TVLSI.2012.2229305
1063–8210/$31.00 © 2013 IEEE
Pb are color-difference portions of the signal.
ADC applications requiring a high sampling rate of sev-
eral hundreds MS/s have been typically based on Flash,
folding, sub-ranging, and pipeline architectures. Considering
10 b resolution and low power simultaneously with the high
sampling rate, the pipeline architecture has been primarily
employed [1]–[5]. On the other hand, inventive calibration
schemes in the digital domain have been proposed to reduce
power consumption of high-performance ADCs; however,
those schemes require additional circuits to remove nonlinear
errors in the digital domain [6]. Another method to implement
low power consumption with enhanced conversion speed is
to employ multi-channel time-interleaved (T-I) techniques [7].
Unfortunately, the overall ADC performance based on T-I
techniques tends to be degraded due to inherent mismatches
between parallel channels such as the gain, bandwidth, timing,
and offset differences of amplifiers in each channel with the
somewhat increased chip area.
This paper proposes a 10 b 200 MS/s CMOS pipeline
ADC based on double-channel time-interleaving and op-amp
sharing techniques to improve the performance of conventional
T-I ADCs. In a single-channel 200 MS/s pipeline ADC,
each op-amp of the input sample-and-hold amplifier (SHA)
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2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 2. Proposed 10 b 200 MS/s 0.18 µm CMOS ADC.
and multiplying D/A converters (MDACs) amplifies a residue
voltage only during a half clock period. However, the pro-
posed double-channel ADC sharing an op-amp amplifies a
residue voltage continuously during a full clock cycle of
200 MHz only with the op-amp specifications for 100 MS/s
operation. The halved number of residue op-amps and the
reduced operating requirements, such as bandwidth and power
dissipation, of the switched and shared op-amp improve the
chip area and power efficiency of the ADC significantly. In
addition, the shared op-amp minimizes the gain, bandwidth,
and offset mismatches, which are observed in conventional
T-I ADCs, between the amplifiers in the sub-ADC of each
channel. Three 4 b sub-ranging Flash ADCs employ the
comparators based on a single shared pre-amplifier (pre-amp)
and two interpolated dynamic latches alternately to handle
the outputs from two separate channels. The proposed low-
jitter input sampling clock removes a sampling-time mismatch
between two channels. The overall architecture and operation
scheme of the proposed ADC are described in Section II while
detailed circuit implementation is discussed in Section III. The
measured results of the prototype ADC are summarized in
Section IV and the conclusion is given in Section V.
II. P ROPOSED ADC A RCHITECTURE
The proposed double-channel op-amp shared 10 b 200 MS/s
three-stage pipeline ADC as shown in Fig. 2 consists of
an input SHA, two 4 b MDACs, three 4 b Flash ADCs
(FLASH1, 2, and 3), a digital correction logic (DCL) block
with multiplexer and decimator, a clock generator, and on-chip
current and voltage (I/V) references.
The proposed T-I ADC has two channels of a 100 MS/s
sub-ADC ultimately to achieve a sampling rate of 200 MS/s.
Each input stage of the SHA and MDACs consists of two
signal channels, X and Y, sharing a single op-amp. The
comparators in the three Flash ADCs are composed of two
latches, LATCH-X and LATCH-Y, with a shared pre-amp to
properly process the time-interleaving outputs of the SHA
and MDACs. A differential difference amplifier (DDA) is
employed as the shared pre-amp to continuously compare the
outputs of the SHA and MDACs with the pre-defined reference
voltages, decreasing the required number of pre-amps by half.
Fig. 3. Timing diagram for the proposed ADC.
A clock phase of 100 MHz for the SHA, MDACs, and Flash
ADCs, and a clock phase of 200 MHz for the DCL are
internally generated from a single external 200 MHz master
clock, CK. This is shown in the timing diagram of Fig. 3,
where the detailed behavior of each functional circuit block
during each clock timing is described.
As observed in Fig. 3, the capacitors in the SHA and
MDACs sample analog inputs alternately during both high and
low intervals of each clock, operating at 100 MS/s for the two
parallel channels, X and Y. Each shared and switched amplifier
continuously operates during the entire time interval while the
amplified outputs are obtained at a full rate of 200 MS/s. Two
latches, LATCH-X and LATCH-Y, in each Flash ADC process
the pre-amp outputs at 200 MS/s alternately. The final 10 b
output is obtained at a rate of 200 MS/s in the DCL using the
raw 12 b from the three Flash ADCs.
III. C IRCUIT I MPLEMENTATION
A. Double-Channel and Op-Amp Sharing Techniques for Low
Power in the SHA and MDACs
Most of the power in conventional high-sampling rate, high-
resolution pipeline ADCs is dissipated in the amplifiers of
the SHA and MDACs. While digital calibration techniques
can greatly alleviate amplifier requirements, such as power
dissipation, the supplementary circuits tend to make a single
chip integration considerably complex [8]–[10]. The proposed
ADC does not employ extra accuracy enhancement circuits for
various single-chip applications, while double-channel time-
interleaving and op-amp sharing techniques greatly reduce the
power dissipation of the overall ADC.
The proposed SHA, sharing a two-stage amplifier for two
separate input channels, is illustrated in Fig. 4 with the
related clocks. Each input channel consists of sampling capac-
itors, CS-X and CS-Y, with gate-bootstrapped input sampling
switches to obtain a signal-independent on-resistance for high
accuracy and low distortion. The SHA samples analog inputs
on the capacitors, CS-X and CS-Y, alternately, with two
nonoverlapped clocks of 100 MHz, Q2s and Q1s, as shown
in Fig. 3. The shared two-stage op-amp holds the sampled
input on CS-X and CS-Y with Q1s and Q2s high, respectively.
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KIM et al.: TIME-INTERLEAVED AND CIRCUIT-SHARED DUAL-CHANNEL 10 b 200 MS/s 0.18 µm CMOS ADC 3

Fig. 5. MDAC1 based on double-channel and op-amp sharing techniques.

Fig. 4. SHA based on double-channel and op-amp sharing techniques.

TABLE I
P OWER C ONSUMPTION OF THE T HREE T YPES OF SHA

Power
Structure
Consumption (mW)
SHA for a single-channel 200 MS/s ADC 17.2
Two SHAs for a dual-channel TI 100 MS/s
16.3
ADC
SHA for the proposed ADC 8.4

The shared op-amp samples and holds the inputs during the
full 100 MHz clock period alternately while the held outputs
are effective at a rate of 200 MS/s.
As a result, the required bandwidth and power dissipation
for the amplifier of the proposed ADC are approximately
a half of those for a single-channel 200 MS/s ADC or
for a dual-channel T-I 100 MS/s ADC, as summarized in
Table I.
The same double-channel and op-amp sharing techniques
are employed in the MDAC1 and MDAC2 of Fig. 2. Two input
channels of the MDAC1 consist of two separate capacitor-
array banks, CBANK-X and CBANK-Y, with a shared op-amp
as shown in Fig. 5. The operation of the MDAC1 is detailed
in Fig. 6.
During clock phase Q1s, the CBANK-X capacitors sample
the output of the X-channel SHA while the shared two-stage
op-amp amplifies a residue voltage, which is the difference
of the sampled input on the CBANK-Y capacitors and the
reconstructed voltage corresponding to the thermometer code
from the Y-channel FLASH1. In contrast, during Q2s, the
shared amplifier amplifies a residue voltage generated by the
CBANK-X capacitors while the CBANK-Y capacitors sample
the output of the Y-channel SHA. As a result, the shared op-
amp operates for a full clock cycle.
The amplifiers of the SHA and MDACs in conventional
pipeline ADCs use only a half of a full sampling clock cycle
for amplification in a complementary fashion. If the sub-ADC
in each channel of a dual-channel T-I ADC employs a separate
amplifier operating at a half sampling rate in a complementary
fashion, the amplifier can dissipate undesired high power
Fig. 6. MDAC1 operation at each clock phase.
with a large chip area during a nonamplifying mode. How-
ever, the proposed double-channel time-interleaving scheme
is continuously processing dual-channel inputs based on a
shared single amplifier, regardless of the sampling rate. As
a result, the shared single op-amp improves the power and
area efficiency while minimizing the gain, offset, and band-
width mismatches. The amplifier and capacitor mismatches
are reduced furthermore with 3-D fully symmetrical layout
techniques without any calibration [11]. Although the shared
op-amp scheme has various merits, a memory effect due to
the nonreset input nodes of the shared op-amp may degrade
the ADC performance [12]. The proposed op-amp, as shown
in Fig. 6, employs two separate input differential pairs [13]
and the input summing nodes of the deactivated differential
pair are reset to the signal common to remove the memory
effect.
The amplifiers in the SHA and MDACs employ a two-stage
op-amp to meet the gain and bandwidth requirements for a
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4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Fig. 7. Two-stage op-amp for the SHA.
10 b resolution at a sampling rate of 200 MS/s. The shared
op-amp with two separate input pairs for the SHA is illustrated
in Fig. 7. The first-stage op-amp, AMP1, is based on a folded
cascode topology while a common-source topology is selected
for the second-stage op-amp to achieve the required high DC
gain and wide output swing range. Two MOS switches steering
the bias current of the AMP1 are turned on and off alternately
with slightly overlapped clock phases, Q2Bs and Q1Bs, rather
than typical nonoverlapped Q1s and Q2s, in order to reduce
the glitch noise of the AMP1 during switching operation.
The cascode compensation capacitor, connected to a low-
impedance cascode node of the AMP1, achieves a required
bandwidth and phase margin for a stable signal, settling at an
operating speed of 100 MHz [14]. The shared op-amp for the
MDAC1 and MDAC2 is similar to that for the SHA except
that the first-stage amplifier has a telescopic topology rather
than a folded cascode to further reduce power dissipation.
The location of a dominant pole derived from the cascode
and Miller compensation is almost the same, whereas the non-
dominant second pole of the cascode compensation is located
at a higher frequency region than the Miller compensation
[14]. Therefore, the SHA with a relatively large capacitive load
employs the cascode compensation, which has a high phase
margin with less power compared to the Miller compensation.
In contrast, the MDACs prefer the Miller compensation, which
is more convenient to meet the required bandwidth and phase
margin. The compensation capacitors used in the SHA and
MDAC1 are 1.2 pF and 200 fF, respectively. The amplifiers
of the SHA and MDAC1 have a DC gain of 80 dB and a
bandwidth of 350 MHz to meet the required settling time.
The power consumption of the SHA and MDAC1 is 8.5 and
7.0 mW, respectively.
B. Shared Pre-Amp for Two Channels in the Flash ADCs
Each comparator in the three Flash ADCs (FLASH1, 2
and 3) consists of a shared pre-amp based on the DDA
topology and on the two latches, LATCH-X and LATCH-Y, to
sequentially operate at a 100 MHz clock, as shown in Fig. 8.
The shared pre-amp continuously compares and amplifies
the difference of the pre-defined differential reference voltage
and the differential analog signal from each channel of the
SHA and MDACs without any switching clock operation.
Fig. 8. Shared pre-amp with two latches alternately operating.
The amplified output of the pre-amp is expressed in (1) [15]
TP − TN = A0 × [(INP − INN) − (REFT − REFC)]
(A0 : DC gain of the DDA). (1)
Since the comparator employs a shared pre-amp instead
of two exclusively used pre-amps for two separate channels
of the SHA or MDACs, the required number of pre-amps is
reduced by half. Thus, the loads of the SHA and MDACs
as well as the chip area and power dissipation for pre-amps
are reduced considerably. Moreover, a well-known interpola-
tion technique implemented in the Flash ADCs additionally
halves the required number of pre-amps with the related
chip area and power dissipation. A single resistor ladder is
also shared between the FLASH2 and FLASH3 to reduce
the chip area and linearity degradation of the overall ADC
caused by a difference of reference voltages for the two Flash
ADCs [16].
C. Proposed Input Sampling Clock with a 50% Duty Cycle for
Reduced Sampling-Time Mismatch
Besides the DC gain and bandwidth mismatches of the op-
amp among channels, the performance of T-I ADCs tends to be
degraded by a sampling-time mismatch due to the nonuniform
input sampling of the sub-ADC in each channel. In conven-
tional T-I ADCs, the sampling-time mismatch is commonly
caused by the parasitic load difference and logic gate-delay
mismatch of an input sampling clock generator [17]. The
mismatch effect is getting worse as input frequencies are
increasing [18], [19]. Sometimes, the performance degradation
due to the sampling-time mismatch can be prevented by
employing the additional circuit such as a delay locked loop
(DLL) [20]. However, it is still difficult to design the DLL
properly because of the process, voltage, and temperature
(PVT) variations [21].
In this paper, the proposed ADC minimizes the sampling-
time mismatch by integrating a low-jitter input sampling
clock generator just next to the SHA, as shown in Fig. 9.
The proposed low-jitter clock generator is composed of only
simple logic circuits, which are insensitive to PVT variations.
Moreover, a delay control circuit is additionally integrated
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KIM et al.: TIME-INTERLEAVED AND CIRCUIT-SHARED DUAL-CHANNEL 10 b 200 MS/s 0.18 µm CMOS ADC 5

Fig. 9. Clock generator minimizing a sampling-time mismatch.

Fig. 10. Die photograph of the prototype ADC.

and manually adjusted with external digital control pins to
get more stable input sampling phase margins, which are not
heavily critical to RC delay time variations.
Two very critical input sampling clocks, QXs and QYs,
are synchronized with the falling edge of a 200 MHz clock,
Q2, to sample uniformly the input signals from two separate
channels. When the input sampling clocks are generated only
by Q2 and QBs (or Qs), the duty cycle of the input sampling
clocks becomes 25% of the 100 MHz clock, reducing the
input sampling time. The duty cycle of QXs and QYs can
be increased up to 50% with an extra clock of Q1PBs (or
Q2PBs) [20].
In the proposed clock generator, only after QBs (or Qs)
changes from high to low, the reference clock, Q2, changes
from high to low. As a result, two input sampling clocks
of each channel, QXs and QYs, precisely are synchronized Fig. 11. Measured DNL and INL of the prototype ADC.
with the falling edge of Q2. However, a small difference of
the parasitic loads and logic gate delays in the 4-phase and
8-phase clock generators of Fig. 9 can affect a serious delay- blocks, Electromagnetic interference problems, power noise,
time variation between the 200 MHz and 100 MHz clocks. and transient glitches.
When the reference clock, Q2, changes earlier than QBs (or The accurate performance evaluation of high-speed ADCs
Qs), the generated input sampling clocks are not synchronized with a sampling rate exceeding 100 MS/s is usually very
with the falling edge of Q2. In contrast, when Q2 changes difficult due to nonideal measurement environments, such
later than Q2Bs (or Q1Bs) to drive the gate-bootstrapped input as the ground bouncing noise from a printed circuit board.
sampling switches in the SHA, the related charge feed-through The prototype ADC captures 10 b digital outputs from two
effect may cause undesired signal distortion. Therefore, the channels separately at a sampling rate of 100 MS/s with on-
proposed clock generator adds an extra delay control circuit chip output buffers. The original digital data are reconstructed
and prevents the problem caused by the difference of the with a simple code mixing to measure the performance of
parasitic components, as shown in the bottom center of Fig. 9. the prototype ADC as accurately as possible. The measured
The delay is controlled by a specific RC time constant and differential nonlinearity (DNL) and integral nonlinearity (INL)
comprised of four steps by using two external control pins. are within 0.62 and 0.99 LSB, respectively, as illustrated in
The delay time is adjusted in a time step of 30 ps while an Fig. 11.
adjustable maximum-delay time is 170 ps. As a result, Q2 The typical FFT spectrum of the ADC measured with an
changes within a period of tt , guaranteeing normally operating input frequency 4 MHz at 200 MS/s is plotted in Fig. 12. The
input sampling clocks. measured dynamic performance of the ADC is summarized in
Fig. 13. The signal-to-noise-and-distortion ratio (SNDR) and
IV. P ROTOTYPE M EASUREMENTS spurious-free dynamic range (SFDR) in Fig. 13 are measured
The proposed 10 b 200 MS/s ADC is implemented in a at different sampling rates from 20 to 200 MS/s with an input
0.18 µm 1P6M CMOS process. The die photo of the prototype frequency of 4 MHz. The measured SNDR and SFDR are
ADC in Fig. 10 shows an active die area of 1.28 mm2 . maintained over 52.8 and 60.4 dB up to 200 MS/s.
The integrated MOS decoupling capacitors of 400 pF in the The dynamic performance of the prototype ADC mea-
unemployed on-chip area reduce interferences between circuit sured with increasing input frequencies at a sampling rate
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6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Fig. 12. Measured FFT spectrum of the proposed ADC. (a)

(b)

Fig. 13. Measured SFDR and SNDR of the ADC depending on fs. Fig. 15. FFT spectrum of the ADC measured with a fin of 80 MHz based
on (a) conventional and (b) proposed input sampling schemes.

TABLE II
P ERFORMANCE S UMMARY OF THE P ROTOTYPE ADC

Resolution 10 bits
Conversion Rate 200 MS/s
Process 0.18 µm CMOS
Input Range 1.2 Vp-p (Differential)
Max.DNL/Max.INL 0.62 LSB/0.99 LSB
SNDR 52.8 dB (@ f in = 4 MHz)
SFDR 60.4 dB (@ f in = 4 MHz)
ADC Power Consumption 54.0 mW@1.8V
Die Area 1.28 mm2 (= 1.16 mm × 1.10 mm)
Fig. 14. Measured SFDR and SNDR of the ADC depending on a fin at
200 MS/s.

of 200 MS/s is illustrated in Fig. 14. Using the conventional
input sampling scheme in Fig. 9 without a low-jitter SHA
sampling clock generator and a delay control circuit, the SFDR
and SNDR performances are degraded due to the sampling-
time mismatch. However, using the input sampling scheme
with a 50% duty cycle, as proposed in Fig. 9, the SNDR
and SFDR at the Nyquist input frequency are measured to
be 49.5 and 57.2 dB, respectively. The prototype ADC with
the proposed input sampling scheme shows the considerably
improved dynamic performance compared to the ADC based
on the conventional input sampling scheme.
The FFT spectrum of the conventional input sampling
scheme is compared to the proposed input sampling scheme,
as shown in Fig. 15(a) and (b). The harmonic component at
[fs/2 - fin], indicated with the dotted circle, is mostly gen-
erated by the sampling-time mismatch of each channel [22].
The sampling-time mismatch effect of the conventional ADC
is improved greatly in the proposed ADC, as observed in
Fig. 15(a) and (b).
The performance of the prototype ADC is summarized in
Table II. The performance of the prototype ADC is com-
pared with the up-to-date reported various CMOS ADCs at
a 10 b resolution and a sampling rate exceeding 200 MS/s,
as shown in Table III. The figure of merit (FoM), defined
as (2), of the prototype ADC is 1.11 pJ/conversion-step,
including the power consumption of the on-chip reference
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KIM et al.: TIME-INTERLEAVED AND CIRCUIT-SHARED DUAL-CHANNEL 10 b 200 MS/s 0.18 µm CMOS ADC 7

TABLE III
P ERFORMANCE C OMPARISON OF R ECENTLY R EPORTED 10 b CMOS ADC S AT S AMPLING R ATE H IGHER T HAN 200 MS/ S

Speed Supply Power Area DNL/INL On-Chip Process FoM

(MS/s) (V) (mW) (mm2 ) (LSB) I/V Ref. (CMOS) (pJ/Conv.)
This Work 200 1.8 54.0 1.28 0.6/1.0 O 0.18 µm 1.11
[23] 200 1.0 5.4 0.19 0.4/1.4 O 65 nm 0.06
[1] 200 1.2 104.0 4.90 0.6/0.8 O 0.13 µm 2.08
[24] 200 1.8 128.0 0.79 0.6/1.1 X 0.18 µm –
[25] 204 1.0 9.2 0.22 0.7/0.9 O 65 nm 0.16
[4] 205 1.0 111.0 1.00 0.5/0.5 O 90 nm 1.74
[5] 205 1.2 92.5 0.52 0.2/0.6 X 0.13 µm 0.38
[26] 210 1.2 52.0 0.38 0.6/1.4 X 0.13 µm 0.80

generator. Although the prototype ADC is implemented
in a 0.18 µm CMOS process, it shows somewhat bet-
ter power efficiency than the ADCs in deep sub-micron
technologies:
Power
FoM = ENOB . (2)
2 × 2ERBW
V. C ONCLUSION
This paper proposed a double-channel 10 b 200 MS/s
0.18 µm CMOS pipeline ADC based on time-interleaving and
op-amp sharing techniques to minimize power dissipation and
channel mismatch. The dual-channel time-interleaved scheme
reduced the required operating speed of amplifiers in the
SHA and MDACs by half. The switched and shared op-
amp with two differential input pairs amplified each channel
signal without extra series switches and memory effects, while
the shared op-amp minimized the gain, offset and bandwidth
mismatches that are usually observed in the conventional dual-
channel ADCs using separate amplifiers for each channel.
The Flash ADCs employed a DDA type shared pre-amp with
two latches to continuously process the dual-channel outputs
from the SHA and MDACs. The conventional sampling-time
mismatch, which was caused by parasitic load and logic gate-
delay mismatches in a clock generator, was reduced by the
proposed low-jitter input sampling clock. The prototype ADC
implemented in a 0.18 µm CMOS technology occupied an
active area of 1.28 mm2 and the measured DNL and INL
were within 0.62 and 0.99 LSB, respectively. At 200 MS/s,
the prototype ADC demonstrates a maximum measured SNDR
of 52.8 dB and a maximum SFDR of 60.4 dB, consuming
54.0 mW at a 1.8 V supply voltage.
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[13] K. H. Lee, S. W. Lee, Y. J. Kim, K. S. Kim, and S. H. Lee, “Ten-bit
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 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

[19] S. Gupta, M. Choi, M. Inerfield, and J. Wang, “A 1 GS/s 11 b time- Tai-Ji An received the B.S. degree in electronic
interleaved ADC in 0.13 µm CMOS,” in IEEE Int. Solid-State Circuits engineering from the University of Seoul, Seoul,
Conf., Dig. Tech. Papers, Feb. 2006, pp. 264–265. Korea, in 2007. He is currently pursuing the M.S.
[20] S. C. Lee, K. D. Kim, J. K. Kwon, J. D. Kim, and S. H. Lee, “A 10 bit degree in electronic engineering with Sogang Uni-
400 MS/s 160 mW 0.13 µm CMOS dual-channel pipeline ADC without versity, Seoul.
channel mismatch calibration,” IEEE J. Solid-State Circuits, vol. 41, He was with Luxen Technologies, Seoul, from
no. 7, pp. 1596–1605, Jul. 2006. 2007 to 2011. His current research interests include
[21] V. Karutharaja, M. Bhaskar, and B. Venkataramani, “Synchronization of design of high-resolution low-power CMOS data
on-chip serial interconnect transceivers using delay locked loop (DLL),” converts, PMICs, and very high-speed mixed-mode
in Proc. Int. Conf., Signal Process., Commun., Comput. Netw. Technol., integrated systems.
Jul. 2011, pp. 213–216.
[22] N. Kurosawa, H. Kobayashi, H. Sugawara, and K. Kobayashi, “Explicit
analysis of channel mismatch effects in time-interleaved ADC systems,”
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, Sung-Meen Myung (S’11) received the B.S. and
pp. 261–271, Mar. 2001. M.S. degrees in electronic engineering from Sogang
[23] Y. Chai and J. T. Wu, “A 5.37 mW 10 b 200 MS/s dual-path pipelined University, Seoul, Korea, in 2010 and in 2012,
ADC,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, respectively.
Feb. 2012, pp. 462–464. He has been with the Display Driver Solution
Team, Brand Business Division, Dongbu HiTek Co.,
[24] T. Nezuka, K. Misawa, J. Azami, Y. Majima, and J. Okamura, “A 10-bit
Ltd., Seoul, since 2012. His current research inter-
200 MS/s pipeline A/D converter for high-speed video signal digitizer,”
ests include analog IC design for TFT-LCD drivers
in Proc. IEEE Asian Solid-State Conf., Nov. 2006, pp. 459–463.
and very high-speed mixed-mode integrated systems.
[25] Y. D. Jeon, Y. K. Cho, J. W. Nam, K. D. Kim, W. Y. Lee, K. T. Hong,
and J. K. Kwon, “A 9.15 mW 0.22 mm2 10 b 204 MS/s pipelined SAR
ADC in 65 nm CMOS,” in Proc. IEEE Custom Integr. Circuits Conf.,
Sep. 2010, pp. 19–22.
[26] Z. Cao and S. Yan, “A 52 mW 10 b 210 MS/s two-step ADC for digital- Seung-Hoon Lee (M’91) received the B.S. and M.S.
IF receivers in 0.13 µm CMOS,” in Proc. IEEE Custom Integr. Circuits degrees (Hons.) in electronic engineering from Seoul
Conf., Sep. 2008, pp. 309–312. National University, Seoul, Korea, in 1984 and in
1986, respectively, and the Ph.D. degree in electrical
and computer engineering from the University of
Illinois, Urbana-Champaign, in 1991.
He was with Analog Devices Semiconductor,
Wilmington, MA, from 1990 to 1993, as a Senior
Design Engineer. Since 1993, he has been with
the Department of Electronic Engineering, Sogang
University, Seoul, where he is currently a Professor.
His current research interests include design and testing of high-resolution
high-speed CMOS data converters, CMOS communication circuits, integrated
Hyo-Jin Kim received the B.S. degree in electronic
sensors, and mixed-mode integrated systems.
engineering from Suwon University, Suwon, Korea,
Dr. Lee is a member of the editorial board and the technical program
in 2011. She is currently pursuing the M.S. degree in
committee of many international and domestic journals and conferences
electronic engineering of Sogang University, Seoul,
including the IEEK Journal of Semiconductor Devices, Circuits, and Systems,
Korea.
and the IEICE T RANSACTIONS ON E LECTRONICS , and the IEEE Symposium
Her current research interests include design of
on VLSI Circuits. Since 2006, he has been organizing various industry-
high-resolution low-power CMOS data converters
university cooperative programs with many companies such as Samsung
and very high-speed mixed-mode integrated systems.
Electronics, SK Hynix Semiconductor, and LG Electronics. In 2010, he
founded Analog IP Research Center supported by the Ministry of Knowledge
and Economy, Korea.