Analog Integrated Circuits and Signal Processing

https://doi.org/10.1007/s10470-019-01389-y (0123456789().,-volV)
(0123456789().,-volV)

A 12bit 250MSPS pipeline ADC with 4 Gbps serial output interface

H. J. Wu1 • Z. H. Chen1,2 • Z. G. Yu1 • H. C. Ji1 • Y. P. Zeng1

Received: 13 November 2017 / Revised: 7 November 2018 / Accepted: 6 January 2019

Ó Springer Science+Business Media, LLC, part of Springer Nature 2019

Abstract
A 12bit 250MSPS pipeline analog-to-digital converter (ADC) with serial output interface is presented. The pseudo random
digital calibration dithered sub-ADC in first stage is used to lower non-ideal errors and improve the dynamic performance
in the high speed ADC. An integrated serial output interface is implemented to convert 12bit parallel data into a differential
serial data stream. The pipeline ADC was fabricated with CMOS 180 nm 1.8 V 1P5 M process. The active ADC with the
serial output interface consumes a power consumption of 395 mW and occupies an area of 8.0 mm2, where the active area
of the interface is 0.75 mm2. The measurement results show that the differential non-linearity and integral non-linearity of
the proposed ADC are - 0.22/? 0.16LSB and - 0.4/? 0.6LSB, respectively. The spurious free dynamic range and signal-
to-noise ratio can get 81.17 dB and 69.92 dB with 20 MHz input signal at full sampling speed. The serial output interface
provides an eye height greater than 800 mV for data rates of 4 GHz bits per second with a power of 75 mW.

Keywords Pipeline  ADC  Pseudo random  PLL  Interface

1 Introduction amplifier (op-amp) gain, capacitor mismatch and settling

Pipeline ADCs with the sampling frequency of over
200 MHz are widely used in broadband communication
receivers, radar subsystems and wireless infrastructures for
IF sampling.
With the rapid increase of data processing rate, the
digital output rate from pipeline ADC has increased from
MHz to GHz. In order to speed up the digital outputs rates
and minimize the output pins, serial low voltage differen-
tial signaling (LVDS) interface is widely used to provide
output rates from 100 MHz to 5 GHz in high speed ADC
[1–4].
The digital pseudo-random (PN) calibration algorithm
used for the main pipeline stages is used to minimize the
non-ideal errors and improve the dynamic performance
[5–8]. The accuracy of switched-capacitor circuits in
pipeline ADC is limited mainly by finite operational
error. The speed of the pipeline ADC is limited mainly by
the bandwidth of op-amp. PN modulated sub-stage circuit
is normally injected a known but random amount of noise
to the sub-DAC or sub-ADC. The pseudo random cali-
bration of sub-ADC will not affect the dynamic input range
of stage compared with the PN calibration in the multi-
plying digital to analog converter (MDAC). Injecting PN
signal at the input of the sub-ADC is easier to achieve high
speed with no change to the MDAC, which is the most
critical and sensitive block in the pipeline ADC. Thus, the
PN calibration in sub-ADC is proposed in this design.
In this paper, a 12-bit 250MSPS pipeline ADC with a
4G bps serial interface is presented. Section 2 describes the
ADC’s architecture with pseudo-random (PN) calibration
and details the CMOS designs of the serial interface blocks.
Section 3 presents the measured results, and Sect. 4 draws
the main conclusions.

& Z. H. Chen 2 Circuit design

diaoyuds@126.com
1
No.58 Research Institute, China Electronic Technology The block diagram of the proposed ADC is illustrated in
Group Corporation, Wuxi 214035, China Fig. 1. The ADC core is composed of a high-speed low-
2
College of Electronic Engineering, Huangshan University, distortion sample and hold circuit, a 4.5-bit first stage, 3
Huangshan 242700, China consecutive 2.5-bit sub-stages and a final 3-bit sub-Flash

123

Fig. 1 Block diagram of the
proposed pipeline ADC
INP
SH
SHA
A Stage1
INN
Voltage
Reference
Generator
250MHz
CLKP
Receiver
CLKN Clk generation
ADC. Besides, differential clock receiver was used to
minimize the clock jitter noise. The pipelined stage circuits
are implemented in switched capacitor scheme. The 41bits
thermometer code from the five pipelined sub-stages is
aligned by Delay Array and encoded by the Digital Cor-
rection Logic and gets the 12bit parallel digital conversion
code. The parallel 12bit digital output codes are transported
to the 4 Gbps serial output interface in order to minimize
the pin numbers and improve the digital signal speed.
As a non-overlapping multi-phase clock signal with
250 MHz frequency is used for the ADC core, a clock
input receiver is used to receive the differential input clock,
and the distributed clock generation and buffer system is
selected to transmit the on-chip non-overlapping clocks. A
fully integrated 2 GHz PLL is designed for generating the
serializing clock for the 4 Gbps serial interface, without
any external component. In order to provide precision
voltage reference with fast settling, an on-chip precision
bandgap reference voltage generator and buffer amplifiers
are also integrated on the chip.
2.1 PN calibration technique in sub-ADC
The first PN calibrated 4.5-bit stage circuit is showed in
Fig. 2(a); the detailed structure of 4.5-bit dithered sub-
ADC is illustrated in Fig. 2(b). The stage circuit is con-
sisted of a 4.5-bit dithered sub-ADC, a traditional 4.5-bit
sub-DAC, a 4.5-bit thermometer to binary code encoder, a
MDAC with the gain of 16 and the PN generator. The 4.5-
bit dithered sub-ADC compares the analog input signal Vi
with PN modulated voltage references and gets the 16-bit
thermometer code. The 16-bit thermometer code is enco-
ded by the 4.5-bit encoder and gets the 5-bit binary code.
The MDAC used in this 4.5-bit sub-stage circuit is
implemented by traditional switched capacitor MDAC
scheme, which consumes major current to achieve accurate
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Analog Integrated Circuits and Signal Processing
4.5-Bit 2.5-Bit 2.5-Bit 3-Bit
2.5-Bit
Stage2 Stage3 Stage4 Flash
16 6 6 6 7
Delay Array and Digital Correction Logic
D[0:11]
2GHz 2GHz 4Gbps Serial Output Interface
PLL
Dout- Dout+
gain and high bandwidth. The Fig. 2(b) gives the structure
of the 4.5-bit dithered sub-ADC. There are 16 dynamic
comparators used in this sub-ADC. The dynamic com-
parator is implemented by commonly used common mode
insensitive switched capacitor multi-stage latched com-
parator. The left reference voltage of Refn1 to Refn16 and
right reference voltage of Refp1 to Refp16 are generated by
resistor array from band-gap signal. The PN1 to PN16 signal
is generated by PN circuit. The sequence of control
switches is random and not repetitive. The left control
signal PN1–16 is same with right control signal. The PN
noise is injected in the voltage references by randomly
varying the comparator threshold level, which is realized
by randomly selecting the reference control switches PN1
to PN16. Thus, the PN signal is injected to input end of sub-
ADC by the dithering reference voltage.
The block diagram of the PN calibration algorithm in
sub-ADC is illustrated in Fig. 3. The PN signal is injected
into the input end of the sub ADC, which is actually
equivalent to adjusting the threshold voltage of the com-
parator according to the PN sequence to change the output
encoding of the sub-ADC.
In the sub ADC, the pseudo random sequence signal can
be illustrated as PN  Vcal . The PN modulation is actually
changed the comparator threshold voltage in the sub-ADC,
which makes the output signal of the corresponding stage
change with random margin in the threshold of the com-
parator. The Output Dsub of sub-ADC is illustrated as:
Dsub ¼ Vin =Vref þ PN  Vcal =Vref þ QS ð1Þ
where QS is the quantization error of sub-ADC, the output
of the back-end ADC is:
Dout ¼ GðPN  Vcal þ QS Vref ÞVref þ Qb ð2Þ
where Qb is the quantization error of the back-end ADC,
the expectation value of D0out is:
Analog Integrated Circuits and Signal Processing

Fig. 2 The first 4.5-bit stage (a)

circuit a PN modulated 4.5-bit
structure b 4.5-bit dithered sub-
ADC

(b)

Fig. 3 The diagram of PN

calibration algorithm in sub- Backend
ADC VIN G
VDAC ADC
Dout
PN ⋅ Vcal
Dsub
G'
sub-ADC sub-DAC
PN
Dout
'

Average

E[D0out  ¼ Ef½Dout þ Dsub  G0   PN 0 g ¼ PN PN sequence. Ideally, after calibration G is equal to G0

 PN 0 ðG0 GÞVcal =Vref
Efg is the expectation function, which is equivalent to
the mean value of the multiple output results. The error
parameters can be extracted by using the characteristic of
ð3Þ approximately. In fact, G0 will approximate to true value of
G.
The pseudo random calibration of sub-ADC will not
affect the dynamic input range of stage compared with the
PN calibration in the MDAC. Compared with injecting PN

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 Analog Integrated Circuits and Signal Processing

to the input of the sub-DAC, injecting PN at the input of
the sub-ADC is much easier to achieve high speed with
simplified system structure. First, the injected pseudo-ran-
dom noise can be compensated by the digital redundancy
of the pipeline ADC without any performance degradation.
Therefore it is unnecessary to reduce the input signal
magnitude when injecting the pseudo-random noise. Sec-
ond, we do not need to face the complication of an accurate
scaling (about 1/4 value) in the analog domain. Third, in
the circuit implementation, the injection of pseudo-random
noise can be done by randomly varying the comparator
threshold level (comparator dithering), as long as this
variation/dithering does not exceed the bounds of digital
redundancy. Finally, MDAC do not need to design dither
circuits, which is the most critical and sensitive block in the
pipeline ADC design. Thus, we can obtain faster operation
and less noise coupling from this radix detection
scheme with low power. Because of these advantages, the
PN is dithered at the input of the sub-ADC for the 4.5-bit
first stage circuit for the 12-bit pipeline ADC.
2.2 High speed operational amplifier
As a critical module used for SH and MDAC in each stage,
the operational amplifier requires careful design to meet the
requirements of the system, so as to minimize the gain and
settling error as possible.
The setting accuracy should be smaller than 1/4 least
significant bit (LSB). The voltage gain needs to satisfy the
following formula:
A  b  2Nþ2 ð4Þ
telescopic amplifier and a common-source amplifier, which
is shown in Fig. 4(a). The voltage gain of the designed op-
amp is:
Av ffi gm1 f½gm3 ro3 ro1 jjðgm5 ro5 ro7 Þg  gm9 ðro9 jjro11 Þ ð6Þ
ro is the resistor of corresponding transistor, gm is the trans-
conductance of corresponding transistor.
The transistor of MN2,3 and MP1–4 is the differential
input and load transistor. The first and second common-
mode feed-back (CMFB) is used to stabilize the common-
mode signal. A improved frequency compensation with the
capacitor of Cc2,3 is adopted in this opamp to improve the
sufficient phase margin, which is shown in Fig. 4 [9].
Because of the frequency compensation theory of Cc2
and Cc3, the small signal model of the op-amp with only
with Cc3 is shown in Fig. 5(a) for quantitative analysis.
The gmn2,3 and RI is the input trans-conductance and output
impedance of first stage; The gmn7,8 and RII is the input
trans-conductance and output impedance of first stage. CL
is the load capacitor. The gmp3,4 is the MP3 and MP4 trans-
conductance of first stage; The gmp7,8 is the MP7 and MP8
trans-conductance of first stage. Vin and Vout is small input
and output voltage, relatively. Then, the node equation of
A point is:
V1
1
g
gmn2;3  Vin þ  gmp3;4  1 mp3;4 1  Vout ¼ 0 ð6Þ
gmp3;4 þ sCc3
RI
the node equation of B point is:
!
1 1
gmn7;8  V1 þ 1 1
þ þ s  CL Vout ¼ 0 ð7Þ
gmn3;4 þ sCc3
RII

A is the gain of the op-amp, b is feedback factor, N is The transfer function is:
 
the resolution of corresponding stage in ADC. Consider gmn2;3 gmn7;8 RI RII 1 þ gCmp3;4
c3
s
Vout
some non-ideal factors, such as input parasitic capacitor, ¼  
Vin RII CL Cc3 2 Cc3
amplifier gain should be greater than ideal gain. In SH, b is gmp3;4  s þ gmp3;4 þ RII CL þ RII Cc3 þ gmp7;8 RI RII Cc3  s þ 1

1, the gain of opamp should be larger than 212 ± 2, which is ð8Þ

84 dB. In MDAC, b is 5, the ideal gain of opamp should be
larger than 5 * 212 ? 2, which is 98 dB. Besides, Process Thus, the two poles of the system can be obtained as
and Voltage and Temperature (PVT) will further deterio- follows:
rate the gain of opamp. In this design, the proposed PN 1
p1 ¼  Cc3
calibration can relax the gain requirement of opamp in þ RII CL þ RII Cc3 þ gmn7;8 RI RII Cc3
gmp3;4
MDAC. 1
The unit-gain bandwidth should be satisfied the fol-  ð9Þ
gmn7;8 RI RII Cc3
lowing formula:
gmn7;8 RI RII Cc3 gmp3;4 gmn7;8 RI
ðN þ 2Þ ln 2 p2   RII CL Cc3

fu [ ð5Þ gmp3;4
CL
2p  b  ts  0
¼ gmp3;4 RI  p2  ð10Þ
ts is the settling time with the ADC’ speed. For the sam-
pling frequency of 250 MHz, fu should be greater than From the above analytical, compensation result is sim-
2.5 GHz. ilar with Miller compensation. The dominant pole is
In order to obtain high gain, high speed and output ‘‘closed to zero’’ after adding the compensation capacitor
swing, the operational amplifier is composed of a of Cc. However, the non-dominant pole is magnified

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Analog Integrated Circuits and Signal Processing

Fig. 4 Op-amp schematic

VBP3 MP11 MP7 VBP1 MP8 VBP3

MP12
Cc3 Cc3
B
Voutp MP5
Voutn
VBP2 MP6
Cc1 RZ Cc1 RZ

CMFB1 A
Vo1 Vo2
MN9 MN10
MN3 VBP2 MN4
Cc2
Cc2
VFo1 VFo2

Vinp MN1 MN2 Vinn

VBIAS1
MN0

Voutp
FB
Voutn CMFB2 MN13

Fig. 5 Small signal model of rop3,4

the op-amp: a only with Cc3;
b simplified equivalent model (a) Cc3
A B Vout

+
V1 gmp3,4*Vs3,4
gmn2,3*Vin RI RII CL
_ gmn7,8*V1

(b) A Cc3 B Vout

+
gmn2,3*Vin gmp3,4*Vs3,4 gmn7,8*V1
V1
RI RII CL
1/gmp3,4
_

gmp3,4R1 after the compensation. Then, The compensation second stage, further lower the whole op-amp’s current.
can obtain relatively larger non-dominant pole with low Besides, The Cc3 draw into a left zero point of - gmp3,4/Cc3
gmp7,8 in the second stage. The opamp can obtain enough in the plane. The simulated gain and unit-gain bandwidth is
phase margins and obviously minimize the current of the

123

shown in Fig. 6. The gain and unit-gain bandwidth can get
85 dB and 3.28 GHz with the phase margin of 57.3.
2.3 Serial output interface
The topology of the 4 Gbps serial output interface for the
high speed ADC is shown in Fig. 7. The block is composed
of an encoder which converts the parallel 12-bit code to
64-bit code, a serializer which changes the parallel 64-bit
code to the serial packets under the clock of 2 GHz and a
current model (CM) output interface that drives the seri-
alized data stream Din to differential output of Dout ? and
Dout -.
To fulfill the design target,the data from the 12-bit ADC
is sent serially in packets of 64 bits, which consist of an
8-bit header, 48-bit data, and 8-bit error correction code
(ECC). The output data streaming of 16 9 the encode
clock is designed for the transmitter to drive the digital
output code of the 12-bit 250MSPS ADC at the data
transmission rate of 4 Gbps. A 2 GHz PLL is used for
generating the serializing clock for the 4 Gbps interface.
The differential output driver is the important part in the
interface, as it is the bottleneck of the bandwidth and
usually consumes a large part of power. The current mode
(CM) output driver is designed to obtain data rate of
4 GHz, which is shown in Fig. 8. The Vbiasp and Vbiasn are
the bias voltage to ensure the 4 mA driving current.
The R is used to reduce the voltage gain and improve the
unity-gain bandwidth. According to Kirchhoff’s law of
electric current, the following formula can obtained:
Fig. 6 Op-amp AC results
123
Analog Integrated Circuits and Signal Processing
Vin  Vout Vout Vout
 gmp  Vin  gmn  Vin    Vout  Cs
R ron rop
¼0
ð10Þ
Then, the Av of output stage can be obtained as follows:
Vout 1  ðgmp þ gmn ÞR
Av ¼ ¼   ð11Þ
Vin 1 þ R r1on þ r1op
Thus, the R can reduce the voltage gain and improve the
unity-gain bandwidth in order to get bandwidth of higher
than 4 GHz.
3 Experimental results
The 12-bit 250-MSPS ADC with 4 Gbps serial interface
has been implemented in a 0.18-lm 1.8 V 1P5 M mix-
signal CMOS process. The die photograph of the proposed
ADC is displayed in Fig. 9. The central part is the SHA
circuit and the five pipeline sub-stages, and the left side
shows reference voltage generator and buffers, the digital
error correction logic block follows the pipelined stages,
the PLL and clock buffer is in the right down of the chip
and the scramble and ECC block is in the right up of the
prototype ADC. The total die area is about 8.9 mm2, where
the active area of the pipeline ADC core is 2.52 mm2, the
die area of the PLL is 0.6 mm2, the active area of scramble
and ECC block is 0.55 mm2, and the active area of the
driver is 0.25 mm2.
Analog Integrated Circuits and Signal Processing

Fig. 7 The block diagram of 12b

interface d0 D1

Digital Correction Logic

d1

Scramble & ECC

.
. d0 D2 12b
.
d1 Dout +
d10 64b CM

12bit ADC
.
Serializer
d11 .
.
d0 D3 12b
Din Driver Dout -
d1
d10 .
d11 .
.
d0 D4 12b
d1
d10 .
d11 .
.
2GHz Clk
d10
d11

Encoder 250MHz Clk

Fig. 8 CM output driver

Vbiasp

R Dout +
Dout -
Din

Vbiasn

Fig. 11. The measured signal to noise ratio (SNR) is

Fig. 9 Die photograph of the proposed ADC
The measured non-linearity of the ADC is shown in
Fig. 10. The maximum integral non-linearity (INL) is
- 0.4/? 0.6 LSB, and the maximum differential non-lin-
earity (DNL) is - 0.22/? 0.16 LSB. The measured 32 K
point output fast Fourier transform (FFT) spectrum with
20.1 MHz input frequency at 250 MSPS is shown in
69.92 dB, the spurious free dynamic range (SFDR) is
81.17 dB, and the effective number of bits (ENOB) is
11.3bit. The measured SNR and SFDR is 67.0 dB and
78 dB with input frequency of 120 MHz, which is shown
in Fig. 12. The total ADC power consumption is about
395 mW with the supply of 1.8 V, where the power con-
sumption of the interface is about 75 mW. The power
consumption of the PLL in the interface is 35 mW.
The measured eye-diagram and the transient waveform
are shown in Fig. 13. The driver current is derived on chip
and sets the output current at each output equal to a
nominal 4 mA. A 100 X differential termination resistor is
placed at the FPGA receiver input to result in a nominal
differential 800 mV-pp swing. The eye diagram of the
digital output data under 4 Gbps is given in Fig. 13(a), we
can see that the signal swing of the interface is 800 mVpp.
The time interval error (TIE) jitter histogram is shown in
Fig. 13(b) with a peak-to-peak jitter of 70 ps.
Table 1 is the performance comparison with reported
higher than 200 MHz pipeline ADCs. The figure of merit
(FOM) of the ADC can obtain 864 fJ/step. It is

123
 Analog Integrated Circuits and Signal Processing

Fig. 10 The DNL and INL of

the proposed ADC

Fig. 11 FFT spectrum for

Fin = 20 MHz of the proposed
ADC

123
Analog Integrated Circuits and Signal Processing

demonstrated that the proposed pipeline ADC can achieves

good performance and a better trade-off among speed,
precision and power in high speed pipeline ADC designs.

4 Conclusion

A high speed 12-bit 250MSPS pipeline ADC is imple-

mented in CMOS 180 nm 1.8 V 1P5 M process for
application system with the sampling frequency of over
200 MHz. In order to reduce the non-ideal errors and
improve the dynamic performance in the ADC, the PN
digital calibration dithered sub-ADC in first stage is
employed. With the 4 Gbps differential serial output
interface, digital output pins of the whole chip can be
reduced obviously and can satisfy the industrial applica-
tions. The measurement results show that the proposed
Fig. 12 Measured FFT performance versus input frequency

Fig. 13 The measured eye-diagram results of interface a eye-diagram b jitter histogram

123
 Analog Integrated Circuits and Signal Processing

Table 1 Comparison with

Reference Ref. [10] Ref. [11] Ref. [12] Ref. [13] This work
published Pipeline ADC
Fs (MHz) 270 230 200 200 250
Technology (nm) 130 180 55 90 180
Supply (V) 1.2 1.8 1.1 1.2 1.8
DNL (LSB) 0.38 N/A 0.28 0.28 0.25
INL (LSB) 0.84 N/A 1.89 1.89 0.6
SNR (dB) 64.4@30.1 M 57.5@1 M 64.6@10.1 M 64@3.5 M 69.9@20.1 M
SFDR (dB) 77.2@30.1 M 71.3@1 M 82.9@10.1 M N/A 81.1@20.1 M
Power (mW) 250 580 30.7 348 320
Active area (mm2) 1.7 1.97 0.28 1.36 2.5
FOM (fJ/step) 735 6354 111 1340 864

ADC can provide 11.3 effective bits of resolution to satisfy
the high speed industrial applications in low power design.
Acknowledgements This work was supported by Natural Science
Foundation of China (No. 61704161), Higher Education Important
Science Foundation of Anhui Province (No. KJ2017A396) and
Guangzhou Industry-Academia-Research Program (No.
201604016122). The authors would like to thank analog group for the
technical discussions, layout and test group for their layout and test
contributions.
11. Liechti, T., Tajalli, A., Akgun, O. C., Toprak, Z., & Leblebici, Y.
(2008). A 1.8 V 12-bit 230-MS/s pipeline ADC in 0.18 lm
CMOS technology. In IEEE International Circuits and Systems
(pp. 21–24).
12. Shin, S. K., Rudell, J. C., Daily, D. C., et al. (2014). A 12-bit,
200MS/s zero-crossing based pipelined ADC with early sub-ADC
decision and output residue background calibration. IEEE Jour-
nal of Solid-State Circuits, 49(6), 1366.
13. Sahoo, B. D., & Razavi, Behzad. (2009). A 12-bit, 200 MHz
CMOS ADC. IEEE Journal of Solid-State Circuits, 44(9), 2366.

H. J. Wu received the M.S.

References degree in electronic science and
technology from University of
1. Fukuda, K., Yamashita, H., Ono, G., et al. (2010). A 12.3 mW Electronic Science and Tech-
12.5-Gbps complete transceiver in 65 nm CMOS process. IEEE nology of China, Chengdu, in
Journal of Solid-State Circuits, 45(12), 2838. 2008 and the Ph.D. degree at the
2. Kossel, M., Menolfi, C., Weiss, J., et al. (2008). A T-coil-en- School of Electronic and Infor-
hanced 8.5 Gbps high-swing SST transmitter in 65 nm bulk mation Engineering, South
CMOS with\ -16 dB return loss over 10 GHz bandwidth. IEEE China University of Technol-
Journal of Solid-State Circuits, 43(12), 2905. ogy, Guangzhou, China, in
3. Lv, J., Ju, H., Yuan, L., et al. (2011). A high speed low jitter 2014. He is currently involved
LVDS output driver for serial links. Analog Integrated Circuit in designing high performance
and Signal Processing, 68, 387. CMOS data converters in China
4. Junsheng, L., Hao, J., Mao, Y., et al. (2014). A 5 Gb/s low power Electronic Technology Group
current-mode transmitter with pre-emphasis for serial links. Corporation, No.58 Research
Chinese Journal of Semiconductors, 34(7), 065004-1-5. Institute, Wuxi, China. Since 2007, he have been an analog circuit
5. Devarajan, S., Singer, L., Kelly, D., et al. (2009). A 16-bit, engineer in BYD Co., Ltd, Guangzhou Runxin Co., Ltd., Shenzhen
125 MS/s, 385 mW, 78.7 dB SNR CMOS pipeline ADC. IEEE Institutes of Advanced Technology, Chinese Academy of Sciences,
Journal of Solid-State Circuits, 44(12), 3305. and No.58 research institute, China electronic technology group
6. Ali, A. M. A., Dinc, H., Bhoraskar, P., et al. (2009). A 14-bit corporation. His current research interests include Pipeline and SAR
1GS/s RF sampling pipelined ADC with background calibration. ADCs.
IEEE Journal of Solid-State Circuits, 49(12), 2857.
7. Li, J., & Moon, U.-K. (2003). Background calibration techniques
for multistage pipelined ADCs with digital redundancy. IEEE
Transactions on Circuits and Systems II, 50(9), 185.
8. Shi, L., Zhao, W., Jianhui, W., & Chen, C. (2012). Digital
background calibration techniques for pipelined ADC based on
comparator dithering. IEEE Transactions on Circuits and Systems
II, 59(4), 239.
9. Ahja, B. K. (1976). An improved frequency compensation tech-
nique for CMOS operational amplifiers. IEEE Journal of Solid-
State Circuits, 18(6), 629–633.
10. Wang, X., Yang, C., Zhao, X., Wu, C., Li, F., Wang, Z., & Wu,
B. (2012). A 12-bit, 270MS/s pipelined ADC with SHA-elimi-
nating front end. In IEEE International Circuits and Systems (p.
798).

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Analog Integrated Circuits and Signal Processing
Z. H. Chen received the B.S. and
M.S. degree in electronic sci-
ence engineering from Jiangnan
University, Wuxi, China, in
2004 and 2007, and the Ph.D.
degree in Microelectronics from
Xidian University in 2014,
Xi’an China. Since 2008, he has
been with China Electronic
Technology Group Corporation,
No.58 Research Institute, Wuxi,
China, where he is involved in
designing high performance
CMOS data converters. He is
the author and/or co-author of
over 10 technical papers of conferences and journals. Also, he has
filed 24 China patents. His research interests include CMOS analog
and mixed-mode integrated circuit design, especially high perfor-
mance low power data converter.
Z. G. Yu received the B.S. and
M.S. degrees in electronic sci-
ence engineering from Xidian
University, Xi’an, China, in
1985 and 1988, and the Ph.D.
degree from Southest Univer-
sity, Nanjing, China in 1997.
Since 1988, he has been with
China Electronic Technology
Group Corporation, No.58
Research Institute, Wuxi, China.
He is now the chief experts of
China Electronic Technology
Group Corporation. Since 2002,
he became an adjunct professor
of Southeast University, Xidian University and Jiangnan University.
His current research interests include high-speed memory, CMOS
analog and mixed mode integrated circuit design.
123