List of Experiments

IV SEM E&C ENGG.
, HDL LAB (06ECL48)
List of Experiments
EXPERIMENT PAGE NO.
1. HDL code to realize all the logic gates 4-5
2. HDL program for the following combinational designs

2 to 4 decoder 6
8 to 3 (encoder without priority & with priority) 7-9
8 to 1 multiplexer 10-11
4 bit binary to gray converter 11-12
Demultiplexer, Comparator 13-15
3. HDL code to describe the functions of a full adder using all modeling styles. 16-19
4. HDL model for 32-bit ALU. 20
5. HDL codes for the following flip-flops, SR, D, JK, T. 21-25
6. HDL code for 4-bit binary, BCD counters (synchronous reset and asynchronous reset) 25-27
and “any sequence” counters.
Interfacing (at least four of the following must be covered using VHDL /VERILOG)
1. HDL code to display messages on the given seven segment display and LCD
and accepting hex key pad input data. 30-38
2. HDL code to control speed, direction of dc and stepper motor. 48-41
3. VHDL code to generate different waveforms (sine square triangle, ramp etc)
using DAC change the frequency and amplitude. 40-45
4. VHDL code to control external lights using relays. 45
5. HDL code to accept 8 channel analog signals, temperature sensors and

display the data on lcd panel or seven segment display. 45-49
6. VHDL code to simulate elevator operations 50-56
Department of Electronics & Communication, C.I.T, Gubbi

1
IV SEM E&C ENGG., HDL LAB (06ECL48)
SYLLABUS
PROGRAMMING (using VHDL and VERILOG)
1. Write HDL code to realize all the logic gates
2. Write a HDL program for the following combinational designs
a. 2 to 4 decoder
b. 8 to 3 (encoder without priority & with priority)
c. 8 to 1 multiplexer
d. 4 bit binary to gray converter
e. Multiplexer, demultiplexer, comparator
3. Write a HDL code to describe the functions of a full adder using all modeling styles.
4. Write a model for 32-bit ALU using the schematic diagram shown below.
A (31:0) B (31:0)
OPCODE (3:0)
ALU
ENABLE
OUT
ALU should use combinational logic to calculate an output based on the four bit op-code input.
ALU should pass the result to the out bus when enable line in high, and tri-state the out bus when the enable
line is low.
ALU should decode the 4 bit op-code according to the given in example below
OPCODE ALU OPERATION

1 A+B
2 A-B
3 A Complement
4 A*B
5 A AND B
6 A OR B
7 A NAND B
8 A XOR B
5. Develop the HDL codes for the following flip-flops, SR, D, JK, T.
6. Design 4 bit binary, BCD counters (synchronous reset and asynchronous reset) and “any sequence”
counters.
Interfacing (at least four of the following must be covered using VHDL /VERILOG)
1. Write HDL code to display messages on the given seven segment display and LCD and accepting hex
key pad input data.
2. Write HDL code to control speed, direction of dc and stepper motor.
3. Write VHDL code to generate different waveforms (sine square triangle, ramp etc) using DAC change
the frequency and amplitude.
4. Write VHDL code to control external lights using relays.
5. Write a HDL code to accept 8 channel analog signals, temperature sensors and display the data on lcd
panel or seven segment display.
6. Write VHDL code to simulate elevator operations

2
TOOL PROCEDURE
It is one of most popular software tool used to synthesize VHDL code. This tool
Includes many steps. To make user feel comfortable with the tool the steps are
given below:-
 Double click on Project navigator. (Assumed icon is present on desktop).
 Select NEW PROJECT in FILE MENU.
Enter following details as per your convenience
Project name : sample
Project location : C:\example
Top level module : HDL
 In NEW PROJECT dropdown Dialog box, Choose your appropriate device
specification. Example is given below:
Device family : Spartan2
Device : xc2s200
Package : TQ144
TOP Level Module : HDL
Synthesis Tool : XST
Simulation : Modelsim / others
Generate sim lang : VHDL
 In source window right click on specification, select new source
Enter the following details
Entity: sample
Architecture : Behavioral
Enter the input and output port and modes.
This will create sample.VHDL source file. Click Next and finish the initial
Project preparation.
 Double click on synthesis. If error occurs edit and correct VHDL code.
 Double click on Lunch modelsim (or any equivalent simulator if you are using)
for functional simulation of your design.
 Right click on sample.VHDL in source window, select new source
Select source : Implementation constraints file.
File name : sample
This will create sample. UCF constraints file.
 Double click on Edit constraint (Text) in process window.
Edit and enter pin constraints with syntax:
NET “NETNAME” LOC = “PIN NAME”
 Double click on Implement, which will carry out translate, mapping, place and
route of your design. Also generate program file by double clicking on it, intern
which will create .bit file.
 Connect JTAG cable between your kit and parallel pot of your computer.
 Double click on configure device and select mode in which you want to
configure your device. For ex: select slave serial mode in configuration window
and finish your configuration.
 Right click on device and select ‘program’. Verify your design giving
appropriate inputs and check for the output.
 Also verify the actual working of the circuit using pattern generator & logic
analyzer.

3
1. VHDL CODE FOR ALL THE BASIC GATES.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY GATES IS
PORT (A, B: IN STD_LOGIC; NOTOUT
NOTOUT: OUT STD_LOGIC;
A
OROUT
OROUT: OUT STD_LOGIC; Basic ANDOUT
ANDOUT: OUT STD_LOGIC; Gates NOROUT
NOROUT: OUT STD_LOGIC; NANDOUT
NANDOUT: OUT STD_LOGIC; XOROUT
XOROUT: OUT STD_LOGIC; B XNOROUT
XNOROUT: OUT STD_LOGIC);
END GATES;
ARCHITECTURE BEHAVIORAL OF GATES IS
BEGIN
NOTOUT<= NOT A;
OROUT<= A OR B;
ANDOUT<= A AND B;
NOROUT<= A NOR B;
NANDOUT<= A NAND B;
XOROUT <= A XOR B;
XNOROUT <= A XNOR B;
END BEHAVIORAL;
1. VERILOG CODE FOR ALL BASIC GATES
module gates(A, B, NOTOUT, OROUT, ANDOUT, NOROUT,NANDOUT,XOROUT,XNOROUT);

input A,B;
output NOTOUT;
output OROUT;
output ANDOUT;
output NOROUT;
output NANDOUT;
output XOROUT;
output XNOROUT;
assign NOTOUT= ~A;
assign OROUT=A|B;
assign ANDOUT=A&B;
assign NOROUT=~(A|B);
assign NANDOUT=~(A&B);
assign XOROUT=A^B;
assign XNOROUT=~(A^B);
endmodule

4
A A
B B B B
B
B
RESULT:
A A A
A
A B A
0 0 1 0 0 1 1 0 1
0 1 1 1 0 0 1 1 0
1 0 0 1 0 0 1 1 0
1 1 0 1 1 0 0 0 1
NOTOUT OROUT ANDOUT NOROUT NANDOUT XOROUT XNOROUT
UCF file (User constraint file)

NET "A" LOC = "P74";
NET "B" LOC = "P75";
NET "ANDOUT" LOC = "P84";
NET "NANDOUT" LOC = "P85";
NET "NOROUT"
A LOC = "P86";
NET "NOTOUT" LOC = "P87";
NET "OROUT" LOC = "P93";
NET "XNOROUT" LOC = "P94";
NET "XOROUT" LOC = "P95";

5
2. VHDL CODE FOR 2 TO 4 DECODER.
ENTITY DECODER2_4 IS
PORT (ENABLE: IN STD_LOGIC;
DIN: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
D_OUT: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END DECODER2_4; ENABLE
ARCHITECTURE DECODER_ARC OF DECODER2_4 IS
BEGIN
PROCESS (ENABLE, DIN)
BEGIN
IF (ENABLE ='1') THEN D_OUT (3)
Din (1) 2-4
D_OUT <= "0000"; D_OUT (2)
ELSE DECODER
CASE DIN IS D_OUT (1)
WHEN "00" => D_OUT <= "0001"; Din (0)
D_OUT (0)
WHEN "01" => D_OUT <= "0010";
WHEN "10" => D_OUT <= "0100";
WHEN "11" => D_OUT <= "1000";
WHEN OTHERS => NULL;
END CASE;
END IF;
END PROCESS;
END DECODER_ARC;
2. VERILOG CODE FOR 2 TO 4 DECODER
module DECODER (DIN,ENABLE,D_OUT);

input [1:0] DIN;
output [3:0] D_OUT;
reg [3:0] D_OUT;
always @(DIN,ENABLE) RESULT:-
if (ENABLE==1)
begin
D_OUT=4’b0000; Enable Select Lines Outputs
else ENABLE DIN(1) DIN(0) D_OUT(3) D_OUT(2) D_OUT(1) D_OUT(0)
begin 1 X X 0 0 0 0
case (DIN) 0 0 0 0 0 0 1
2'b00: D_OUT = 4'b0001; 0 0 1 0 0 1 0
2'b01: D_OUT = 4'b0010; 0 1 0 0 1 0 0
2'b10:D_OUT = 4'b0100;
0 1 1 1 0 0 0
2'b11: D_OUT = 4'b1000;
default: D_OUT =4'bXXXX;
endcase
end
end
endmodule
===============================================================
UCF FILE (USER CONSTRAINT FILE)

NET "ENABLE" LOC = "P74";
NET "DIN<0>" LOC = "P75";
NET "DIN<1>" LOC = "P76";
NET "D_OUT<0>" LOC = "P84";

6
3.(A) VHDL CODE FOR 8 TO 3 ENCODER.(WITHOUT PRIORITY)
ENTITY ENCODER8_3 IS
ENABLE
END ENCODER8_3;
ARCHITECTURE ENCODER_ARCH OF ENCODER8_3 IS
BEGIN
PROCESS (ENABLE, DIN) DIN(0)
BEGIN
IF (ENABLE = '1') THEN DIN(1)
D-OUT(0)
D_OUT <= "000"; DIN(2)
ELSE 8:3
CASE DIN IS DIN(3) D-OUT(1)
WHEN "00000001" => D_OUT <= "000"; DIN(4) ENCODER
WHEN "00000010" => D_OUT <= "001"; D-OUT(2)
WHEN "00000100" => D_OUT <= "010"; DIN(5)
WHEN "00001000" => D_OUT <= "011"; DIN(6)
WHEN "00010000" => D_OUT <= "100";
WHEN "00100000" => D_OUT <= "101"; DIN(7)
WHEN "01000000" => D_OUT <= "110";
WHEN "10000000" => D_OUT <= "111";
END CASE;
END IF;
END PROCESS;
END ENCODER_ARCH;
3.(A)VERILOG CODE FOR 8TO 3 ENCODER
module ENCODER8_3(ENABLE, DIN, D_OUT);

input EN;
input [7:0] DIN;
output [2:0] D_OUT;
reg [2:0] D_OUT;
always @ (DIN,ENABLE)
begin
if(ENABLE==1| )
D_OUT=3’b000;
else
begin
case (DIN)
8'b00000001: D_OUT = 3'b000;
8'b00000010: D_OUT = 3'b001;
8'b00000100: D_OUT = 3'b010;
8'b00001000: D_OUT = 3'b011;
8'b00010000: D_OUT = 3'b100;
8'b00100000: D_OUT = 3'b101;
8'b01000000: D_OUT = 3'b110;
8'b10000000: D_OUT = 3'b111;
default: D_OUT =3'bXXX;
endcase
end
endmodule

7
RESULT
INPUTS OUTPUTS
D_OUT D_OUT D_OUT
ENABLE DIN(0) DIN(1) DIN(2) DIN(3) DIN(4) DIN(5) DIN(6) DIN(7)
(0) (1) (2)
1 X X X X X X X X 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0 1
0 0 0 1 0 0 0 0 0 0 1 0
0 0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 0 1 1 1 1
===============================================================
UCF FILE(USER CONSTRAINT FILE)
NET "D_IN<0>" LOC = "P75";
NET "D_IN<1>" LOC = "P76";
NET "D_IN<2>" LOC = "P78";
NET "D_IN<3>" LOC = "P77";
NET "D_IN<4>" LOC = "P80";
NET "D_IN<5>" LOC = "P79";
NET "D_IN<6>" LOC = "P83";
NET "D_IN<7>" LOC = "P112";
3.(b) VHDL CODE FOR 8 TO 3 ENCODER.(WITH PRIORITY)
ENTITY ENCODER8_3 IS
ENABLE
END ENCODER8_3;
ARCHITECTURE ENCODER_ARCH OF ENCODER8_3 IS
BEGIN
PROCESS (ENABLE, DIN) DIN(0)
BEGIN
IF (ENABLE = '1') THEN DIN(1)
D-OUT(0)
D_OUT <= "000"; DIN(2)
ELSE 8:3
CASE DIN IS DIN(3) D-OUT(1)
WHEN "00000001" => D_OUT <= "000"; DIN(4) ENCODER
WHEN "0000001-" => D_OUT <= "001"; D-OUT(2)
WHEN "000001--" => D_OUT <= "010"; DIN(5)
WHEN "00001---" => D_OUT <= "011"; DIN(6)
WHEN "0001----" => D_OUT <= "100";
WHEN "001-----" => D_OUT <= "101"; DIN(7)
WHEN "01------" => D_OUT <= "110";
WHEN "1-------" => D_OUT <= "111";
END CASE;
END IF;
END PROCESS;

8
END ENCODER_ARCH;
3.(B)VERILOG CODE FOR 8TO 3 ENCODER
module ENCODER8_3(ENABLE, DIN, D_OUT);

input EN;
input [7:0] DIN;
output [2:0] D_OUT;
reg [2:0] D_OUT;
always @ (DIN,ENABLE)
begin
if(ENABLE==1| )
D_OUT=3’b000;
else
begin
casex (DIN)
8'b00000001: D_OUT = 3'b000;
8'b0000001x: D_OUT = 3'b001;
8'b000001xx: D_OUT = 3'b010;
8'b00001xxx: D_OUT = 3'b011;
8'b0001xxxx: D_OUT = 3'b100;
8'b001xxxxx: D_OUT = 3'b101;
8'b01xxxxxx: D_OUT = 3'b110;
8'b1xxxxxxx: D_OUT = 3'b111;
default: D_OUT =3'bXXX;
endcase
end
endmodule
RESULT
INPUTS OUTPUTS
D_OUT D_OUT D_OUT
ENABLE DIN(0) DIN(1) DIN(2) DIN(3) DIN(4) DIN(5) DIN(6) DIN(7)
(0) (1) (2)
1 X X X X X X X X 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0
0 X 1 0 0 0 0 0 0 0 0 1
0 X X 1 0 0 0 0 0 0 1 0
0 X X X 1 0 0 0 0 0 1 1
0 X X X X 1 0 0 0 1 0 0
0 X X X X X 1 0 0 1 0 1
0 X X X X X X 1 0 1 1 0
0 X X XX X X X X 1 1 1 1
===============================================================
NET "D_IN<0>" LOC = "P75";
NET "D_IN<1>" LOC = "P76";
NET "D_IN<2>" LOC = "P78";
NET "D_IN<3>" LOC = "P77";
NET "D_IN<4>" LOC = "P80";
NET "D_IN<5>" LOC = "P79";
NET "D_IN<6>" LOC = "P83";
NET "D_IN<7>" LOC = "P112";

9

4. VHDL CODE FOR 8:1 MUX.
ENTITY MUX8_1 IS
PORT (SEL: IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- SELECT LINES
A, B, C, D, E, F, G, H: IN STD_LOGIC; -- INPUTS OF THE MUX.
MUX_OUT: OUT STD_LOGIC); -- OUTPUT OF THE MUX.
END MUX8_1;
ARCHITECTURE MUX4_1_ARCH OF MUX8_1 IS
A
BEGIN B
PROCESS (SEL, A, B, C, D, E, F, G, H)
C
BEGIN 8: 1 MUX_OUT
CASE SEL IS D
WHEN "000" => MUX_OUT <= A;
WHEN "001" => MUX_OUT <= B; E MUX
WHEN "010" => MUX_OUT <= C; F
WHEN "011" => MUX_OUT <= D;
WHEN "100" => MUX_OUT <= E; G
WHEN "101" => MUX_OUT <= F; H
WHEN "110" => MUX_OUT <= G;
WHEN "111" => MUX_OUT <= H;
END CASE; SEL(2) SEL(1) SEL(0)
END PROCESS;
END MUX4_1_ARCH;
===============================================================
NET "SEL<0>" LOC = "P74";
NET "A" LOC = "P78";
NET "B" LOC = "P77";
NET "C" LOC = "P80";
NET "D" LOC = "P79";
NET "E" LOC = "P83";
NET "F" LOC = "P112";
NET "G" LOC = "P114";
NET "H" LOC = "P113";
NET "MUX_OUT" LOC = "P84";
===============================================================
4. VERILOG CODE FOR 8TO 1 MUX
module MUX8_1(A, SEL, D_OUT);
input [7:0] A;
input [2:0] SEL;
output D_OUT;
reg D_OUT;
always@ (A,SEL )
begin
case (SEL)
3'b000:D_OUT=A[0];
3'b001:D_OUT=A[1];
3'b010:D_OUT=A[2];
3'b011:D_OUT=A[3];
3'b100:D_OUT=A[4];
3'b101:D_OUT=A[5];
3'b110:D_OUT=A[6];
3'b111:D_OUT=A[7];
default: D_OUT =3'b000;

10
endcase
end
endmodule
RESULT:
INPUTS OUTPUT
SEL[2] SEL[1] SEL[0] D_OUT
0 0 0 A[0]
0 0 1 A[1]
0 1 0 A[2]
0 1 1 A[3]
1 0 0 A[4]
1 0 1 A[5]
1 1 0 A[6]
1 1 1 A[7]
===============================================================
NET "A[0]" LOC = "P78";
NET "A[1]" LOC = "P77";
NET "A[2]" LOC = "P80";
NET "A[3]" LOC = "P79";
NET "A[4]" LOC = "P83";
NET "A[5]" LOC = "P112";
NET "A[6]" LOC = "P114";
NET "A[7]" LOC = "P113";
NET "D_OUT" LOC = "P84";
===============================================================
5. CODE 4 BIT BINARY TO GRAY CONVERTER.

B(3) G(3)
ENTITY BINARY_GRAY IS
PORT( B: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
G: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END BINARY_GRAY; B(2) G(2)
ARCHITECTURE BEHAVIORAL OF BINARY_GRAY IS
BEGIN
G(3)<= B(3); G(1)
G(2)<= B(3) XOR B(2); B(1)
G(1)<= B(2) XOR B(1);
G(0)<= B(1) XOR B(0);
END BEHAVIORAL; B(0) G(0)
G2 G1 G0
B1 B0 B1 B0 B1 B0
B3 B2 00 01 11 10 B3 B2 00 01 11 10 B3 B2 00 01 11 10
00 00 1 1 00 1 1
01 1 1 1 1 01 1 1 01 1 1
11 11 1 1 11 1 1
10 1 1 1 1 10 1 1 10 1 1
G3=B3 G2 = B3 B2’ + B3 B2’ G1 = B2 B1’ + B1 B2’ G0 = B1’B0 + B1 B0’

G2 = B3  B2 G1 = B1  B2 G0 = B1  B0
5. VERILOG CODE FOR BINARY TO GRAY CONVERTER
module BINARY_GRAY(B, G);

input [3:0] B;

11
output [3:0] G;
assign G[3] = B[3];
assign G[2] = B[3] ^ B[2];
assign G[1] = B[2] ^ B[1];
assign G[0] = B[1] ^ B[0];
endmodule
RESULT:
Binary inputs Gray Outputs

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
===============================================================
NET "B<0>" LOC = "P74";
NET "B<1>" LOC = "P75";
NET "B<2>" LOC = "P76";
NET "B<3>" LOC = "P78";
NET "G<0>" LOC = "P84";
NET "G<1>" LOC = "P85";
NET "G<2>" LOC = "P86";
NET "G<3>" LOC = "P87";
6. VHDL CODE FOR 1:4 DEMUX.

ENTITY DEMUX1_4 IS
PORT (D_IN: IN STD_LOGIC; --INPUT FOR DEMULTIPLEXER
SEL: IN STD_LOGIC_VECTOR (1 DOWNTO 0); --SELECT LINE OF DEMUX

12
D_OUT: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); --OUTPUT LINES OF DEMUX

END DEMUX1_4;
ARCHITECTURE DEMUX1_4_ARCH OF DEMUX1_4 IS
BEGIN D_OUT[3]
PROCESS (D_IN, SEL) 1:4
D_OUT[2]
BEGIN
D_IN
CASE SEL IS DEMUX D_OUT[1]
WHEN "00" => D_OUT (0) <=D_IN;
WHEN "01" => D_OUT (1) <=D_IN; D_OUT[0]
WHEN "10" => D_OUT (2) <=D_IN;
WHEN "11" => D_OUT (3) <=D_IN;
WHEN OTHERS => D_OUT<=”0000”;
END CASE;
END PROCESS;
END DEMUX1_4_ARCH;
SEL[1] SEL[0]
===============================================================
NET "SEL<0>” LOC = "P74";
NET "SEL<1>” LOC = "P75";
NET "D_IN" LOC = "P76";
===============================================================
6. VERILOG CODE FOR 1:4 DEMUX
module DEMUX1_4(D_IN, SEL, D_OUT);

input D_IN;
input [1:0] SEL;
D_IN
output [3:0] D_OUT;
reg[3:0] D_OUT;
always @(D_IN, SEL)
begin
case (SEL)
2b00:D_OUT[0]=D_IN;
2'b01:D_OUT[1]=D_IN;
default: D_OUT=3'b000;
endcase
end
endmodule
RESULT:-

13
SELECT INPUT OUTPUT

SEL[1] SEL[0] D_IN D_OUT[3] D_OUT[2] D_OUT[1] D_OUT[0]
0 0 1 X X X 1
0 1 1 X X 1 X
1 0 1 X 1 X X
1 1 1 1 X X X
===============================================================
UCF file(User constraint file)
NET "SEL<0>” LOC = "p74";
NET "SEL<1>” LOC = "p75";
NET "D_IN" LOC = "p76";
NET "D_OUT[0]" LOC = "p84";
7. COMBINATIONAL VHDL CODE FOR N BIT COMPARATOR.
ENTITY COMPARATOR IS
GENERIC (N: INTEGER: = 3);
PORT (A, B: IN STD_LOGIC_VECTOR (N DOWNTO 0) ;
ALB, AGB, AEB: OUT STD_LOGIC);
END COMPARATOR;
ARCHITECTURE COMPARATOR_ARC OF COMPARATOR IS
BEGIN
PROCESS (A, B)
BEGIN
IF (A < B) THEN
ALB <= '1'; A<B
ELSE A 4-BIT
ALB <= '0';
END IF; COMPARATER A>B
IF (A > B) THEN B
AGB <= '1'; A=B
ELSE
AGB <= '0';
END IF;
IF (A = B) THEN
AEB <= '1';
ELSE
AEB <= '0';
END IF;
END PROCESS;
END COMPARATOR_ARC;
7. COMBINATIONAL VERILOG CODE FOR 4-BIT COMPARATOR
module COMPARATER(A, B, ALB,AGB,AEB);

input [3:0] A;

14
input [3:0] B;
output ALB;
output AGB;
output AEB;
reg ALB,AGB,AEB;
always @ (A,B)
begin
if (A<B)
ALB=1'b1;
else
ALB=1'b0;
if (A>B)
AGB=1'b1;
else
AGB=1'b0;
if (A==B)
AEB=1'b1;
else
AEB=1'b0;
end
endmodule
RESULT:
A B A=B A>B A<B

0000 0000 1 0 0
0000 0100 0 0 1
0100 0001 0 1 0
===============================================================
NET "A<0>" LOC = "p74";
NET "A<1>" LOC = "p75";
NET "A<2>" LOC = "p76";
NET "A<3>" LOC = "p78";
NET "B<0>" LOC = "p77";
NET "B<1>" LOC = "p80";
NET "B<2>" LOC = "p79";
NET "B<3>" LOC = "p83";
NET "ALB" LOC = "p84";
NET "AGB" LOC = "p85";
NET "AEB" LOC = "p86";
===============================================================
8a. VHDL CODE FOR THE IMPLEMENTATION OF HALF ADDER.
DATA FLOW STYLE

ENTITY HALFADDER IS

15
PORT (A, B: IN STD_LOGIC; --2BIT INPUT

SUM, CARRY: OUT STD_LOGIC); --SUM& CARRY
END HALFADDER;
ARCHITECTURE DATAFLOW OF HALFADDER IS
BEGIN
SUM <= A XOR B;
CARRY<= A AND B;
END DATAFLOW;
BEHAVIORAL STYLE
ENTITY HALFADDER IS
END HALFADDER;
ARCHITECTURE BEHAVIORAL OF HALFADDER IS
BEGIN
PROCESS(A,B)
VARIABLE TEMP:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
TEMP: =A&B;
CASE TEMP IS
WHEN”00”=>SUM<=’0’; CARRY<=’0’;
WHEN”01”=>SUM<=’1’; CARRY<=’0’;
WHEN”10”=>SUM<=’1’; CARRY<=’0’;
WHEN”11”=>SUM<=’0’; CARRY<=’1’;
WHEN OTHERS=>NULL;
END CASE;
END PROCESS;
END BEHAVIORAL; U1
STRUCTURAL STYLE
ENTITY HALFADDER IS
END HALFADDER;
ARCHITECTURE STRUCTURAL OF HALFADDER IS
COMPONENT XOR1 IS
PORT(X, Y: IN STD_LOGIC; U2
Z: OUT STD_LOGIC);
END COMPONENT;
COMPONENT AND1 IS
PORT (P, Q: IN STD_LOGIC;
R: OUT STD_LOGIC);
END COMPONENT;
BEGIN
U1:XOR1 PORT MAP (A, B, SUM);
U2:AND1 PORT MAP (A,B, CARRY);
END STRUCTURAL;
COMPONENT PROGRAM
ENTITY XOR1 IS
PORT (X, Y: IN STD_LOGIC; --2BIT INPUT
Z: OUT STD_LOGIC); --SUM& CARRY
END XOR1;
ARCHITECTURE BEHAVIORAL OF XOR1 IS

BEGIN
Z <= X XOR Y;
END BEHAVIORAL;

16
ENTITY AND1 IS
PORT (P, Q: IN STD_LOGIC; --2BIT INPUT
R: OUT STD_LOGIC); --SUM& CARRY
END AND1;
ARCHITECTURE BEHAVIORAL OF AND1 IS
BEGIN
R<= P AND Q;
END BEHAVIORAL;
8b.VERILOG CODE FOR THE IMPLEMENTATION OF HALF ADDER.
DATA FLOW STYLE

module HALFADDER(A, B, SUM, CARRY);
input A, B;
output SUM, CARRY;
assign SUM = A^B;
assign CARRY = A & B;
endmodule
BEHAVIORAL STYLE
module HALFADDER(AB, SUM, CARRY);
input[1:0] AB;
output SUM,CARRY;
reg SUM,CARRY;
always@(AB)
begin
case AB
2’b00:begin SUM=1’b0; CARRY=1’b0;end
endcase
end
endmodule
STRUCTURAL STYLE
module HALFADDER(A, B, SUM, CARRY); RESULT
input A,B;
output SUM,CARRY; Inputs Outputs
XOR U1 ( SUM , A, B); A B Sum(S) Carry(C)
AND U2 (CARRY, A, B); 0 0 0 0
endmodule 0 1 1 0
1 0 1 0
1 1 0 1
===============================================================
NET "A” LOC = "p74";
NET "B” LOC = "p75";
NET "SUM” LOC = "p84";
NET "CARRY” LOC = "p85";
==============================================================
9a. VHDL CODE FOR THE IMPLEMENTATION OF FULL ADDER.
Truth table
Inputs Outputs

17
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
SUM CARRY
BC BC
A 00 01 11 10 A 00 01 11 10
0 0 1 0 1 0 0 0 1 0
1 1 0 1 0 1 0 1 1 1
SUM=A’B’C+A’BC’+AB’C’+ABC
CARRY = AB+BC+AC
SUM = A  B C
DATA FLOW STYLE
ENTITY FULLADDER IS
PORT (A, B, CIN: IN STD_LOGIC; --3BIT INPUT
END FULLADDER;
ARCHITECTURE DATAFLOE OF FULLADDER IS
BEGIN
SUM <= A XOR B XOR CIN;
CARRY<= (A AND B) OR (B AND C) OR (A AND C);
END DATAFLOE;
BEHAVIORAL STYLE
ENTITY FULLADDER IS
PORT (A, B, CIN: IN STD_LOGIC; --3BIT INPUT
END FULLADDER;
ARCHITECTURE BEHAVIORAL OF FULLADDER IS
BEGIN
PROCESS(A,B,CIN)
VARIABLE TEMP:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
TEMP: =A&B&CIN;
CASE TEMP IS
WHEN”000”=>SUM<=’0’; CARRY<=’0’;
WHEN”001”=>SUM<=’1’; CARRY<=’0’;
WHEN”010”=>SUM<=’1’; CARRY<=’0’;
WHEN”011”=>SUM<=’0’; CARRY<=’1’;
WHEN”100”=>SUM<=’1’; CARRY<=’0’;
WHEN”101”=>SUM<=’0’; CARRY<=’1’;
WHEN”110”=>SUM<=’0’; CARRY<=’1’;
WHEN”111”=>SUM<=’1’; CARRY<=’1’;
WHEN OTHERS=>NULL;
END CASE;
END PROCESS; Temp1
END BEHAVIORAL; A SUM
STRUCTURAL STYLE
HA1 HA2
ENTITY FULLADDER IS
B
PORT (A, B, CIN: IN STD_LOGIC;
SUM, CARRY: OUT STD_LOGIC);
CARRY
Department of ElectronicsCIN
& Communication, C.I.T, Gubbi
18
Temp 2
END FULLADDER; Temp 3

ARCHITECTURE STRUCTURAL OF FULLADDER IS
COMPONENT HALFADDER IS
PORT (P, Q: IN STD_LOGIC;
R, S: OUT STD_LOGIC);
END COMPONENT;
SIGNAL Temp1, Temp2, Temp3: STD_LOGIC;
BEGIN
HA1: HALFADDER PORT MAP (A, B, Temp1,Temp2);
HA2: HALFADDER PORT MAP (Temp1, CIN, SUM, Temp3);
CARRY <=Temp2 OR Temp3;
END STRUCTURAL;
9b.VERILOG CODE FOR THE IMPLEMENTATION OF FULL ADDER.
DATA FLOW STYLE

module FULLADDER(A, B, CIN, SUM, CARRY);
input A, B,CIN;
output SUM, CARRY;
assign SUM = A^B^CIN;
assign CARRY = (A & B)|(B & CIN)|(A & CIN);
endmodule
BEHAVIORAL STYLE
module FULLADDER(ABC, SUM, CARRY);
input[2:0] ABC;
output SUM,CARRY;
reg SUM,CARRY;
always@(ABC)
begin
case (ABC)
3’b100:begin SUM=1’b1; CARRY=1’b0end
endcase
end
endmodule
STRUCTURAL STYLE
module FULLADDER(A, B, CIN, SUM, CARRY);
input A,B, CIN;
output SUM,CARRY;
wire Temp1, Temp2, Temp3;
HALFADDER HA1 (A, B, Temp1, Temp2);
HALFADDER HA2 (CIN, Temp1, SUM, Temp3);
assign CARRY=Temp3| Temp2;
endmodule
===============================================================
NET "A” LOC = "p74"; NET "B” LOC = "p75"; NET "CIN” LOC = "p76";
NET "SUM” LOC = "p84"; NET "CARRY” LOC = "p85";
9. VHDL CODE FOR 8 BIT ALU MODEL
ENTITY ALU IS
PORT (A, B: IN STD_LOGIC_VECTOR (31 DOWNTO 0) ;
OPCODE: IN STD_LOGIC_VECTOR (2 DOWNTO 0);

19
ENABLE: IN STD_LOGIC; -- ENABLE SIGNAL

Y: OUT STD_LOGIC_VECTOR (31 DOWNTO 0));
END ALU;
ARCHITECTURE BEHAVIORAL OF ALU IS
BEGIN
PROCESS (A, B, OPCODE, ENB)
BEGIN
IF ENABLE= '1' THEN
CASE OPCODE IS
WHEN "000" => Y<=A+B;
WHEN "001" => Y<=A-B;
WHEN "010" => Y<=NOT A;
----WHEN "011" => Y<=A*B;
WHEN "100" => Y<=A AND B;
WHEN "101" => Y<=A OR B;
WHEN "110" => Y<=A NAND B;
WHEN "111" => Y<=A XOR B;
WHEN OTHERS =>NULL;
END CASE;
ELSE
Y<= (OTHERS =>'Z');
END IF;
END PROCESS;
END BEHAVIORAL;
9. VERILOG CODE FOR 8-BIT ALU MODEL.

module ALU(A, B, SEL,EN,Y);
input [31:0] A,B;
input EN;
input [2:0] SEL;
output [31:0] Y;
reg [31:0]Y;
always @(A, B , SEL)
begin
if (EN==1)
begin
case (SEL)
3'b000:Y=A+B;
3'b001:Y=A-B;
3'b010:Y=~A;
3'b011:Y=A&B;
3'b100:Y=A|B;
3'b101:Y=~(A&B);
3'b101:Y=~(A|B);
3'b111:Y=A^B;
endcase
end
else
begin
Y=31’bZ;
end
end
endmodule
10. VHDL CODE FOR SR F/F.
ENTITY SRFF IS
PORT ( RST, CLK: IN STD_LOGIC;

20
SR: IN STD_LOGIC_VECTOR (1 DOWNTO 0);

Q, QBAR: BUFFER STD_LOGIC); RST
END SRFF;
ARCHITECTURE BEHAVIORAL OF SRFF IS
BEGIN
PROCESS (CLK)
VARIABLE TEMP1, TEMP2:STD_LOGIC; S Q
BEGIN S-R
IF (RST=’1’) THEN
TEMP1:=’0’; CLK
FLIP-FLOP
TEMP2:=’1’;
ELSIF RISING_EDGE (CLK) THEN R QBAR
CASE SR IS
WHEN”00”=>TEMP1:=TEMP1; TEMP2:=TEMP2;
WHEN”01”=>TEMP1:=’0’; TEMP2:=’1’;
WHEN”10”=>TEMP1:=’1’; TEMP2:=’0’;
WHEN”11”=>TEMP1:=’Z’; TEMP2:=’Z’;
WHEN OTHERS=>NULL;
END CASE;
END IF;
Q<=TEMP1;
QBAR<=TEMP2;
END PROCESS;
RESULT: INPUTS OUTPUTS
END BEHAVIORAL;
RST S R Q QBAR
1 X X 0 1
10. VERILOG CODE FOR SR F/F
0 0 0 0 1
module SR_FF(SR, CLK, RST, Q, QBAR); 0 0 1 0 1
input [1:0]SR; 0 1 0 1 0
input RST, CLK; 0 1 1 X X
output Q,QBAR;
reg Q,QBAR;
always @ (posedge CLK)
begin
if (RST==1)
begin
Q=0;
QBAR=1;
end
else
begin
case (SR)
2'b00: begin Q=Q; QBAR=QBAR; end
2'b01: begin Q=0; QBAR=1; end
2'b11: begin Q=1’bX; QBAR=1’bX; end
endcase
end
end
endmodule
===============================================================
NET "S” LOC = "P74";
NET "R” LOC = "P75";
NET "CLK” LOC = "P18";
NET "Q” LOC = "P84";
===============================================================
11. VHDL CODE FOR D F/F.

21
ENTITY DFF IS
PORT (CLK, RST: IN STD_LOGIC;
D: IN STD_LOGIC;
Q, QBAR: OUT STD_LOGIC);
END DFF;
ARCHITECTURE D_FF_ARCH OF DFF IS D Q
BEGIN D
PROCESS (CLK) CLK
BEGIN FLIP-FLOP
IF RST=’1’ THEN
Q<=’0’; RST QBAR
QBAR <=’1’;
ELSIF (RISING_EDGE (CLK)) THEN
Q<=D;
QBAR<=NOT (Q);
ELSE
Q<=Q;
QBAR<=QBAR;
END IF;
END PROCESS;
END D_FF_ARCH;
11. VERILOG CODE FOR D-FLIPFLOP.

module D_FF(D, RESET, CLK, Q, QBAR);
input D, RESET, CLK;
output Q, QBAR;
reg Q,QBAR;
always@(posedge CLK)
begin
if (RESET==1)
begin
Q=0;
QBAR=1;
end
else
begin
Q=D;
QBAR=~D;
end
end
endmodule
RESULT:-
RESET D Q QBAR
1 X 0 1
0 0 0 1
0 1 1 0
===============================================================
NET "RESET” LOC = "P74";
NET "D” LOC = "P75";
NET “QBAR”LOC=”P85”;
===============================================================
12. VHDL CODE FOR JK F/F

ENTITY JKFF IS

22
PORT (CLK, RESET: IN BIT; RST

JK: IN BIT_VECTOR (1 DOWNTO 0);
Q, QBAR: INOUT BIT);
END JKFF;
ARCHITECTURE JKFF_ARCH OF JKFF IS
SIGNAL DIV: STD_LOGIC_ VECTOR (22 DOWNTO 0);
SIGNAL CLKDIV: STD_LOGIC; J Q
J-K
BEGIN
PROCESS (CLK) --CLKDIVIDE CLK
BEGIN FLIP-FLOP
IF RISING_EDGE (CLK) THEN
K QBAR
DIV<=DIV+1;
ENDIF;
END PROCESS;
CLKDIV<=DIV (22);
PROCESS (CLKDIV, RESET)
BEGIN
IF (RESET='1') THEN
Q<='0';
QBAR<=’1’;
ELSIF (RISING_EDGE (CLKDIV)) THEN
CASE JK IS
WHEN”00”=>Q<=Q; QBAR<=QBAR;
WHEN”01”=>Q<=’0’; QBAR<=’1’;
WHEN”10”=>Q<=’1’; QBAR<=’0’;
WHEN”11”=>Q<=NOT(Q); QBAR<=NOT(QBAR);
WHEN OTHERS=>NULL;
END CASE;
END IF;
END PROCESS;
END JKFF_ARCH;
12. VERILOG CODE FOR JK-FLIPFLOP.
module JK_FF(J, K, CLK, RESET, Q, QBAR);

input [1:0]JK;
input CLK,RESET;
output Q, QBAR;
reg Q, QBAR;
reg [22:0] div;
reg clkdiv
always @ (posedge CLK)
begin
div=div+1;
end
clkdiv=div[22];
if(RESET==1)
begin
Q=0;
QBAR=1;
end
else if(posedge(clkdiv))
begin
case (JK)
2'b00: begin Q=Q; QBAR=QBAR; end
2'b11: begin Q=~(Q); QBAR=~(QBAR); end
endcase
end

23
end
endmodule
RESULT:-
RESET J K Q QBAR
1 X X 0 1
0 0 0 0 1
0 0 1 0 1
0 1 0 1 0
0 1 1 1 0
==============================================================
NET "J” LOC= "P74";
NET "K” LOC = "P75";
NET "RESET” LOC = "P76";
NET "QBAR” LOC = "P85";
===============================================================
13. VHDL CODE FOR T F/F.
ENTITY TFF IS T Q
T
PORT (T: IN STD_LOGIC;
CLK, RST: IN STD_LOGIC; CLK
Q, QBAR: OUT STD_LOGIC); FLIP-FLOP
END TFF; RST QBAR
ARCHITECTURE T_FF_ARCH OF TFF IS
SIGNAL DIV:STD_LOGIC_VECTOR(22 DOWNTO 0);
SIGNAL CLKDIV:STD_LOGIC;
BEGIN
PROCESS (CLK)--CLKDIVIDE
BEGIN
IF RISING_EDGE(CLK) THEN
DIV<=DIV+1;
ENDIF;
END PROCESS;
CLKDIV<=DIV(22);
BEGIN
PROCESS (CLKDIV)
BEGIN
IF RST=’1’ THEN
Q<=’0’;
QBAR<=’1’;
IF (RISING_EDGE(CLKDIV)) THEN
CASE T IS
WHEN’0’=>Q<=Q; QBAR<=QBAR;
WHEN’1’=>Q<=NOT(Q); QBAR<=NOT(QBAR);
END CASE;
END IF;
END PROCESS;
END T_FF_ARCH;

24
13. VERILOG CODE FOR T-FLIPFLOP.
module T_FF(T, CLK, RESET, Q, QBAR);

input T, CLK, RESET;
output Q, QBAR; RESULT:
reg Q,QBAR;
always @ (posedge CLK) RESET T Q QBAR
begin 1 X 0 1
if (RESET==1) 0 0 1 0
begin 0 1 0 1
Q=0;
QBAR=1;
end
else if()
case T
1’b0:begin Q=Q; QBAR=QBAR; end
1’b1:begin Q=~(Q); QBAR=~(QBAR)S; end
endcase
end
endmodule
===============================================================
NET "RESET” LOC= "P74";
NET "T” LOC= "P75";
NET "QBAR” LOC= "P85";
14. 4-BIT ASYNCHRONOUS BINARY COUNTER.(FOR HARDWARE IMPLEMENTATION)

LIBRARY IEEE;
ENTITY ASYNC_COUNTER IS
PORT( CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
COUNT: OUT STD_LOGIC_VECTOR( 3 DOWNTO 0));
END ASYNC_COUNTER;
ARCHITECTURE COUNTER_ARCH OF ASYNC_COUNTER IS
BEGIN
PROCESS (CLK)--CLKDIVIDE
BEGIN
DIV<=DIV+1;
ENDIF;
END PROCESS;
CLKDIV<=DIV(22);
PROCESS (CLKDIV, RESET)
BEGIN
IF RESET='1' THEN
COUNT <= “0000”;
ELSIF (RISING_EDGE (CLKDIV)) THEN
COUNT <= COUNT + 1;
END IF;
END PROCESS;
END COUNTER_ARCH;

25
RESULT:-
Clock Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1 ===========================================
2 0 0 1 0 UCF FILE(USER CONSTRAINT FILE)
3 0 0 1 1 NET "RESET" LOC= "P74";
4 0 1 0 0 NET "CLK" LOC = "P18";
NET "COUNT<0>" LOC = "P84";
5 0 1 0 1 NET "COUNT<1>" LOC = "P85";
6 0 1 1 0 NET "COUNT<2>" LOC = "P86";
7 0 1 1 1 NET "COUNT<3>" LOC = "P87";
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
14 3-BIT SYNCHRONOUS BINARY COUNTER.(FOR HARDWARE IMPLEMENTATION)
LIBRARY IEEE;
ENTITY SYNC_COUNTER IS
PORT( CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
COUNT: INOUT STD_LOGIC_VECTOR ( 2 DOWNTO 0));
END SYNC_COUNTER;
ARCHITECTURE COUNTER_ARCH OF SYNC_COUNTER IS
BEGIN
PROCESS (CLK)
BEGIN
IF RISING_EDGE (CLK) THEN
DIV<=DIV+1;
ENDIF;
END PROCESS;
CLKDIV<=DIV(22);
PROCESS(CLKDIV)
BEGIN
IF (RESET='1') THEN
COUNT<=”000”;
ELSE
CASE COUNT IS
WHEN”000”=>COUNT<=”001”;
WHEN”001”=>COUNT<=”010”;
WHEN”010”=>COUNT<=”011”;
WHEN”011”=>COUNT<=”100”;
WHEN”100”=>COUNT<=”101”;
WHEN”101”=>COUNT<=”000”;
WHEN OTHERS=>NULL”;
END CASE;
END IF;

26
END PROCESS; END COUNTER_ARCH;

14. VERILOG CODE FOR SYNCHRONOUS COUNTER
module SYNCH_COUNTER(CLK, RESET, COUNT);

input CLK;
input RESET;
output [3:0] COUNT;
reg [3:0] COUNT;
always @ (posedge CLK )
begin
if (RESET==1)
COUNT=4'b0000;
else
COUNT=COUNT+1'b1;
end
endmodule
RESULT:-
Clock Q3 Q2 Q1 Q0
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
===============================================================
NET "RESET" LOC= "P74";
NET "CLK" LOC = "P18";
===============================================================

27
INTERFACING
--Package for LCD Display (This Package must be added to display all the messages on
LCD)
-- Package File Template
-- Purpose: This package defines supplemental types, subtypes, constants, and functions
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package LCD_GRAP is
-- THE NUMBERS
constant ONE : std_logic_vector(7 downto 0) := "00110001";
constant TWO : std_logic_vector(7 downto 0) := "00110010";
constant THREE : std_logic_vector(7 downto 0) := "00110011";
constant FOUR : std_logic_vector(7 downto 0) := "00110100";
constant FIVE : std_logic_vector(7 downto 0) := "00110101";
constant SIX : std_logic_vector(7 downto 0) := "00110110";
constant SEVEN : std_logic_vector(7 downto 0) := "00110111";
constant EIGHT : std_logic_vector(7 downto 0) := "00111000";
constant NINE : std_logic_vector(7 downto 0) := "00111001";
constant ZERO : std_logic_vector(7 downto 0) := "00110000";
-- THE CHARACTERS
constant A : std_logic_vector(7 downto 0) := "01000001";
constant B : std_logic_vector(7 downto 0) := "01000010";
constant C : std_logic_vector(7 downto 0) := "01000011";
constant D : std_logic_vector(7 downto 0) := "01000100";
constant E : std_logic_vector(7 downto 0) := "01000101";
constant F : std_logic_vector(7 downto 0) := "01000110";
constant G : std_logic_vector(7 downto 0) := "01000111";
constant H : std_logic_vector(7 downto 0) := "01001000";
constant I : std_logic_vector(7 downto 0) := "01001001";
constant J : std_logic_vector(7 downto 0) := "01001010";
constant K : std_logic_vector(7 downto 0) := "01001011";
constant L : std_logic_vector(7 downto 0) := "01001100";
constant M : std_logic_vector(7 downto 0) := "01001101";
constant N : std_logic_vector(7 downto 0) := "01001110";
constant O : std_logic_vector(7 downto 0) := "01001111";
constant P : std_logic_vector(7 downto 0) := "01010000";
constant Q: std_logic_vector(7 downto 0) := "01010001";
constant R : std_logic_vector(7 downto 0) := "01010010";
constant S : std_logic_vector(7 downto 0) := "01010011";
constant T : std_logic_vector(7 downto 0) := "01010100";
constant U : std_logic_vector(7 downto 0) := "01010101";
constant V : std_logic_vector(7 downto 0) := "01010110";
constant W : std_logic_vector(7 downto 0) := "01010111";
constant X : std_logic_vector(7 downto 0) := "01011000";
constant Y : std_logic_vector(7 downto 0) := "01011001";
constant Z : std_logic_vector(7 downto 0) := "01011010";

28
-- SMAL LETTERS
constant SA : std_logic_vector(7 downto 0) := "01100001";
constant SB : std_logic_vector(7 downto 0) := "01100010";
constant SC : std_logic_vector(7 downto 0) := "01100011";
constant SD : std_logic_vector(7 downto 0) := "01100100";
constant SE : std_logic_vector(7 downto 0) := "01100101";
constant SF : std_logic_vector(7 downto 0) := "01100110";
constant SG : std_logic_vector(7 downto 0) := "01100111";
constant SH : std_logic_vector(7 downto 0) := "01101000";
constant SI : std_logic_vector(7 downto 0) := "01101001";
constant SJ : std_logic_vector(7 downto 0) := "01101010";
constant SK : std_logic_vector(7 downto 0) := "01101011";
constant SL : std_logic_vector(7 downto 0) := "01101100";
constant SM : std_logic_vector(7 downto 0) := "01101101";
constant SN : std_logic_vector(7 downto 0) := "01101110";
constant SO : std_logic_vector(7 downto 0) := "01101111";
constant SP : std_logic_vector(7 downto 0) := "01110000";
constant SQ : std_logic_vector(7 downto 0) := "01110001";
constant SR : std_logic_vector(7 downto 0) := "01110010";
constant SS : std_logic_vector(7 downto 0) := "01110011";
constant ST : std_logic_vector(7 downto 0) := "01110100";
constant SU : std_logic_vector(7 downto 0) := "01110101";
constant SV : std_logic_vector(7 downto 0) := "01110110";
constant SW : std_logic_vector(7 downto 0) := "01110111";
constant SX : std_logic_vector(7 downto 0) := "01111000";
constant SY : std_logic_vector(7 downto 0) := "01111001";
constant SZ : std_logic_vector(7 downto 0) := "01111010";
---THE SYMBOLS
constant SPACE: std_logic_vector(7 downto 0) := "00100000";
constant SLASH: std_logic_vector(7 downto 0) := "00101111";
constant MINUS: std_logic_vector(7 downto 0) := "00101101";
constant EQUAL: std_logic_vector(7 downto 0) := "00111101";
constant PLUS : std_logic_vector(7 downto 0) := "00101011";
constant STAR : std_logic_vector(7 downto 0) := "00101010";
constant DOT : std_logic_vector(7 downto 0) := "00101110";
end LCD_GRAP;

29
1a.WRITE VHDL CODE TO DISPLAY MESSAGES ON THE GIVEN LCD ACCEPTING HEX
KEY PAD INPUT DATA.
AIM: TO DISPLAY THE MESSAGE ON THE LCD PANEL BY ACCEPTING HEX KEY BOARD
DATA AS INPUT.
PROCEDURE:
1. Make the connection between FRC5 of the FPGA board to the LCD display
Connector of the VTU card1.
2. Make the connection between FRC 4 of the FPGA board to the key board
3. Make the connection between FRC 6 of the FPGA board to the dip switch
4. Connect the downloading cable and power supply to the FPGA board
5. Then open the xilinx impact software (refer ISE flow) select the slave
Serial mode and select the respective bit file and click program.
6. Make the reset switch on (active low).
7. Press the hex keys and analyze the data.
VHDL CODE
LIBRARY IEEE;
USE WORK.LCD_GRAP.ALL;
ENTITY HEXKEY_LCD IS
PORT (
CLK: IN STD_LOGIC; -- 16 MHZ CLOCK
RESET: IN STD_LOGIC; -- MASTER RESET PIN
LCD_RW : OUT STD_LOGIC;
LCD_SELECT : OUT STD_LOGIC;
LCD_ENABLE : OUT STD_LOGIC;
ROW: IN STD_LOGIC_VECTOR(0 TO 3); -- THIS ARE THE ROW LINES
LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- GIVES REGISTERED DATA OUTPUT
COL: INOUT STD_LOGIC_VECTOR(0 TO 3));
END HEXKEY_LCD;
ARCHITECTURE HEXKEY_BEH OF HEXKEY_LCD IS
TYPE KEYPAD_STATE_TYPE IS (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE, WAIT_R_1); --
STATE NAMES
TYPE STATE_TYPE IS (INITIAL,DISPLAY,CLEAR,LOCATION,PUTCHAR);
SIGNAL STATE,NEXT_STATE: STATE_TYPE;
-- CLEAR SCREEN.
CONSTANT CLR: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000001";
-- DISPLAY ON, WITHOUT CURSOR.
CONSTANT DON: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00001100";
-- FUNCTION SET FOR 8-BIT DATA TRANSFER AND 2-LINE DISPLAY
CONSTANT SET: STD_LOGIC_VECTOR(7 DOWNTO 0) := "00111000";
--FREQUENCY DIVIDER
CONSTANT BIG_DELAY: INTEGER :=16;
CONSTANT SMALL_DELAY: INTEGER :=2;
CONSTANT REG_SETUP: INTEGER :=1;
SIGNAL CS, NS: KEYPAD_STATE_TYPE; -- SIGNALS FOR CURRENT AND NEXT STATES
SIGNAL DIV_REG: STD_LOGIC_VECTOR (16 DOWNTO 0); -- CLOCK DIVIDE REGISTER
SIGNAL DCLK,DDCLK: STD_LOGIC; -- THIS HAS THE DIVIDED CLOCK.
SIGNAL COL_REG_VALUE: STD_LOGIC_VECTOR (0 TO 3);
SIGNAL R1: STD_LOGIC; -- ROW DETECTION SIGNAL
SIGNAL KEY_VALUE: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL DATA: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
R1 <= ROW(3) OR ROW(2) OR ROW(1) OR ROW(0);

30
---------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) -------------------------------

SYNC_PROC: PROCESS (DCLK, RESET, KEY_VALUE) -- THIS IS THE SYNCHRONOUS PART
BEGIN
IF (RESET = '0') THEN -- YOU MUST HAVE A RESET FOR FSM TO SYNTHESIZE PROPERLY
CS <= WAIT_R_0;
ELSIF (DCLK'EVENT AND DCLK = '1') THEN
CS <= NS;
END IF;
END PROCESS;
COMB_PROC: PROCESS (CS, R1, COL_REG_VALUE) -- THIS IS THE COMBINATIONAL PART
BEGIN
CASE CS IS
---------------------------------------------------------------------------------------------------
WHEN WAIT_R_0 => -- WAITS TILL A BUTTON IS PRESSED
COL <= "1111"; -- KEEP ALL COLUMNS ACTIVATED
IF R1 = '1' THEN -- A BUTTON WAS PRESSED. BUT WHICH ONE?
NS <= C3; -- LET'S FIND OUT
ELSE
NS <= WAIT_R_0;
END IF;
---------------------------------------------------------------------------------------------------
WHEN C3 => --
COL <= "0001"; -- ACTIVATE COLUMN 3
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 3
NS <= C2; -- SO CHECK IF IT WAS IN COLUMN 2
ELSE NS <= FOUND; -- BUTTON WAS IN COLUMN 3
END IF;
---------------------------------------------------------------------------------------------------
WHEN C2 => --
ELSE
NS <= FOUND; -- BUTTON WAS IN COLUMN 2
END IF;
---------------------------------------------------------------------------------------------------
WHEN C1 => --
ELSE
END IF;
---------------------------------------------------------------------------------------------------
WHEN C0 => --
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 0 ??
NS <= WAIT_R_0; -- SO THE BUTTON MUST HAVE BEEN DEPRESSED FAST
ELSE
END IF;
---------------------------------------------------------------------------------------------------
WHEN FOUND => --
COL <= COL_REG_VALUE;
IF R1 = '0' THEN -- THIS MEANS BUTTON IS DEPRESSED
NS <= WAIT_R_0; -- SO GO BACK TO INITIAL STATE
ELSE
NS <= SAMPLE; -- OTHERWISE WRITE THE KEY VALUE TO DATA REGISTER
END IF;
---------------------------------------------------------------------------------------------------

31
WHEN SAMPLE => -- THIS STATE WILL GENERATE A SIGNAL WITH ONE CLOCK PERIOD
FOR SAMPLING
NS <= WAIT_R_1; -- OTHERWISE WAIT TILL BUTTON IS PRESSED
---------------------------------------------------------------------------------------------------
WHEN WAIT_R_1 => --
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS DEPRESSED
ELSE
END IF;
---------------------------------------------------------------------------------------------------
END CASE;
END PROCESS;
---------------------------------------------------------------------------------------------------
WRITE_DATA: PROCESS (DCLK, CS, KEY_VALUE) -- WRITE VALID DATA TO REGISTER
BEGIN
IF DCLK'EVENT AND DCLK = '0' THEN -- ON THE FALLING EDGE
IF CS = FOUND THEN
DATA <= KEY_VALUE;
END IF;
END IF;
END PROCESS; -- WRITE_DATA
---------------------------------------------------------------------------------------------------
COL_REG: PROCESS (DCLK, CS, COL) -- THIS IS THE COLUMN VALUE REGISTER
BEGIN
IF (DCLK'EVENT AND DCLK = '0') THEN -- REGISTER THE COL VALUE ON THE FALLING
EDGE
IF (CS = C3 OR CS = C2 OR CS = C1 OR CS = C0) THEN -- PROVIDED WE'RE IN STATES C3 THRU
C0 ONLY
COL_REG_VALUE <= COL; -- OTHERWISE THE COLUMN VALUE IS NOT VALID
END IF;
END IF;
END PROCESS; -- COL_REG
---------------------------------------------------------------------------------------------------
DECODER: PROCESS(ROW, COL_REG_VALUE) -- DECODES BINARY VALUE OF PRESSED
KEY FROM ROW AND
COLUMN
VARIABLE CODE: STD_LOGIC_VECTOR (0 TO 7);
BEGIN
CODE := (ROW & COL_REG_VALUE);
CASE CODE IS
-- COL
-- ROW 0 0123
WHEN "00010001" => KEY_VALUE <= ZERO;--KEY 0
WHEN "00010010" => KEY_VALUE <= ONE;--KEY 1
WHEN "00010100" => KEY_VALUE <= TWO;--KEY 2
WHEN "00011000" => KEY_VALUE <= THREE;--KEY 3
-- ROW 1
WHEN "00100001" => KEY_VALUE <= FOUR;--KEY 4
WHEN "00100010" => KEY_VALUE <= FIVE;--KEY 5
WHEN "00100100" => KEY_VALUE <= SIX;--KEY 6
WHEN "00101000" => KEY_VALUE <= SEVEN;--KEY 7
-- ROW 2
WHEN "01000001" => KEY_VALUE <= EIGHT;--KEY 8
WHEN "01000010" => KEY_VALUE <= NINE;--KEY 9
WHEN "01000100" => KEY_VALUE <= A;--KEY A
WHEN "01001000" => KEY_VALUE <= B;--KEY B
-- ROW 3

32
WHEN "10000001" => KEY_VALUE <= C;--KEY C

WHEN "10000010" => KEY_VALUE <= D;--KEY D
WHEN "10000100" => KEY_VALUE <= E;--KEY E
WHEN "10001000" => KEY_VALUE <= F;--KEY F
WHEN OTHERS => KEY_VALUE <= SPACE; -- JUST IN CASE
END CASE;
END PROCESS; -- DECODER
---------------------------- END OF FSM1 (KEYPAD SCANNER) ---------------------------------------
-- SELECT THE APPROPRIATE LINES FOR SETTING FREQUENCY
CLK_DIV: PROCESS (CLK, DIV_REG) -- CLOCK DIVIDER
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
DIV_REG <= DIV_REG + 1;
END IF;
END PROCESS;
DCLK <= DIV_REG(8);
DDCLK<=DIV_REG(10);
---------------------------- END OF CLOCK DIVIDER -------------------------------------------------
LCD_RW<='0';
PROCESS (DDCLK,RESET)
VARIABLE COUNT: INTEGER RANGE 0 TO BIG_DELAY;
VARIABLE C1 : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF RESET = '0' THEN
STATE<=INITIAL;
COUNT:=0;
LCD_ENABLE<='0';
LCD_SELECT<='0';
C1 := "01111111";
ELSIF DDCLK'EVENT AND DDCLK = '1' THEN
CASE STATE IS
WHEN INITIAL => -- TO SET THE FUNCTION
IF COUNT=REG_SETUP THEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=SET;
LCD_SELECT<='0';
IF COUNT=SMALL_DELAY THEN
STATE<=DISPLAY;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN DISPLAY => -- TO SET DISPLAY ON
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=DON;
LCD_SELECT<='0';
STATE<=CLEAR;COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN CLEAR => -- CLEAR THE SCREEN

33
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=CLR;
LCD_SELECT<='0';
IF COUNT=BIG_DELAY THEN
STATE<=LOCATION;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN LOCATION => -- CLEAR THE SCREEN
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
IF COUNT=0 THEN
IF C1="10001111" THEN
C1:="11000000";
ELSIF C1="11001111" THEN
C1:="10000000";
ELSE
C1:=C1+'1';
END IF;
END IF;
LCD_DATA <= C1 ;
LCD_SELECT<='0';
STATE<=PUTCHAR;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
WHEN PUTCHAR=> -- DISPLAY THE CHARACTER ON THE LCD
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
CASE C1 IS
WHEN "10000000" => LCD_DATA<= H ;--SIGLE LINE
WHEN "10000001" => LCD_DATA<= E ;--SIGLE LINE
WHEN "10000010" => LCD_DATA<= X ;--SIGLE LINE
WHEN "10000011" => LCD_DATA<= SPACE ;--SIGLE LINE
WHEN "10000101" => LCD_DATA<= K ;--SIGLE LINE
WHEN "10000111" => LCD_DATA<= Y ;--SIGLE LINE
WHEN "10001000" => LCD_DATA<= B ;
WHEN "10001001" => LCD_DATA<= O ;
WHEN "10001010" => LCD_DATA<= A ;
WHEN "10001011" => LCD_DATA<= R ;
WHEN "10001100" => LCD_DATA<= D ;
WHEN "10001101" => LCD_DATA<= SPACE ;
WHEN "10001111" => LCD_DATA<= SPACE;
WHEN "11000000" => LCD_DATA<= K ;--SIGLE LINE

34
WHEN "11000010" => LCD_DATA<= Y ;--SIGLE LINE

WHEN "11000011" => LCD_DATA<= P ;--SIGLE LINE
WHEN "11000100" => LCD_DATA<= R ;--SIGLE LINE
WHEN "11000110" => LCD_DATA<= S ;--SIGLE LINE
WHEN "11001000" => LCD_DATA<= E ;
WHEN "11001001" => LCD_DATA<= D ;
-- WHEN "11001011" => LCD_DATA<= RIGHT_ARROW ;
WHEN "11001101" => LCD_DATA<= DATA ;
END CASE ;
LCD_SELECT<='1';
STATE<=LOCATION;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
END CASE;
END IF;
END PROCESS;
END HEXKEY_BEH;
===============================================================
NET "CLK" LOC = "P18" ;
NET "COL<0>" LOC = "P139" ;
NET "COL<1>" LOC = "P134" ;
NET "COL<2>" LOC = "P136" ;
NET "COL<3>" LOC = "P132" ;
NET "LCD_DATA<0>" LOC = "P21" ;
NET "LCD_ENABLE" LOC = "P19" ;
NET "LCD_RW" LOC = "P20" ;
NET "LCD_SELECT" LOC = "P4" ;
NET "RESET" LOC = "P41" ;
NET "ROW<0>" LOC = "P126" ;
NET "ROW<1>" LOC = "P129" ;
NET "ROW<2>" LOC = "P124" ;
NET "ROW<3>" LOC = "P122" ;
===============================================================

35
1b. WRITE VHDL CODE TO DISPLAY MESSAGES ON THE GIVEN SEVEN SEGMENT
DISPLAY ACCEPTING HEX KEY PAD INPUT DATA.
AIM: TO DISPLAY THE MESSAGE ON THE SEVEN SEGMENT DISPLAY BY ACCEPTING HEX
KEY PAD INPUT
DATA.
PROCEDURE:
1. Make the connection between frc5 of the fpga board to the seven-segment connector of the vtu card1.
2. Make the connection between frc4 of the fpga board to the keyboard connector of the vtu card1.
3. Make the connection between frc6 of the fpga board to the dipswitch connector of the vtu card1.
4. Connect the downloading cable and power supply to the fpga board.
5. Then open the xilinx impact software (refer ise flow) select the slave serial mode and select the
respective bit file and click program.
6. Make the reset switch on (active low).
7. Press the hex keys and analyze the data.
VHDL CODING
------------------------------------
--CODE FOR SIMULATING 16 KEYS USING
--KEYBOARD PROVIDED ON SPARTAN BOARD
------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY KEY_40 IS
PORT ( SCAN_L : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
READ_L_IN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CLK : IN STD_LOGIC;
DISP_CNT: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
DISP : OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END KEY_40;
ARCHITECTURE BEHAVIORAL OF KEY_40 IS

SIGNAL DISP1 : STD_LOGIC_VECTOR(6 DOWNTO 0);
SIGNAL SCAN_L_SIG : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CLK_DIV : STD_LOGIC_VECTOR( 11 DOWNTO 0);
SIGNAL CLK_4K : STD_LOGIC;
SIGNAL CNT_2BIT : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL READ_L : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
---------------------------
--CLOCK DIVISION TO 4KHZ
--------------------------
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
CLK_DIV <= CLK_DIV + '1';
END IF;
END PROCESS;
---------------------------
CLK_4K <= CLK_DIV(11);
---------------------------
-- 2 BIT COUNTER
--------------------------
PROCESS(CLK_4K)
BEGIN

36
IF CLK_4K = '1' AND CLK_4K'EVENT THEN

CNT_2BIT <= CNT_2BIT + '1';
END IF;
END PROCESS;
--------------------------
--------------------------
-- SCANNING THE LINES
--------------------------
PROCESS(CNT_2BIT)
BEGIN
CASE CNT_2BIT IS
WHEN "00" => SCAN_L_SIG <= "0001";
WHEN "01" => SCAN_L_SIG <= "0010";
WHEN "10" => SCAN_L_SIG <= "0100";
WHEN "11" => SCAN_L_SIG <= "1000";
END CASE;
END PROCESS;
------------------------------
READ_L <= READ_L_IN;
SCAN_L <= SCAN_L_SIG;
DISP_CNT <= "1110";
-------------------------------
--READING THE LINES
-------------------------------
PROCESS(SCAN_L_SIG,READ_L)
BEGIN
CASE SCAN_L_SIG IS
WHEN "0001" =>
CASE READ_L IS
WHEN "0001" => DISP1 <= "1111110";
WHEN "0010" => DISP1 <= "0110011";
WHEN "0100" => DISP1 <= "1111111";
WHEN "1000" => DISP1 <= "1001110";
WHEN OTHERS => DISP1 <= "0000000";
END CASE;
WHEN "0010" =>
CASE READ_L IS
WHEN "0001" => DISP1 <= "0110000";
WHEN "0010" => DISP1 <= "1011011";
WHEN "0100" => DISP1 <= "1111011";
WHEN "1000" => DISP1 <= "0111101";
WHEN OTHERS=> DISP1 <= "0000000";
END CASE;
WHEN "0100" =>
CASE READ_L IS
WHEN "0001" => DISP1 <= "1101101";
WHEN "0010" => DISP1 <= "1011111";
WHEN "0100" => DISP1 <= "1110111";
WHEN "1000" => DISP1 <= "1001111";
END CASE;
WHEN "1000" =>
CASE READ_L IS
WHEN "0001" => DISP1 <= "1111001";
WHEN "0010" => DISP1 <= "1110000";
WHEN "0100" => DISP1 <= "0011111";

37
WHEN "1000" => DISP1 <= "1000111";

END CASE;
WHEN OTHERS=> NULL;
END CASE;
END PROCESS;
DISP<= DISP1;
----------------------------
END BEHAVIORAL;
===============================================================

NET "CLK" LOC = "P18";
NET "DISP_CNT<0>" LOC = "P30";
NET "DISP<0>" LOC = "P26";
NET "READ_L_IN<0>" LOC = "P122";
NET "SCAN_L<0>" LOC = "P132";
===============================================================
2a. WRITE A VHDL CODE TO CONTROL SPEED, DIRECTION OF DC MOTOR.

AIM: TO CONTROL SPEED AND DIRECTION OF DC MOTOR.
PROCEDURE:
1. MAKE THE CONNECTION BETWEEN FRC9 OF THE FPGA BOARD TO THE DC MOTOR
CONNECTOR OF THE VTU CARD2.
2. MAKE THE CONNECTION BETWEEN FRC7 OF THE FPGA BOARD TO THE KEYBOARD
3. MAKE THE CONNECTION BETWEEN FRC1 OF THE FPGA BOARD TO THE DIP SWITCH
4. CONNECT THE DOWNLOADING CABLE AND POWER SUPPLY TO THE FPGA BOARD.
5. THEN OPEN THE XILINX IMPACT SOFTWARE (REFER ISE FLOW) SELECT THE SLAVE
SERIAL MODE AND SELECT THE RESPECTIVE BIT FILE AND CLICK PROGRAM.
6. MAKE THE RESET SWITCH ON (ACTIVE LOW).
7. PRESS THE HEX KEYS AND ANALYZE THE SPEED CHANGES.
VHDL CODE
library IEEE;
---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

38
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY DCM IS
PORT ( CLK,DIR,RST : IN STD_LOGIC;
ROW : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
RLY : OUT STD_LOGIC;
PWM : OUT STD_LOGIC_VECTOR (1 DOWNTO 0));
END DCM;
ARCHITECTURE BEHAVIORAL OF DCM IS

SIGNAL CNTR:STD_LOGIC_VECTOR(7 DOWNTO 0):="11111110";
SIGNAL DCLK:STD_LOGIC_VECTOR(16 DOWNTO 0);
SIGNAL TICK:STD_LOGIC;
SIGNAL DUTYCYCLE:INTEGER RANGE 0 TO 255;
BEGIN
PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK)THEN
DCLK<=DCLK+'1';
END IF;
END PROCESS;
TICK<=ROW(0)AND ROW(1)AND ROW(2)AND ROW(3);
PROCESS(TICK)
BEGIN
IF FALLING_EDGE(TICK)THEN
CASE ROW IS
WHEN"1110"=>DUTYCYCLE<=255;
WHEN OTHERS=>DUTYCYCLE<=100;
END CASE;
END IF;
END PROCESS;
PROCESS(RST,DCLK(16))
BEGIN
IF RST='0' THEN
CNTR<=(OTHERS=>'0');
PWM<="01";
ELSIF RISING_EDGE(DCLK(16))THEN
CNTR<=CNTR+'1';
IF CNTR>=DUTYCYCLE THEN
PWM(1)<='0';
ELSE
PWM(1)<='1';
END IF;
END IF;
END PROCESS;
RLY<=DIR;
END BEHAVIORAL;
===============================================================
NET "PWM<0>" LOC = "P5" ;

39
NET "PWM<1>" LOC = "P141" ;

NET "RLY" LOC = "P3" ;
NET "ROW<0>" LOC = "P64" ;
NET "ROW<1>" LOC = "P63" ;
NET "ROW<2>" LOC = "P60" ;
NET "ROW<3>" LOC = "P58" ;
===============================================================
2b. WRITE A VHDL CODE TO CONTROL SPEED, DIRECTION OF STEPPER MOTOR.

AIM: TO CONTROL SPEED AND DIRECTION OF STEPPER MOTOR.
PROCEDURE:
1. MAKE THE CONNECTION BETWEEN FRC9 OF THE FPGA BOARD TO THE STEPPER MOTOR
7. PRESS THE HEX KEYS AND ANALYZE THE SPEED CHANGES.
VHDL CODE
library IEEE;
---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
ENTITY STEPPER IS
PORT ( RESET : IN STD_LOGIC;
DIR : IN STD_LOGIC;
CLOCK : IN STD_LOGIC;
STEP_SEQ : INOUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END STEPPER;
ARCHITECTURE BEHAVIORAL OF STEPPER IS

SIGNAL CLK_DIV : STD_LOGIC_VECTOR(20 DOWNTO 0);
BEGIN
PROCESS(CLOCK)
BEGIN
IF RISING_EDGE (CLOCK) THEN
CLK_DIV <= CLK_DIV + '1';
END IF;
END PROCESS;
PROCESS(CLK_DIV(16),DIR,RESET)
BEGIN
IF RESET='0' THEN
STEP_SEQ<="0001";

40
ELSIF RISING_EDGE(CLK_DIV(16)) THEN

IF DIR = '0' THEN
STEP_SEQ<=STEP_SEQ(2 DOWNTO 0) & STEP_SEQ(3);
ELSE
STEP_SEQ<=STEP_SEQ(0) & STEP_SEQ(3 DOWNTO 1);
END IF;
END IF;
END PROCESS;
END BEHAVIORAL;
===============================================================
NET "CLK" LOC = "P18"; NET "DOUT<0>" LOC = "P7";
NET "DOUT<1>" LOC = "P5"; NET "DOUT<2>" LOC = "P3";
NET "DOUT<3>" LOC = "P141"; NET "RESET" LOC = "P74";
===============================================================
3. WRITE A VHDL CODE TO GENERATE WAVEFORMS USING DAC CHANGE THE

FREQUENCY ANDAMPLITUDE.
AIM: TO GENERATE SINE WAVE USING DAC CHANGE THE FREQUENCY AND AMPLITUDE.
PROCEDURE:
1. MAKE THE CONNECTION BETWEEN FRC5 OF THE FPGA BOARD TO THE DAC
5. MAKE THE RESET SWITCH ON (ACTIVE LOW) AND ANALYZE THE DATA.
VHDL CODE
a. Square wave generation
library IEEE;
ENTITY SQUARE IS
CLK : IN STD_LOGIC;
DAC_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END SQUARE;
ARCHITECTURE BEHAVIORAL OF SQUARE IS

SIGNAL TEMP:STD_LOGIC_VECTOR(4 DOWNTO 0);
SIGNAL COUNT:STD_LOGIC_VECTOR(0 TO 7);
BEGIN
PROCESS(CLK)
BEGIN
TEMP<=TEMP+1;
END IF;
END PROCESS;
PROCESS(RESET,TEMP)
BEGIN
IF RESET='1' THEN
COUNT<="00000000";
ELSIF RISING_EDGE(TEMP(4)) THEN

41
COUNT<=COUNT+1;
IF COUNT<128 THEN
DAC_OUT<="00000000";
ELSE
DAC_OUT<="11111111";
END IF;
END IF;
END PROCESS;
END BEHAVIORAL;
b. Triangular wave generation
library IEEE;
ENTITY TRIANGLE_WAVE IS
CLK : IN STD_LOGIC;
END TRIANGLE_WAVE;
ARCHITECTURE BEHAVIORAL OF TRIANGLE_WAVE IS

SIGNAL TEMP : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUNTER: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL K : BIT ;
BEGIN
PROCESS(CLK)
BEGIN
TEMP <= TEMP + '1' ;
END IF;
END PROCESS;
PROCESS(TEMP(3))
BEGIN
IF RESET='0' THEN
COUNTER <= "00000000";
IF COUNTER = 254 THEN
K <= '1';
ELSIF COUNTER = 1 THEN
K <= '0';
END IF;
IF K = '0' THEN
COUNTER <= COUNTER + 1;
ELSE
COUNTER <= COUNTER - 1;
END IF;
END IF;
END PROCESS;
DAC_OUT <=COUNTER;
END BEHAVIORAL;
c. Ramp wave generation
library IEEE;

42
ENTITY RAMP_WAVE IS
PORT ( CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
END RAMP_WAVE;
ARCHITECTURE BEHAVIORAL OF RAMP_WAVE IS

SIGNAL COUNTER : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(CLK)
BEGIN
END IF;
END PROCESS;
PROCESS(TEMP(3))
BEGIN
IF RESET='0' THEN
COUNTER <= "00000000";
COUNTER <= COUNTER + 1 ;
END IF;
END PROCESS;
DAC_OUT <=COUNTER;
END BEHAVIORAL;
d. Sawtooth wave generation
library IEEE;
ENTITY SAWTOOTH_WAVE IS
CLOCK : IN STD_LOGIC;
END SAWTOOTH_WAVE;
ARCHITECTURE BEHAVIORAL OF SAWTOOTH_WAVE IS

SIGNAL TEMP:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL COUNTER:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
CLOCKDIV:PROCESS(CLOCK)
BEGIN
IF RISING_EDGE(CLOCK) THEN
TEMP<=TEMP+1;
END IF;
END PROCESS;
SAWTOOTH:PROCESS(RESET,TEMP)

43
BEGIN
IF RESET='0' THEN
COUNTER<=(OTHERS=>'0');
COUNTER<=COUNTER+1;
END IF;
END PROCESS;
DAC_OUT<=COUNTER;
END BEHAVIORAL;
e. Staircase wave generation
library IEEE;
ENTITY STAIRCASE IS
PORT ( CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
END STAIRCASE;
ARCHITECTURE BEHAVIORAL OF STAIRCASE IS

SIGNAL COUNTER : STD_LOGIC_VECTOR(0 TO 7);
SIGNAL COUNT:INTEGER RANGE 0 TO 200;
BEGIN
PROCESS(CLK)
BEGIN
END IF;
END PROCESS;
PROCESS(TEMP(3))
BEGIN
IF RESET='0' THEN
COUNTER <= "00000000";
COUNT<=COUNT+1;
IF COUNT=60 THEN
COUNTER <= COUNTER + 20 ;
COUNT<=0;
END IF;
END IF;
END PROCESS;
DAC_OUT <=COUNTER;
END BEHAVIORAL;
4. WRITE A VHDL CODE TO CONTROL EXTERNAL LIGHTS USING RELAYS.

AIM: TO CONTROL EXTERNAL LIGHTS USING RELAYS.
PROCEDURE:

44
1. MAKE THE CONNECTION BETWEEN FRC9 OF THE FPGA BOARD TO THE EXTERNAL
LIGHT CONNECTOR OF THE VTU CARD2.
5. MAKE THE RESET SWITCH ON (ACTIVE LOW) AND ANALYZE THE DATA.
VHDL CODE
LIBRARY IEEE;
ENTITY EXTLIGHT IS
PORT ( CNTRL1,CNTRL2 : IN STD_LOGIC;
LIGHT : OUT STD_LOGIC);
END EXTLIGHT;
ARCHITECTURE BEHAVIORAL OF EXTLIGHT IS
BEGIN
LIGHT<= CNTRL1 OR CNTRL2 ;
END BEHAVIORAL;
===============================================================
UCF FILE(USER CONSTRAINT

NET "CNTRL1" LOC = "P74";
NET "CNTRL2" LOC = "P75";
NET "LIGHT" LOC = "P7";
5a. WRITE A VHDL CODE TO ACCEPT 8 CHANNEL ANALOG SIGNAL, TEMPERATURE

SENSORS AND DISPLAY THE DATA ON LCD PANEL OR SEVEN SEGMENT DISPLAY.
AIM: TO ACCEPT 8 CHANNEL ANALOG SIGNAL, AND DISPLAY THE DATA ON LCD PANEL
DISPLAY.
PROCEDURE:
1. MAKE THE CONNECTION BETWEEN FRC5 OF THE FPGA BOARD TO THE LCD DISPLAY
2. MAKE THE CONNECTION BETWEEN FRC10 OF THE FPGA BOARD TO THE ADC
4. SHORT THE JUMPER J1 TO THE VIN TO GET THE ANALOG SIGNAL.
8. PRESS THE HEX KEYS AND ANALYZE THE DATA.
VHDL CODING
LIBRARY IEEE;

45
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
ENTITY ADC_LCD IS
PORT ( CLK: IN STD_LOGIC; -- 4 MHZ CLOCK
RESET: IN STD_LOGIC; -- MASTER RESET PIN
INTR: IN STD_LOGIC;
ADC_OUT: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CS,RD,WR:OUT STD_LOGIC;
LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); -- GIVES REGISTERED DATA OUTPUT
END ADC_LCD;
ARCHITECTURE ADC_BEH OF ADC_LCD IS
-- CLEAR SCREEN.
--FREQUENCY DIVIDER
SIGNAL COUNTER : STD_LOGIC_VECTOR(18 DOWNTO 0);
SIGNAL CLK_DIV :STD_LOGIC;
SIGNAL DIGITAL_DATA1,DATA1,DATA2: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DIGITAL_DATA : INTEGER RANGE 0 TO 255;
SIGNAL NTR :STD_LOGIC;
BEGIN
IBUF_INST : IBUF
-- EDIT THE FOLLOWING GENERIC TO SPECIFY THE I/O STANDARD FOR THIS PORT.
GENERIC MAP (
IOSTANDARD => "LVCMOS25")
PORT MAP (
O => NTR, -- BUFFER OUTPUT
I => INTR -- BUFFER INPUT (CONNECT DIRECTLY TO TOP-LEVEL PORT));
PROCESS(CLK)
BEGIN
IF CLK='1' AND CLK'EVENT THEN
COUNTER<=COUNTER+'1';
END IF;
END PROCESS;
CLK_DIV<=COUNTER(7);
CS <='0';
WR <=NTR;
DIGITAL_DATA1 <= ADC_OUT ;
RD <='0';
DIGITAL_DATA<=CONV_INTEGER(DIGITAL_DATA1) ;
PROCESS(DIGITAL_DATA)
BEGIN
CASE (DIGITAL_DATA) IS
WHEN 0 TO 100 => DATA1 <= ONE ; DATA2 <= NINE ;
WHEN 101 TO 110 => DATA1 <= TWO ; DATA2 <= ZERO ;
WHEN 111 TO 120 => DATA1 <= TWO ; DATA2 <= ONE ;
WHEN 121 TO 130 => DATA1 <= TWO ; DATA2 <= TWO ;
WHEN 131 TO 140 => DATA1 <= TWO ; DATA2 <= THREE ;

46
WHEN 141 TO 150 => DATA1 <= TWO ; DATA2 <= FOUR ;
WHEN 151 TO 160 => DATA1 <= TWO ; DATA2 <= FIVE ;
WHEN 161 TO 170 => DATA1 <= TWO ; DATA2 <= SIX ;
WHEN 171 TO 180 => DATA1 <= TWO ; DATA2 <= SEVEN ;
WHEN 181 TO 190 => DATA1 <= TWO ; DATA2 <= EIGHT ;
WHEN 191 TO 200 => DATA1 <= TWO ; DATA2 <= NINE ;
WHEN 201 TO 205 => DATA1 <= THREE ; DATA2 <= ZERO ;
WHEN 206 TO 210 => DATA1 <= THREE ; DATA2 <= ONE ;
WHEN 211 TO 215 => DATA1 <= THREE ; DATA2 <= TWO ;
WHEN 216 TO 220 => DATA1 <= THREE ; DATA2 <= THREE ;
WHEN 221 TO 225 => DATA1 <= THREE ; DATA2 <= FOUR ;
WHEN 226 TO 230 => DATA1 <= THREE ; DATA2 <= FIVE ;
WHEN 231 TO 235 => DATA1 <= THREE ; DATA2 <= SIX ;
WHEN 236 TO 240 => DATA1 <= THREE ; DATA2 <= SEVEN ;
WHEN 241 TO 245 => DATA1 <= THREE ; DATA2 <= EIGHT ;
WHEN 246 TO 250 => DATA1 <= THREE ; DATA2 <= NINE ;
WHEN OTHERS => DATA1 <= FOUR ; DATA2 <= ZERO ;
END CASE;
END PROCESS;
LCD_RW<='0';
PROCESS (CLK_DIV,RESET)
BEGIN
IF RESET = '1' THEN
STATE<=INITIAL;
COUNT:=0;
LCD_ENABLE<='0';
LCD_SELECT<='0';
C1 := "01111111";
ELSIF CLK_DIV'EVENT AND CLK_DIV = '1' THEN
CASE STATE IS
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=SET;
LCD_SELECT<='0';
STATE<=DISPLAY;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=DON;
LCD_SELECT<='0';
STATE<=CLEAR;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;

47

LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
LCD_DATA<=CLR;
LCD_SELECT<='0';
STATE<=LOCATION;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
LCD_ENABLE<='1';
ELSE
LCD_ENABLE<='0';
END IF;
IF COUNT=0 THEN
IF C1="10001111" THEN
C1:="10000000";
ELSE
C1:=C1+'1';
END IF;
END IF;
LCD_DATA <= C1 ;
LCD_SELECT<='0';
STATE<=PUTCHAR;
COUNT:=0; ELSE
COUNT:=COUNT+1;
END IF;
LCD_ENABLE<='1';
ELSE LCD_ENABLE<='0';
END IF;
CASE C1 IS
WHEN "10000000" => LCD_DATA<= A ;
WHEN "10000001" => LCD_DATA<= D ;
WHEN "10000010" => LCD_DATA<= C ;
WHEN "10000100" => LCD_DATA<= V ;
WHEN "10000101" => LCD_DATA<= O ;
WHEN "10000110" => LCD_DATA<= L ;
WHEN "10000111" => LCD_DATA<= T ;
WHEN "10001000" => LCD_DATA<= A ;
WHEN "10001001" => LCD_DATA<= G ;
WHEN "10001010" => LCD_DATA<= E ;
WHEN "10001100" => LCD_DATA<= EQUAL ;
WHEN "10001101" => LCD_DATA<= DATA1 ;
WHEN "10001110" => LCD_DATA<= DOT ;
WHEN "10001111" => LCD_DATA<= DATA2;

48

END CASE ;
LCD_SELECT<='1';
STATE<=LOCATION;
COUNT:=0;
ELSE
COUNT:=COUNT+1;
END IF;
END CASE;
END IF;
END PROCESS;
END ADC_BEH;
===============================================================
NET "CS" LOC = "P6" ;
NET "INTR" LOC = "P12" ;
NET "ADC_OUT<0>" LOC = "P13" ;
NET "WR" LOC = "P11";
NET "RD" LOC = "P10";
NET "LCD_RW" LOC = "P20";
NET "LCD_SELECT" LOC = "P4";
NET "LCD_ENABLE" LOC = "P19" ;
===============================================================
6. WRITE A VHDL CODE TO SIMULATE ELEVATOR OPERATIONS.
AIM: TO OPERATE ELEVATOR AND OBSERVE THE SIMULATION RESULTS ON LCD.
PROCEDURE:

49
1. MAKE THE CONNECTION BETWEEN FRC5 OF THE FPGA BOARD TO THE LCD DISPLAY
7. PRESS THE HEX KEYS AND ANALYZE THE DATA.
VHDL CODE
LIBRARY IEEE;
ENTITY ELEVATOR IS
GENERIC(BITS : INTEGER := 8 ); -- NUMBER OF BITS USED FOR DUTY CYCLE.
-- ALSO DETERMINES PWM PERIOD.
PORT ( CLK: IN STD_LOGIC; -- 4 MHZ CLOCK
RESET,EN: IN STD_LOGIC; -- MASTER RESET PIN
PWM : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ROW: IN STD_LOGIC_VECTOR(0 TO 3); -- THIS ARE THE ROW LINES
LCD_DATA: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- GIVES REGISTERED DATA OUTPUT
COL: INOUT STD_LOGIC_VECTOR(0 TO 3));
END ELEVATOR;
ARCHITECTURE RTL OF ELEVATOR IS
SIGNAL COUNTER : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0):="00000000";
TYPE KEYPAD_STATE_TYPE IS (WAIT_R_0, C3, C2, C1, C0, FOUND, SAMPLE, WAIT_R_1);
-- STATE NAMES
-- CLEAR SCREEN.
--FREQUENCY DIVIDER
SIGNAL CS, NS: KEYPAD_STATE_TYPE; -- SIGNALS FOR CURRENT AND NEXT STATES
SIGNAL DUTY_CYCLE,DUTY_CYCLE1 : STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0);
SIGNAL DIV_REG: STD_LOGIC_VECTOR (22 DOWNTO 0); -- CLOCK DIVIDE REGISTER
SIGNAL DCLK,DDCLK: STD_LOGIC; -- THIS HAS THE DIVIDED CLOCK.
SIGNAL COL_REG_VALUE: STD_LOGIC_VECTOR (0 TO 3);
SIGNAL R1,CLK_D,START,STOP: STD_LOGIC; -- ROW DETECTION SIGNAL
SIGNAL KEY_VALUE1,FLOOR,KEY_VALUE: INTEGER RANGE 0 TO 15;
SIGNAL DATA,DATA1,FLOOR_NUM: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL TEMP1,TEMP2,TEMP3,TEMP4: STD_LOGIC_VECTOR (7 DOWNTO 0);
SIGNAL TEMP5,TEMP6,TEMP7,TEMP8: STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
--CLK_OUT <= DCLK;

50
R1 <= ROW(3) OR ROW(2) OR ROW(1) OR ROW(0);

---------------------------- BEGINING OF FSM1 (KEYPAD SCANNER) -------------------------------
SYNC_PROC: PROCESS (DCLK, RESET, KEY_VALUE) -- THIS IS THE SYNCHRONOUS PART
BEGIN
IF (RESET = '0') THEN -- YOU MUST HAVE A RESET FOR FSM TO SYNTHESIZE PROPERLY
CS <= WAIT_R_0;
ELSIF (DCLK'EVENT AND DCLK = '1') THEN
CS <= NS;
END IF; END PROCESS;
COMB_PROC: PROCESS (CS, R1, COL_REG_VALUE) -- THIS IS THE COMBINATIONAL PART
BEGIN
CASE CS IS
WHEN WAIT_R_0 => -- WAITS TILL A BUTTON IS PRESSED
COL <= "1111"; -- KEEP ALL COLUMNS ACTIVATED
IF R1 = '1' THEN -- A BUTTON WAS PRESSED. BUT WHICH ONE?
NS <= C3; -- LET'S FIND OUT
ELSE
NS <= WAIT_R_0;
END IF;
---------------------------------------------------------------------------------------------------
WHEN C3 => --
ELSE NS <= FOUND; -- BUTTON WAS IN COLUMN 3
END IF;
---------------------------------------------------------------------------------------------------
WHEN C2 => --
ELSE
END IF;
---------------------------------------------------------------------------------------------------
WHEN C1 => --
ELSE
END IF;
---------------------------------------------------------------------------------------------------
WHEN C0 => --
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS NOT IN COLUMN 0 ??
NS <= WAIT_R_0; -- SO THE BUTTON MUST HAVE BEEN DEPRESSED FAST
ELSE
END IF;
---------------------------------------------------------------------------------------------------
WHEN FOUND => --
IF R1 = '0' THEN -- THIS MEANS BUTTON IS DEPRESSED
ELSE
NS <= SAMPLE; -- OTHERWISE WRITE THE KEY VALUE TO DATA REGISTER
END IF;
---------------------------------------------------------------------------------------------------

51
WHEN SAMPLE => -- THIS STATE WILL GENERATE A SIGNAL WITH ONE CLOCK PERIOD
FOR SAMPLING
---------------------------------------------------------------------------------------------------
WHEN WAIT_R_1 => --
IF R1 = '0' THEN -- THIS MEANS BUTTON WAS DEPRESSED
ELSE
END IF;
---------------------------------------------------------------------------------------------------
END CASE;
END PROCESS;
---------------------------------------------------------------------------------------------------
WRITE_DATA: PROCESS (DCLK, CS, KEY_VALUE) -- WRITE VALID DATA TO REGISTER
BEGIN
IF DCLK'EVENT AND DCLK = '0' THEN -- ON THE FALLING EDGE
IF CS = FOUND THEN
KEY_VALUE <= KEY_VALUE1;
END IF;
END IF;
END PROCESS; -- WRITE_DATA
---------------------------------------------------------------------------------------------------
COL_REG: PROCESS (DCLK, CS, COL) -- THIS IS THE COLUMN VALUE REGISTER
BEGIN
IF (DCLK'EVENT AND DCLK = '0') THEN -- REGISTER THE COL VALUE ON THE FALLING
EDGE
IF (CS = C3 OR CS = C2 OR CS = C1 OR CS = C0) THEN -- PROVIDED WE'RE IN STATES C3 THRU
C0 ONLY
COL_REG_VALUE <= COL; -- OTHERWISE THE COLUMN VALUE IS NOT VALID
END IF;
END IF;
END PROCESS; -- COL_REG
---------------------------------------------------------------------------------------------------
DECODER: PROCESS(ROW, COL_REG_VALUE) -- DECODES BINARY VALUE OF PRESSED
KEY FROM ROW AND
COLUMN
VARIABLE CODE: STD_LOGIC_VECTOR (0 TO 7);
BEGIN
CODE := (ROW & COL_REG_VALUE);
CASE CODE IS
-- COL
-- ROW 0 0123
WHEN "00010001" => KEY_VALUE1 <= 0;
WHEN "00010010" => KEY_VALUE1 <= 1;
WHEN "00010100" => KEY_VALUE1 <= 2;
WHEN "00011000" => KEY_VALUE1 <= 3;
-- ROW 1
WHEN "00100001" => KEY_VALUE1 <= 4;
WHEN "00100010" => KEY_VALUE1 <= 5;
WHEN "00100100" => KEY_VALUE1 <= 6;
WHEN "00101000" => KEY_VALUE1 <= 7;
-- ROW 2
WHEN "01000001" => KEY_VALUE1 <= 8;
WHEN "01000010" => KEY_VALUE1 <= 9;
WHEN "01000100" => KEY_VALUE1 <= 10;
WHEN "01001000" => KEY_VALUE1 <= 11;
-- ROW 3

52
WHEN "10000001" => KEY_VALUE1 <= 12;

WHEN "10000010" => KEY_VALUE1 <= 13;
WHEN "10000100" => KEY_VALUE1 <= 14;
WHEN "10001000" => KEY_VALUE1 <= 15;
WHEN OTHERS => KEY_VALUE1 <= 0;
END CASE;
END PROCESS; -- DECODER
---------------------------- END OF FSM1 (KEYPAD SCANNER) ---------------------------------------
-- SELECT THE APPROPRIATE LINES FOR SETTING FREQUENCY
CLK_DIV: PROCESS (CLK, DIV_REG) -- CLOCK DIVIDER
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
DIV_REG <= DIV_REG + 1;
END IF;
END PROCESS;
DCLK <= DIV_REG(8);
DDCLK<=DIV_REG(10);
CLK_D<=DIV_REG(22);
---------------------------- END OF CLOCK DIVIDER -------------------------------------------------
LCD_RW<='0';
PROCESS (DDCLK,RESET)
BEGIN
IF RESET = '0' THEN
STATE<=INITIAL;
COUNT:=0;
LCD_ENABLE<='0';
LCD_SELECT<='0';
C1 := "01111111";
ELSIF DDCLK'EVENT AND DDCLK = '1' THEN
CASE STATE IS
LCD_ENABLE<='1';
END IF;
LCD_DATA<=SET;
LCD_SELECT<='0';
STATE<=DISPLAY;
COUNT:=0;
ELSE COUNT:=COUNT+1;
END IF;
LCD_ENABLE<='1';
END IF;
LCD_DATA<=DON;
LCD_SELECT<='0';
STATE<=CLEAR;
COUNT:=0;
END IF;
LCD_ENABLE<='1';

53
END IF;
LCD_DATA<=CLR;
LCD_SELECT<='0';
STATE<=LOCATION;
COUNT:=0;
END IF;
LCD_ENABLE<='1';
END IF;
IF COUNT=0 THEN
IF C1="10001111" THEN
C1:="11000000";
ELSIF C1="11001111" THEN
C1:="10000000";
ELSE C1:=C1+'1';
END IF;
END IF;
LCD_DATA <= C1;
LCD_SELECT<='0';
STATE<=PUTCHAR;
COUNT:=0;
END IF;
LCD_ENABLE<='1';
END IF;
CASE C1 IS
WHEN "10000000" => LCD_DATA<= F ;--SIGLE LINE
WHEN "10000001" => LCD_DATA<= L ;--SIGLE LINE
WHEN "10000010" => LCD_DATA<= O ;--SIGLE LINE
WHEN "10000011" => LCD_DATA<= O ;--SIGLE LINE
WHEN "10000100" => LCD_DATA<= R ;--SIGLE LINE
WHEN "10000110" => LCD_DATA<= N ;--SIGLE LINE
WHEN "10000111" => LCD_DATA<= U ;--SIGLE LINE
WHEN "10001000" => LCD_DATA<= M ;
WHEN "10001001" => LCD_DATA<= B ;
WHEN "10001010" => LCD_DATA<= E ;
WHEN "10001011" => LCD_DATA<= R ;
WHEN "10001101" => LCD_DATA<= EQUAL ;
WHEN "10001110" => LCD_DATA<= FLOOR_NUM ;
WHEN "11000001" => LCD_DATA<= T ;--SIGLE LINE
WHEN "11000010" => LCD_DATA<= A ;--SIGLE LINE
WHEN "11000011" => LCD_DATA<= T ;--SIGLE LINE
WHEN "11000100" => LCD_DATA<= U ;--SIGLE LINE
WHEN "11000111" => LCD_DATA<= TEMP1 ;--SIGLE LINE
WHEN "11001000" => LCD_DATA<= TEMP2 ;

54

END CASE ;
LCD_SELECT<='1';
STATE<=LOCATION;
COUNT:=0;
END IF; END CASE; END IF; END PROCESS;
PROCESS(CLK_D,RESET)
VARIABLE COU : STD_LOGIC_VECTOR(1 DOWNTO 0);
VARIABLE START,STOP: STD_LOGIC; -- ROW DETECTION SIGNAL
BEGIN
IF RESET='0' THEN
COU:="00";
TEMP1 <= L ;
TEMP2 <= I ;
TEMP3 <= F ;
TEMP4 <= T ;
TEMP5 <= I ;
TEMP6 <= D ;
TEMP7 <= L ;
TEMP8 <= E ;
FLOOR_NUM <= ZERO ;
ELSIF RISING_EDGE(CLK_D) THEN
CASE KEY_VALUE IS
WHEN 0 => FLOOR_NUM <= ZERO ;
FLOOR <=0;
WHEN 1 => FLOOR_NUM <= ONE ;
FLOOR <=1;
WHEN 2 => FLOOR_NUM <= TWO ;
FLOOR <=2;
WHEN 3 => FLOOR_NUM <= THREE ;
FLOOR <=3;
WHEN 4 =>
TEMP1 <= D ;
TEMP2 <= O ;
TEMP3 <= O ;
TEMP4 <= R ;
TEMP5 <= O ;
TEMP6 <= P ;
TEMP7 <= E ;
TEMP8 <= N ;
WHEN 5 =>
TEMP1 <= D ;
TEMP2 <= O ;
TEMP3 <= O ;
TEMP4 <= R ;
TEMP5 <= C ;
TEMP6 <= L ;
TEMP7 <= O ;
TEMP8 <= S ;
WHEN 6 =>
START:='1';
STOP:='0';

55
WHEN 7 =>
STOP:='1';
START:='0';
WHEN OTHERS =>
TEMP1 <= I ;
TEMP2 <= D ;
TEMP3 <= L ;
TEMP4 <= E ;
TEMP5 <= K ;
TEMP6 <= E ;
TEMP7 <= Y ;
TEMP8 <= SPACE ;
END CASE;
IF START='1' THEN
IF COU=FLOOR THEN
START := '0';
COU:=COU;
TEMP7 <= "001100" & COU ;
ELSIF COU<=FLOOR THEN
COU:=COU + '1';
TEMP1 <= U ;
TEMP2 <= P ;
TEMP3 <= SPACE ;
TEMP4 <= SPACE ;
TEMP5 <= SPACE ;
TEMP6 <= "01111110" ;
TEMP7 <= "001100" & COU ;
TEMP8 <= SPACE ;
ELSIF COU>=FLOOR THEN
COU:=COU-'1';
TEMP1 <= D ;
TEMP2 <= O ;
TEMP3 <= W ;
TEMP4 <= N ;
TEMP5 <= SPACE ;
TEMP6 <= "01111111" ;
TEMP7 <= "001100" & COU ;
TEMP8 <= SPACE ;
END IF; END IF; END IF;
END PROCESS;
END RTL;
Question Bank
1. a) Write an VHDL code to implement all logic gates.
b) Write a VHDL code to display messages on the given seven segment
display accepting HEX keypad input data.
2. a) Write an HDL code to implement 2 to 4 decoder.

56
b) Write a VHDL code to generate square waveform using DAC.

3. a) Write an HDL code to implement 8 to 3 encoder with priority.
b) Write a VHDL code to implement triangular waveform using DAC.
4. a) Write an HDL code to implement 8 to 3 encoder without priority.
b) Write a VHDL code to implement ramp waveform using DAC.
5. a) Write an HDL code to implement 8 to 1 multiplexer.
b) Write a VHDL code to generate Ramp waveform using
DAC.
6. a) Write an HDL code to implement 4 - bit binary to gray converter.
b) Write a VHDL code to generate staircase waveform using DAC.
7. a) Write an HDL code to implement 1:8 demultipexer.
b) Write a VHDL code to control speed, direction of DC motor.
8. a) Write an HDL code to implement 4 - bit comparator.
b) Write a VHDL code to control speed, direction of stepper motor.
9. Write a VHDL code for full adder using three modeling styles.
10. Write a verilog code for full adder using three modeling styles.
11. a) Write an verilog code to implement all logic gates.
b) Write a VHDL code to display messages on the given seven segment
display accepting HEX keypad input data.
12. Write an HDL model for 32-bit ALU using the schematic diagram shown
below.
13. Write a VHDL code for SR and D Flip flops.

14. Write a verilog code for SR and D Flip flops.
15. Write a VHDL code for JK and T Flip flops.
16. Write a verilog code for JK and T Flip flops.

57
17. Write an HDL code for 4 – bit binary asynchronous counter.(Asynchronous

reset) and any sequence counters. (Mod ------)
18. Write an HDL code for 4 – bit binary synchronous counter.(synchronous
reset) and any sequence counters. (Mod ------)
19. Write an HDL code for 4 – bit BCD counter.

58

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IV SEM E&C ENGG.

, HDL LAB (06ECL48)

EXPERIMENT PAGE NO.

1. HDL code to realize all the logic gates 4-5

2. HDL program for the following combinational designs

4. HDL model for 32-bit ALU. 20

5. HDL codes for the following flip-flops, SR, D, JK, T. 21-25

2. HDL code to control speed, direction of dc and stepper motor. 48-41

4. VHDL code to control external lights using relays. 45

5. HDL code to accept 8 channel analog signals, temperature sensors and

6. VHDL code to simulate elevator operations 50-56

Department of Electronics & Communication, C.I.T, Gubbi

OPCODE ALU OPERATION

2. Write HDL code to control speed, direction of dc and stepper motor.

4. Write VHDL code to control external lights using relays.

6. Write VHDL code to simulate elevator operations

Department of Electronics & Communication, C.I.T, Gubbi

Department of Electronics & Communication, C.I.T, Gubbi

1. VHDL CODE FOR ALL THE BASIC GATES.

1. VERILOG CODE FOR ALL BASIC GATES

module gates(A, B, NOTOUT, OROUT, ANDOUT, NOROUT,NANDOUT,XOROUT,XNOROUT);

Department of Electronics & Communication, C.I.T, Gubbi

UCF file (User constraint file)

Department of Electronics & Communication, C.I.T, Gubbi

2. VHDL CODE FOR 2 TO 4 DECODER.

2. VERILOG CODE FOR 2 TO 4 DECODER

module DECODER (DIN,ENABLE,D_OUT);

UCF FILE (USER CONSTRAINT FILE)

Department of Electronics & Communication, C.I.T, Gubbi

3.(A) VHDL CODE FOR 8 TO 3 ENCODER.(WITHOUT PRIORITY)

3.(A)VERILOG CODE FOR 8TO 3 ENCODER

module ENCODER8_3(ENABLE, DIN, D_OUT);

Department of Electronics & Communication, C.I.T, Gubbi

3.(b) VHDL CODE FOR 8 TO 3 ENCODER.(WITH PRIORITY)

Department of Electronics & Communication, C.I.T, Gubbi

3.(B)VERILOG CODE FOR 8TO 3 ENCODER

module ENCODER8_3(ENABLE, DIN, D_OUT);

Department of Electronics & Communication, C.I.T, Gubbi

NET "D_OUT<1>" LOC = "P85";

Department of Electronics & Communication, C.I.T, Gubbi

5. CODE 4 BIT BINARY TO GRAY CONVERTER.

G3=B3 G2 = B3 B2’ + B3 B2’ G1 = B2 B1’ + B1 B2’ G0 = B1’B0 + B1 B0’

module BINARY_GRAY(B, G);

Department of Electronics & Communication, C.I.T, Gubbi

Binary inputs Gray Outputs

6. VHDL CODE FOR 1:4 DEMUX.

Department of Electronics & Communication, C.I.T, Gubbi

D_OUT: OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); --OUTPUT LINES OF DEMUX

6. VERILOG CODE FOR 1:4 DEMUX

module DEMUX1_4(D_IN, SEL, D_OUT);

Department of Electronics & Communication, C.I.T, Gubbi

SELECT INPUT OUTPUT

7. COMBINATIONAL VHDL CODE FOR N BIT COMPARATOR.

7. COMBINATIONAL VERILOG CODE FOR 4-BIT COMPARATOR

module COMPARATER(A, B, ALB,AGB,AEB);

Department of Electronics & Communication, C.I.T, Gubbi

A B A=B A>B A<B

8a. VHDL CODE FOR THE IMPLEMENTATION OF HALF ADDER.

DATA FLOW STYLE

Department of Electronics & Communication, C.I.T, Gubbi

PORT (A, B: IN STD_LOGIC; --2BIT INPUT

ARCHITECTURE BEHAVIORAL OF XOR1 IS