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IEICE Electronics Express, Vol.* No.*,*-*

Design of an H-Bridge Driver

without Dead-Time
Generation using Gate Bias
Hsin-Chuan Chen1 , Nonmember and Rong-San Lin 2, Member

1
Department of Electronic Engineering, St. John’s University, Taiwan
499, Sec. 4, Tam-King Road, Tamsui District, New Taipei City, 25135 Taiwan.

2
Department of Computer Science and Information Engineering, Southern Taiwan
University of Science and Technology.
No. 1, Nan-Tai Street, Yungkang Dist., Tainan City 710, Taiwan

2) rslin@mail.stust.edu.tw

Abstract: H-bridges are important driving components for consumer

electronics and industry controls. They also play an important role in
technologies related to DC motor control. Conventional H-bridge drivers
require dead-time generation to avoid the shoot-through current resulting
from both upper and lower power transistors being turned on concurrently.
Unlike the conventional H-bridge driver, this paper proposes an H-bridge
driver based on a complementary MOSFET type using gate bias, without a
dead time generator, to improve its driving efficiency. Moreover, this
proposed H-bridge driver also has a reduced hardware complexity.

Keywords: H bridge, MOSFET, dead time, gate bias, DC motor.

Classification: Electron devices, circuits, and systems

References
[1] N. Mohan, T .M. Undeland and W. P. Robbins, Power Electronics: Converters,
Applications, and Design, 2nd ed., John Wiley & Sons, Inc., 1995.
[2] J. Brown and B. Jordan, “Brief H-Bridge Theory of Operation,”
http://www.dprg.org/tutorials/1998-04a/, August 2002.
[3] T. J. Summers and R. E. Betz, “Dead-Time Issues in Predictive Current
Control,” IEEE Transactions on Industry Applications, vol. 40, no. 3,
pp.835-844, May/June 2004.
[4] N. Urasaki, T. Senjyu, K. Uezato, and T. Funabashi, “Adaptive Dead-Time
Compensation Strategy for Permanent Magnet Synchronous Motor Drive,”
IEEE Transactions on Energy Conversion, vol. 22, no. 2, pp.271-280, June
2007.
[5] H. C. Chen, “An H-Bridge Driver Using Gate Bias for DC Motor Control,”
Proc. 17th IEEE International Symposium on Consumer Electronics, pp.
265-266, June 2013.
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1 Introduction
In many control applications, such as motors, DC/DC converters, and class-D
amplifiers, the H-bridge is an often-used power control device that drives the
inductive load. In particular, the H-bridge driver can control the direction and
speed of DC motors [1]. Therefore, it has become an important driving component
for power electronics. The basic structure of the H-bridge consists of four power
transistors, such as BJT, MOSFET, or IGBT, which work as electronic switches
[2]. When both upper and lower power transistors on the same side are turned on
concurrently, the shoot-through phenomenon may occur due to the transition delay
of the power transistors. Consequently, the generation of dead time is necessary
and important for the H-bridge driver. However, this may cause a nonlinear output
corresponding to the PWM control input, and thus several drivers need dead-time
compensation [4]. Modern conventional H-bridge chips or modules all have
built-in dead-time circuits to avoid a shoot-through situation. Based on the
complementary MOSFET structure, a new H-bridge design using gate bias
technology is proposed in this paper. Without dead-time generation existing in
conventional H-bridge drivers, the proposed H-bridge driver can benefit from low
hardware costs and achieve better linear control.

2 Dead time in H bridge

Consider the H-bridge driver using a complementary MOSFET structure shown in
Fig. 1. When the lower power MOSFET Q3 (Q4) turns on from the off state, it
must wait for the upper power MOSFET Q1 (Q2) to turn off from the on state in
advance for a period of time (called dead time). Similarly, it also needs the dead
time to turn Q3 (Q4) off from the on state in advance when the upper power
MOSFET Q1 (Q2) turns on from the off state. Fig. 2 illustrates the generation of
dead time corresponding to the input PWM signal. The dead time can prevent the
upper and lower transistors on the same side from turning on concurrently, such
that these transistors are not damaged by the shoot-through current. However, the
existence of dead time will affect the performance of the controlled device,
especially the high-speed switching of power transistors. Moreover, there exists
the voltage error between the control voltage and the actual output voltage, which
will result in a temporary loss of control, and cause a nonlinear distortion when
transferring the control voltage to the corresponding physical signal [3, 4].
+VDD

VGP1 VGP2
Q1 D1 D2 Q2
Dead Time
PWM Generation Load
Signal and
Gate Control
Q3 D3 D4 Q4
VGN3 VGN4

Fig. 1 CMOS H-bridge driver with dead-time generation.

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PWM :

Q1 (Q2) OFF
Q1 (Q2) ON Q1 (Q2) ON
VGP1 (VGP2) :

Q3 (Q4) ON
Q3 (Q4) OFF Q3 (Q4) OFF
VGN3 (VGN4) :

Dead Time Dead Time

Fig. 2 Definition of dead time.

3 Proposed H-bridge driver

The architecture of the proposed H-bridge driver, shown in Fig. 3, includes the
basic CMOS H-bridge, open-collector inverters, a gate-holding circuit for the
PMOS, and a gate-biasing circuit for the NMOS. In the driver circuit shown in Fig.
4, no complicated control circuit is required, only four open-collector inverters
(U1–U4) used as buffers for the logical inputs (A and B) associated with some
resistors (R1–R6) and capacitors (C1 and C2). Here, the output of U1 (U2) can pull up
to the supply voltage (VDD) to turn Q1 (Q2) off, and it also connects to R1 and C1 (R2
and C2) to construct a gate-holding circuit that always keeps the “Lo” state when
the PWM signal enters into Q1 (Q2). U3 (U4) is connected to R3 and R5 (R4 and R6),
forming a gate-biasing circuit for Q3 (Q4), which avoids incurring shoot-through
current when the PWM signal inputs to Q1 and Q3 (Q2 and Q4) at the same time. In
addition, D1–D4 are fly-back diodes, which eliminate the back EMF from inductive
loads.

VGP1
Gate-Holding
Circuit VGP2
Inputs Open-
(A, B) CMOS
Collector H Bridge
Inverters
VGN1
Gate-Biasing
Circuit VGN2

Fig. 3 Architecture of the proposed H-bridge driver without dead time.

+VDD

R1 R2
A Q1 D1 D2 Q2 B
C1 C2
U1 U2
+5V Load +5V
R3 R4
Q3 D3 D4 Q4
U3 R5 R6 U4

Fig. 4 Proposed H-bridge driver circuit.

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3.1 Gate bias technology

To improve the efficiency of an H-bridge driver on PWM control, this paper
proposes applying gate bias technology to a CMOS-based H-bridge driver. In the
proposed driver circuit, according to the superposition principle at A = “Lo” or B =
“Lo”, two gate voltages (VGN3 and VGN4) of the NMOS transistors (Q3 and Q4) can
be expressed as, respectively [5]:

 R5   R3 
VGN 3    VS    VB (1)
 R3  R5   R3  R5 

 R6   R4 
VGN 4    VS    VA (2)
 R4  R6   R4  R6 
where VA and VB are the logical voltages for inputs A and B, and VS is the logical
supply voltage (e.g., VS = 5 V for TTL logic). When both A and B remain in a “Lo”
state (i.e., VA = VB  0), two PMOS transistors (Q1 and Q2) turn off immediately. If
R3, R5 and R4, R6 are appropriately selected to build two gate-bias voltages slightly
larger than Vth for Q3 and Q4, respectively, then Q3 and Q4 turn on in this state,
where VGN3 and VGN4 are given by:

 R5 
VGN 3    VS  Vth (3)
 3
R  R5 

 R6 
VGN 4    VS  Vth (4)
 R4  R6 
and R3/R5 and R4/R6 can be found as:
R3 R4 VS
  1 (5)
R5 R6 Vth

Since the PWM signal, with a period less than the R1C1 time constant, that
enters into input A and input B remains “Lo”, Q1 always turns on by holding the
gate of the PMOS at a “Lo” state and VGN4 is modified to:

 R4 
VGN 4  Vth    VS  D , (6)
 R4  R6 
where D is the duty cycle of the PWM signal and it is assumed that the logical level
of the PWM signal is TTL. Therefore, Q4 can easily be turned on by the PWM
signal with smaller duty cycle than that of conventional H-bridge drivers.
Although the PWM signal also appears at the input of U3, VGN3 will vary under Vth
as the duty cycle of PWM signal increases, and it is given by:

 R5 
VGN 3    VS  (1  D ) (7)
 R3  R5 
Consequently, Q3 can work from the pinch-off region at D = 0 to the cutoff region
at D > 0 to make sure Q1 and Q3 do not turn on concurrently. Therefore, the
proposed H-bridge driver can naturally avoid the shoot-through situation without

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dead-time generation. Similarly, when the PWM signal enters into input B at
A = “Lo”, Q2 and Q3 will turn on, and Q4 works from the pinch-off region to the
cutoff region as the duty cycle increases.

3.2 Circuit operation

To explain how the proposed H-bridge driver operates, the proposed H-bridge
driver was applied to a DC motor controller and executed the four basic functions
shown in Table 1, which include stop, forward, reverse, and brake. The detailed
operation of the proposed driver circuit using the example of DC motor control is
described as follows:
(1) When A = B = “Lo”, Q1 and Q2 turn off, and two biases, VGN3 and VGN4, have
been built to make Q3 and Q4 turn on. Therefore, the motor has no current
flowing through it, putting it in a “stop” state.
(2) When A = B = “Hi”, both Q1 and Q2 turn on, but Q3 and Q4 are off, and the
motor comes to a sudden stop, which results in a “brake” state.
(3) When A = PWM and B = “Lo”, Q1 turns on and Q4 is activated by the PWM
signal until it completely turns on at the 100% duty cycle. The motor can thus
rotate forward, and its speed is proportional to the duty cycle of the PWM
signal.
(4) When B = PWM and A = “Lo”, Q2 turns on and Q3 is activated by the PWM
signal until it completely turns on at the 100% duty cycle. The motor can thus
rotate in reverse, and its speed is controlled by the PWM signal.

Table I. Basic operation of proposed H-bridge driver for DC motor control.

Input
Motor Operation
A B
Lo Lo Stop
PWM Lo Forward (Speed controlled by PWM)
Lo PWM Reverse (Speed controlled by PWM)
Hi Hi Brake

3.3 Benefits and overheads

By providing the gate biases on the two NMOS transistors, the proposed H-bridge
driver can successfully increase the control range when using PWM, making
PWM control highly efficient. Unlike conventional H-bridge drivers, the proposed
H-bridge driver does not require an extra dead-time generator to prevent the
shoot-through phenomenon from occurring. Therefore, this proposed H-bridge
driver without dead-time generation can reduce hardware costs. The only
limitation in the operation of this driver is the situation where one input keeps a
“Hi” state and the other one is controlled by the PWM signal. This situation will
still cause shoot-through occurrences. However, this can be solved by connecting
two extra NMOS switches to the gates of Q3 and Q4 to force VGN3 or VGN4 to ground
once the other side inputs “Hi”, even when the PWM signal enters into this side.

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4 Experimental results
This experiment used two PMOS (IRF9540) and two NMOS (IRF540) transistors
to implement the CMOS H-bridge, where their threshold voltage Vth is about 3 V,
and selected R3 = R4 = 1 KΩ and R5 = R6 = 1.8 KΩ to build two gate biases: VGN3 =
VGN4 = 3.2 V according to Eqs. (1) and (2). The practical circuit prototype is shown
in Fig. 5. This driver offers a supply voltage range of 5–24 V and a maximum
supply current of 10 A for the load, and a DC motor of 12 V and 1800 rpm was
used as the testing load.
For the verification and measurement of the proposed driver, the PWM signal
at 15.625 KHz was inputted to one control node of the H-bridge, and the another
node was kept at a low level. The measured waveforms shown in Fig. 6(a) include
a low-level voltage at node A (CH1), a PWM signal of 50% duty cycle at node B
(CH2), and two gate voltages: VGN3 (CH3) and VGN4 (CH4). From Fig. 6(a), it can
be seen that the average voltage of VGN3 increases to 4.09 V from the gate-bias
voltage of 3.2 V at 50% duty cycle, and the average voltage of VGN4 decreases to
1.61 V from 3.2 V to always make Q4 cutoff even though Q2 stays on.
Consequently, VGN3 can increase as the duty cycle of the PWM signal increases,
and, inversely, VGN4 decreases under Vth as the duty cycle increases. Therefore, no
dead time is required in the proposed driver. Fig. 6(b) shows that the average drain
voltage VDS3 of Q3 (CH1) progressively decreases as the duty cycle of the PWM
signal increases, and VDS4 of Q4 (CH2) always stays at 12 V because Q2 completely
turns on.

Fig. 5 Circuit of the proposed H-bridge driver.

5V

3.2V

(a) (b)
Fig. 6 The measured waveforms for a 50% duty cycle.

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As for the H-bridge driver with a dead-time generator, the same NMOS and
PMOS as in the proposed H-bridge were used to construct the CMOS H-bridge, as
well as delay line elements and necessary logic gates were used to implement a
dead-time generator. By inputting the PWM signal into the NMOS to drive the
same DC motor, it was found that the driver with dead time must start up the motor
until the duty cycle D is greater than 27%. However, the proposed driver can easily
make the motor rotate at only D = 14.06%, where the output voltage shown in Fig.
7 corresponds to the rotating speed after starting up the DC motor. Therefore, the
proposed driver without dead time generation can achieve a larger range of speed
control for DC motors, especially for low-speed control.

12

10 Dead Time
Output Voltage (V)

No Dead Time
8

0
0.0 5.5 15.6 25.0 35.2 45.3 55.5 65.6 75.0 85.9 95.3 100.0
D uty Cycle (%)

Fig. 7 Comparison of output voltages for an H-bridge driver with and without dead time.

5 Conclusion
This paper proposed a design for an H-bridge driver based on the complementary
MOSFET type. Unlike conventional H-bridge drivers that require dead-time
generation, the proposed driver does not have a dead time generator, but instead
uses gate bias. This can successfully increase the control range of a device, such as
the speed range of a DC motor using PWM control, 14.6% to 100% in this
experiment. Therefore, the proposed H-bridge driver indeed improves its driving
efficiency for DC motors and provides a low cost design compared to the other
drivers with dead-time generation.

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