2017 IEEE 67th Electronic Components and Technology Conference
Thermal compression bonding: understanding heat transfer by in situ
measurements and modeling
Pieter Bex, Teng Wang, Melina Lofrano, Vladimir Cherman, Giovanni Capuz, Erik Sleeckx, Eric Beyne
imec
Kapeldreef 75, Leuven, Belgium
bexp@imec.be
Abstract—Thermal compression bonding (TCB) is becoming an
increasingly important process step in the assembly of advanced
components such as fine pitch flip chip packages, system-in-
package products, and 3D IC`s. To increase the throughput and
robustness of TCB processes, it is crucial to understand and
control important process parameters like time, force and
temperature. However, for TCB processes it becomes
challenging to measure and control the temperature over the
bond interface, since typically different temperature profiles are
applied to top chip and substrate. This paper proposes and
validates a new methodology for temperature measurements
and characterization of heat transfer during a TCB process. On-
chip thermal sensors measure the temperature in real time
during the TCB process, at different locations on both top and
bottom chips. Since the proposed methodology does not require
the insertion of a thermocouple in between the top chip and
substrate, it will enable more reliable measurements, especially
for fine pitch micro bump devices.
I. INTRODUCTION
Thermal compression bonding (TCB) is becoming an
increasingly important process step in the assembly of
advanced components, such as fine pitch flip chip packages,
system-in-package products, and 3D IC`s. TCB enables
bonding of chips with fine pitch interconnects and low bond
line thickness (BLT), the handling and bonding of thinned
and warped chips [1], and can reduce the chip warpage and
thermo-mechanical stress induced in the BEOL layers. This
becomes very important in case of advanced node chips,
which contain very fragile ultra-low dielectric constant (ULK)
layers [2, 3].
However, there are still obstacles that slow down the wider
adoption of TCB in high volume production.
First, a TCB process has relatively low throughput
compared to traditional mass reflow processes. High speed
bonding equipment with fast heating and cooling ramp rates,
combined with the development of rapid flowing and curing
wafer level underfill (WLUF) materials [4], shortened the
TCB process time. Additionally, the introduction of new
concepts such as gang bonding and vertical collective bonding
[1, 5] significantly increased the TCB process throughput.
Second, TCB has become a highly complex process,
especially in presence of pre-applied underfill materials. Good
interconnect joint formation needs to be achieved while the
underfill flows and cures. At the same time, specifications
2377-5726/17 $31.00 © 2017 IEEE
DOI 10.1109/ECTC.2017.49
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including alignment accuracy, BLT control and chip tilt have
to be met.
These complexities combined with the need for faster
TCB profiles present significant challenges for the
development and optimization of TCB processes.
Therefore, careful fine tuning of the TCB process
parameters becomes essential [5]. It is relatively easy to
measure and control process parameters like time, force and
z-height. Temperature is a much more challenging parameter,
yet a very important one. An appropriate temperature profile
is required to control the underfill flow and curing behavior,
and yield good quality joints at the same time.
In typical TCB processes, a high temperature profile is
applied to the top chip, while the bottom chuck is kept at a
constant lower temperature. This will result in a temperature
gradient over the stacked layers, which makes it very difficult
to predict and control the actual bonding interface
temperature.
The traditional and most commonly used approach for
measuring the interface temperature during TCB, is to insert a
thermocouple between the chips before bonding [6, 7, 8]. This
method however has significant disadvantages. First, a
thermocouple wire is relatively thick. For finer pitch bump
assemblies the BLT eventually becomes smaller than the
thermocouple wire diameter. This will cause bad contact and
gaps between the chips, mechanical damage to fragile thinned
devices, and chip tilt. All these effects will eventually
influence the heat transfer behavior, and finally result in
interface temperature measurements that are not
representative for the actual TCB process.
Furthermore, a single point thermocouple measurement
does not reveal the complex heat transfer behavior during the
TCB process. Figure 1 shows a 50 μm diameter thermocouple
wire that was placed in between a 20 μm pitch bump stack.
After the TCB process, the thermocouple shows almost no
deformation, resulting in a chip gap which is much larger than
the normal 13 μm BLT for this specific test vehicle. For even
smaller bump pitches where the bumps are embedded in a
polymer [9], there is virtually no space left at all for insertion
of thermocouples.
Therefore, alternative solutions are required to measure
the interface temperature and characterize the heat transfer for
fine pitch interconnect TCB processes. One interesting option
is the use of thermal sensors embedded in the chips.
392
 Normal bond line thickness for the imec 20 μm bump pitch
testvehicle (left) and a thermocouple wire that had been inserted between
test chips for TCB (right)
Up to now, such on-chip thermal sensors are being used
for the characterization of chip and package thermal
dissipation, and inter-die thermal coupling in 3D-IC`s. In
those experiments, the temperature is measured by diodes
[10], ring oscillators [11] or resistance temperature detectors
(RTD`s) [12].
This paper proposes and validates a new methodology to
characterize the heat transfer and estimate the interface
temperature during a TCB process. On-chip thermal sensors
measure the temperature at different locations in both top and
bottom chips in real time during the TCB process. The real
time temperature measurements are combined with finite
element method (FEM) modeling to enhance the
understanding of heat transfer during TCB processes.
In section II we introduce the test vehicle. The TCB
experimental details are given in section III, while section IV
discusses the FEM modeling. Section V starts with the
calibration of the on chip sensors, followed by the in situ
thermal measurement results.
II. TEST VEHICLE DESCRIPTION
The test vehicle used in this paper is the passive imec 20
μm bump pitch Packaging Test Chip version O (top chip) and
P (substrate chip). These chips are designed for die to die
(D2D) and die to wafer (D2W) assembly and pre-assembly
process R&D, as well as for reliability tests after assembly.
The PTCO/P test chip combination can be used in both face-
to-face (F2F) and multi-die back-to face (B2F) stacking
configurations, as illustrated in figure 2. The size of the PTCO
top chip is 5.2x5.2 mm2, the substrate PTCP chip size is
10.2x10.2 mm2. Both chips contain various test structures for
the evaluation of stacking misalignment, electrical yield, RF
characterization and thermal measurements.
Stacking configuration options for the 20 μm bump pitch
PTCO/P test vehicle. Face-to-face (left) and Back-to-face multi die stack
(right)
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Micro bump layout and thermal sensor locations for the
PTCO/P test vehicle.
PTCO thermal sensor (left) and PTCP thermal sensor layout
(right)
The test chips are made up of 2 standard imec 65nm node
CMOS BEOL layers, finished with semi-additive
electroplated 20 μm pitch Cu/Sn microbumps. For B2F
stacking, the PTCO chips additionally contain TSV`s,
manufactured in a 5x50 μm via-middle process module, and
are thinned to 50 μm. All processing is done on a 300 mm
wafer platform. For the current experiments, the F2F bonding
configuration was used, with full thickness PTCO top dies.
After the 300mm wafer manufacturing process, a PTCP
substrate wafer was diced in 3x3 die coupons to mimic a D2W
bonding configuration while saving material, and to allow
easy manipulation of the wired substrate. Flexible printed
circuit boards were then attached to a PTCP substrate coupon,
and wire-bonded to the bond pads of the 3 middle dies.
The PTCO top die wafer was laminated with a silica filled dry
film WLUF, and finally diced.
Figure 3 visualizes the bump layout and thermal sensor
locations in the test vehicle. The thermal sensors are RTD`s,
formed by a copper meander structure in the metal 1
interconnect layer. In the PTCP substrate chip, thermal
sensors are located in the center and periphery of the chip. The
PTCO top chips only contain sensors in the center.
The PTCO thermal sensor dimensions are 40 x 50 μm2,
while the PTCP sensor size is 50 x 90 μm2. All sensors have 4
terminals, enabling reliable 4-point resistance measurements.
The layout for both PTCO and PTCP sensors is shown in
figure 4.
Both PTCP and PTCO thermal sensors are internally
connected to the bond pads of the substrate PTCP chip.
Therefore, measurement of the top chip sensors is only
possible once electrical connection is established between top
and bottom chip during the chip stacking process.
 The temperature measurement principle is based on the
linear temperature dependency of the electrical resistance of
the RTD sensor. Electrical resistance in function of
temperature can be written as follows:

ܴሺܶሻ ൌ ܴ଴ ൈ ሺͳ ൅ ܶ‫ ܴܥ‬ൈ ሺܶ െ ܶ଴ ሻ) (1)

Where TCR is the Temperature Coefficient of Resistance,

T0 is a reference temperature, and R0 is the resistance at the
reference temperature. Once the TCR and R0 are determined
during the sensor calibration, the sensor temperature can be
calculated from the measured resistance.

ோିோబ ଵ
ܶ ൌ ൈ ൅ ܶ଴  (2)
ோబ ்஼ோ

The sensor calibration was performed after the chip

bonding experiments, since the top die sensors can only be TCB temperature profile
measured after bonding to the bottom PTCP chip.
III. TCB EXPERIMENTAL SETUP
The equipment used for the TCB experiments is a BESI
Datacon 8800 TC. This equipment enables fast TCB
processes, because of its rapid movements, and fast
temperature ramping. The maximum heating ramp rate is 200
C/s, while the cooling ramp rate goes up to 100 C/s. A
300mm substrate chuck is installed to enable D2W bonding.
Since a 30.6 x 30.6 mm2 coupon substrate is used instead of a
complete wafer, the chuck vacuum grooves were partially
blocked to assure good contact between substrate chuck and
coupon. Temperature calibration of the bondhead is
performed either by an infrared camera or a contact type
measurement, such that the set temperature represents the
actual temperature on the surface of the bondhead.
Figure 5 shows the TCB profile that was used for the
bonding experiments. The substrate chuck heater temperature
is kept constant at 75C, while the bondhead temperature is
applied in a 2 step profile. The first temperature staging step Schematic overview of TCB experiments and involved thermal
enables good underfill reflow and activation of the fluxing sensors. (a) measurement of stack under bonding conditions, (b) assess
agent, before reaching the solder melting point in the second thermal impact on adjacent substrate sites during TCB
step. The bondforce remains constant at 2 kgf.
The wired substrate coupon was connected to a setup that
measures the resistance of up to 3 sensors in real time with a
sampling rate of 66 Hz. Low voltage and current IV. FINITE ELEMENT METHOD MODEL
measurements minimize Joule self-heating of the RTD In addition to the in situ thermal measurements, a 3D
sensors. No self-heating effect could be observed during Finite Element Method (FEM) model was built to increase the
measurements at room temperature. The 4-point resistance understanding of heat transfer behavior during TCB.
measurement setup enables reliable resistance measurements The model was created using a commercial FEM software
of the sensors itself, by avoiding wiring and contact resistance package, Msc MarcTM. The model consists out of the
within and outside of the chip. 30.6x30.6 mm2 PTCP substrate coupon bonded with full
Two different in situ temperature measurement thickness PTCO chips. Due to symmetry, only ½ of the
experiments were performed. First, the temperature in both bonded coupon was modeled. The detailed micro bump layout
top and bottom chip of a stack under bonding conditions was as shown in figure 3 is included in the model.
measured. Second, during bonding of a chip, the temperature The thermal conductivity of the WLUF was set to 0.3
in the adjacent PTCP substrate positions was measured to W/m.K, based on previously published results for a silica
characterize the thermal influence of the TCB process on particle filled WLUF [13].
neighboring substrate sites. Figure 6 shows the sensors that
were measured during the different experiments.

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 In order to take into account the temperature variation
caused by external thermal resistance present in the TCB
equipment, the model was augmented with both the bondhead
and substrate chuck, combined with a heat transfer coefficient
to mimic the vacuum contact. Furthermore, due to the fact that
the bottom chuck is placed on top of a heater element with
relatively high thermal conductivity, also a part of this heater
and contact resistance between heater and substrate chuck was
incorporated in the model. The final FEM model design is
shown in figure 7.
FEM model design
FEM thermal simulation results for TCB on edge and middle of
3x3 PTCP substrate coupon
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Figure 8 presents the transient thermal simulation results
for TCB processes in the middle and at the edge of a substrate
coupon. Within a single stack, a significant temperature
gradient over the bonding interface is seen. This gradient can
be explained by the high thermal resistance of the WLUF
between the dies, combined with a low amount of micro
bumps in the center of the chips.
Furthermore, a temperature difference between the center
and periphery of a substrate die is observed. This is mainly
due to the strong lateral heat spreading, caused by the
relatively large dimensions of the substrate compared to the
top die, in combination with the high thermal conductivity of
the silicon. Therefore, the substrate itself acts as a heat sink
during the TCB process, as illustrated in figure 9.
The lateral heat spreading also explains the temperature
difference between a stack in the middle of the coupon
compared to the edge stack. Heat will dissipate more easily
from the middle stack compared to an edge stack, because of
the larger silicon area surrounding the middle stack. The
strong lateral heat transfer also leads to a significant
temperature increase in neighboring substrate sites during
TCB. Figure 10 illustrates the temperature increase in the left
and middle substrate bond position during TCB of the right
stack.
Besides the baseline micro bump layout, alternative bump
layouts were used as input for the FEM model. Figure 11
shows that the addition of dummy micro bumps in the center
of the dies helps to decrease the temperature gradient between
the chip center and periphery.
FEM simulation: Temperature variation within substrate die
during TCB
FEM simulation: temperature increase in substrate coupon
during TCB
 FEM simulation: influence of microbump layout on temperature uniformity during TCB

First, the room temperature resistance R0 was determined.

V. IN SITU THERMAL MEASUREMENT RESULTS
A. Thermal sensor calibration
After the TCB experiments, the thermal sensors of both
the substrate and the top chip were calibrated. Since R0 and
TCR can vary because of defects and variations in the wafer
manufacturing process, all involved sensors were individually
calibrated. The left stack sensors were excluded, since a
wiring failure was observed, most likely caused by manual
handling of the substrate coupon after the TCB process.
The TCR can be calculated as follows:
Afterwards the wired coupon was placed in a Votsch VT7011
oven, and the TCR was calculated by measuring the sensor
resistance at different temperatures between 23C and 150C.
A linear relationship between temperature and resistance
was observed for all calibrated sensors. As example, the
resistance in function of temperature for one PTCP sensor is
shown in figure 12.
Table 1 presents an overview of TCR (ppm/ C) and R0
(Ohm) for the calibrated sensors in respectively the middle
and edge stack.

ோିோబ TABLE I. SENSOR CALIBRATION: TCR AND R0

ܶ‫ ܴܥ‬ൌ (3)
ோൈሺ்ି்బ ሻ

Middle Stack

Sensor PTCO center PTCP center PTCP

Periphery
TCR(ppm/ C) 3106 3217 3210
R0 (Ohm) 749 1047 1058

Right Stack

Sensor PTCO center PTCP center PTCP

Periphery
TCR(ppm/ C) 3118 3198 3102
R0 (Ohm) 753 1046 1033
PTCP thermal sensor calibration: ectrical resistance in function
of temperature

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Wired substrate coupon after TCB
From this point in time onwards, readout of the PTCO top
chip sensor becomes possible.
Table 2 provides the maximal measured temperatures of
the sensors during TCB of both the middle and the right stack.
The measured temperature gradient between periphery and
center of the substrate dies was around 12 C. Also a high
temperature gradient of 50 C was observed over the bond
interface. Additionally, the measurements showed
considerable higher temperatures during TCB of the right
stack compared to the middle stack, caused by the lateral heat
transfer in the silicon substrate.
The second TCB experiment measured the thermal
influence of the TCB process on adjacent substrate locations.
During TCB of the left stack, the temperature in the middle
and the right bond position of the substrate was measured.
Figure 15 illustrates the temperature increase in the adjacent
substrate sites. A limited temperature increase to 85 C was
measured for the right substrate bond site, while the direct
neighboring bond site is heated to 110 C.

TABLE II. IN SITU THERMAL MEASUREMENTS: MAXIMAL

TEMPERATURES DURING TCB PROCESS

Middle Stack

Sensor PTCO center PTCP center PTCP

Periphery
Temperature (C) 274 224 212

Right Stack

Sensor PTCO center PTCP center PTCP

In situ thermal measurements: TCB of right stack Periphery
Temperature (C) 305 254 241
B. In situ thermal measurements
After the thermal sensor calibration, the sensor
temperatures during the TCB process were calculated from
the resistance measurements and the TCR and R0 of the
individual sensors, as described in equation 2.
Figure 13 depicts the bonded coupon after the TCB
experiments. For all stacks, the TCB profile given in figure 5
was used.
Figure 14 shows the top chip and substrate sensor
temperatures during TCB of the right stack. A high
temperature gradient between top chip and substrate was
observed. Also the temperature in the center of the substrate
die was higher than in the periphery. After reaching the
required bondhead temperature setpoint, the on chip sensor
temperatures slowly keep on increasing since no steady state
is achieved. Therefore, the maximum temperature is only
reached at the end of the bonding profile.
An additional interesting observation is the detection of
the point when electrical connection is established between In situ thermal measurements: temperature increase in adjacent
the top chip and substrate. This point is easily recognizable in substrate sites
figure 14, visualized by the green dashed circle.

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 The FEM model predicts and explains the general trends
seen in the in situ thermal measurement results. The low
thermal conductivity of the WLUF and the limited amount of
micro bumps cause a high temperature gradient over the bond
interface, while the high thermal conductivity of Si leads to
considerable lateral heat transfer in the substrate coupon. This
in turn results in stack-to-stack temperature differences, and a
temperature gradient between the center and periphery of the
individual substrate dies. However, the mismatch between the
in situ thermal measurements and the FEM model simulation
results suggest that more accurate calibration and fine tuning
of the model is required, in combination with an increased
number of experiments to verify the process repeatability.
VI. CONCLUSIONS
In this paper we presented a new methodology to
understand the thermal aspect of a TCB process. On chip
thermal sensors enable in situ temperature measurements in
both top and substrate dies, without insertion of thermocouple
wires.
The experiments produced some important findings. First,
we observed a high temperature gradient across the thin bond
interface between the top and bottom chips when the top and
bottom chucks are set to different temperatures. Second, a
significant temperature difference between the center and
periphery of the chip was detected. Third, by monitoring the
temperature at different sites of the substrate coupon, we
found a significant thermal coupling effect on the adjacent
substrate sites during TCB.
Since no steady state was reached during the TCB process,
the interface temperature keeps increasing towards the end of
the bonding profile. This additional time dependency can
become important when shortening the TCB process. A
simple reduction of TCB process time without temperature
increase, will result in lower maximal process temperatures,
potentially affecting the TCB process quality.
An additional interesting aspect of the in situ thermal
measurement method is that it enables accurate detection of
the time when electrical contact is established between the top
and bottom chips.
In addition to the in situ thermal measurements, a FEM
model was created to increase understanding of the heat
transfer behavior during TCB. The low thermal conductivity
of the WLUF in combination with the micro bump layout and
the high thermal conductivity of the Si substrate coupon are
the main contributors to the temperature gradients observed
during the in situ thermal measurement experiments. Further
fine tuning and calibration of the FEM model is however
required to obtain more accurate simulation results.
The in situ thermal measurement methodology can
provide valuable information for the development of new and
fast TCB processes, as well as the tuning of existing processes.
The methodology is however not limited to TCB processes,
and can also be extended to the study of other processes where
accurate real time thermal measurements are needed.
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