ST9040 FAMILY 8/16 BIT MCU DATABOOK 1% EDITION APRIL 1993USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED. SGS-THOMSON PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF SGS-THOMSON Microelectronics. As used herein: 1. Life support devices or systems are those which (a) are 2. A critical component is any component of a lfe support intended for surgical implant into the body, or (b) support device or system whose failure to perform can reason- or sustain life, and whose failure to perform, when prop- ably be expected to cause the failure of the life support erly used in accordance with instructions for use provided device or system, or to affect its safety or effectiveness. with the product, can be reasonably expected to result in significant injury to the user.TABLE OF CONTENTS GENERAL INDEX INTRODUCTION ST9 FAMILY OVERVIEW DEVELOPMENTS TOOLS DATASHEETS sT9040 16K ROM MCU ST90E40/T40 EPROM & OTP version ST90R40 ROMLess version APPLICATION NOTES Page 5 12GENERAL INDEX Pages Number GENERAL INDEX : . : 5 INTRODUCTION o . 12 ST9 FAMILY OVERVIEW cccese tenses 15 DEVELOPMENTS TOOLS oo) ee 61 DATASHEETS : - cesses ces 88 ST9040 c . coe BS 1 DESCRIPTION . ee nee 88 1.1 GENERAL DESCRIPTION. : — vines 88 1.2 PIN DESCRIPTION . . R . 89 aoe \/O Port Alternate Functions .. = 89 2 CORE ARCHITECTURE : cocoon teceneeecaeeeeeese os 93 24 COREARCHITECTURE o.oo... cesses . fetes 98 2.2 ADDRESS SPACES 93 22.1 — Register File 93 2.2.2 Addressing Registers vee foeeeeteees cece 9S 2.2.3 Input/Output Ports Leese veces . . 95. 23 SYSTEM REGISTERS R . 97 2.3.1 Central Interrupt Control Register . oe 2.3.2 Flag Register . . seteneerertuepeereeesee 9B 2.3.3 Register Pointing Techniques decteteteeens 99 2.3.4 Page Configuration . - cecsteeeeeesnerseseens 104 2.3.5 Mode Registers . sete eee see ses capitan sees 101 2.3.6 Stack Pointers “ 102 3 MEMORY ce coves 105 3.1. INTRODUCTION 405 3.2 PROGRAM SPACE DEFINITION 106 3.3 ROMLESS OPTION SUMMARY 106 34 DATA SPACE DEFINITION 106 35 EEPROM 106 3.5.1. Introduction... se. . 106 3.5.2 EEPROM Programming Procedure ... 107 3.5.3 Parallel Programming Procedure 108 3.5.4 EEPROM Programming Voltage ...... oe 109 3.5.5 EEPROM Programming Time ...... . see 109 3.5.6 EEPROM Interrupt Management 109 3.5.7 EEPROM Control Register : cecceeteeesereee 109 73a ——_—_—_—_—_—_——_____—_GENERAL INDEX Pages Number INTERRUPTS. 4.1. INTRODUCTION : ceceeeesees ene 2) | INTERRUBTVECTORICATION® tere 100) 4.3 INTERRUPT PRIORITY LEVEL ARCHITECTURE m1 4.4 PRIORITY LEVELARBITRATION .......2..0:c0ccsccescee cee eer tee eee pom ih) 4.4.1 — Concurrent Mode 4.4.2 Nested Mode 4.5 EXTERNAL INTERRUPTS 4.6 — TOPLEVEL INTERRUPT 47 — ON-CHIP PERIPHERAL INTERRUPTS. .........0..00++ so 120 48 — WAITFOR INTERRUPT INSTRUCTION .......0.....- , cecceeseeeeseee 122 49 INTERRUPT RESPONSE TIME 122 4.10 INTERRUPT REGISTERS... cscs ceessscessssecesse eer nseeesnscerseesersseceeseesee 124 ON-CHIP DMA 5.1 INTRODUCTION cesetee eases 5.2 DMAPRIORITY LEVEL ARCHITECTURE... 5.3 DMATRANSACTIONS ee ee eee eee ee leo 5.4 DMACYCLE TIME... 129 5.5 THE SWAP-MODE. 132 5.6 DMAREGISTERS ................ ioe CLOCK ........... 6.1 INTRODUCTION . 6.2 CLOCKMANAGEMENT ......... eee - 133 6.3 CLOCK CONTROL REGISTER ..........2..0... mena - ceeseeee 184 eee er eRe gig aaa cee 135, RESET rpecreencrneeorr eperoecod 197 (2ie) INTRODUGTION ee 137 7.2 RESET GENERATION ceeeeeeeeeee 137 7.3 RESET PIN TIMING ces ceecee tester serene tee 137 7.4 PROCESSOR SYNCHRONIZATION UNDER RESET 1.20.0. s00cssccecseeerser eee 137 7.5 EPROM PROGRAMMING PIN ..0.....0.ccsccssessesssren esos cocoon 138 G57 S&S:THOMSON YA. incnostecinomesGENERAL INDEX Pages Number 8 EXTERNAL MEMORY INTERFACE ............-...... 141 8.1 INTRODUCTION ao = eS ial 8.2 CONTROLSIGNALS 000.00... ccc cscces eee cee cess est teetineeeeeteneteenteseceecee ceases 141 8.3 MEMORY ACCESS CYCLE cress las) 8.4 STRETCHED ACCESS CYCLE...... 143 8.5 SHARED BUS 146 8.6 PORTS PO, P1, Pé INITIALIZATION AFTER RESET... coos 147 87 ROMLESS FUNCTION ........ . . cece 147 88 PIPELINE . orp cneprneneoroceccmen . 8.9 “SPURIOUS” MEMORY ACCESSES... 0... 2. cesceccse cesses cee ees ete teeettenetteceeeee 149 610 =REGISIERS) es a dorbroorocn (E) 9 WOPORTS ......... cette teesiettesseseanenaeieseetesereesee 151 941 INTRODUCTION ..... . 151 9.2 CONTROLREGISTERS ........... cesses eee testes ces sesenevtneteerene 151 9.3 PORT BIT STRUCTURE AND PROGRAMMING ere we 152 9.4 ALTERNATE FUNCTION ARCHITECTURE ...... cvretteteseeeeseeeetaness 155 9.5 SPECIAL PORTS 2 oe oe 150) 9.5.1 Bit Structure For A/D Converter Inputs . 156 9.6 VO STATUS AFTER WF, HALT AND RESET 156 10 HANDSHAKE/DMA CONTROLLER . 157 10.1 INTRODUCTION ......... 157 10.2 PROGRAMMABLE HANDSHAKE MODES fone 158 10.2.1. Input Handshake 158 10.2.2 Output Handshake . eee enee . eens - 160 10.23 Bidirectional Handshake 162 10.2.4 Mapping an ST9 onto the memory bus of another ST9 sess 163 10.3 PROGRAMMABLE DMA MODES 164 10.3.1 DMA Transfers Driven By Timer CAPTO Channel With Handshake......... 164 10.3.2 DMA Input transfers with two line input handshake ....... secsseeeee 164 10.3.3 DMA output transfers with two lines output handshake ............eeessee. 165 10.3.4 DMA input transfers with one line input handshake coseeeese 165 10.3.5 DMA output transfers with one line output handshake 10.3.6 DMA inpuvoutput transfers with bidirectional handshake... esses 166 10.3.7 DMA Transfers Driven By Timer Comp0 Channel With Handshake ........ 167 10.4 HANDSHAKE/DMA CONTROL REGISTERS . 168 SSRNGENERAL INDEX Pages Number 11. SERIAL PERIPHERAL INTERFACE = : im 41.1 INTRODUCTION ......... 171 11.2 FUNCTIONAL DESCRIPTION oe seseeee 172 11.2.1 Input Signal Description cece sesseeeeee 172 11.2.2 Output Signal Description : vase 172 11.3. INTERRUPT STRUCTURE. ..... os peace 173 11.4 SPIREGISTERS cesses soo 174 11.5 WORKING with DIFFERENT PROTOCOLS . cecteseesene 175 11.5.1 PC-bus Interface 175 11.5.2 S-Bus Interface soscsnssnesne . 178 11.5.3 IM-Bus Interface peneaen pas 179 12 TIMER/WATCHDOG . . 181 12.1 INTRODUCTION — 181 12.2. FUNCTIONAL DESCRIPTION . 182 12.2.1 Timer/Counter Input Modes area : 182 12.2.2 Timer/Watchdog Output Modes . . 182 122.3. Timer/Counter Control = : : ». 182 12.2.4 Timer/Watchdog Mode : . 183 12.3 TIMERAWATCHDOG INTERRUPT 184 12.4 TIMERWATCHDOG REGISTERS . coset 186 13 MULTIFUNCTION TIMER . coset 187 13.1 INTRODUCTION ossesieuinsueieneineies boos 187 13.2. FUNCTIONAL DESCRIPTION .......00.00.00.00sstsuee sets sve 189 18.2.1 One Shot Mode = 189 fis22) (Continucus Modog este eeeeeees : eves 189 18.2.3 Trigger And Retrigger Modes 0.0... cc: susssssssenss seen cn 189 13.2.4 Gate Mode Soscenssee cesstreensseetensee ns 189 13.2.5 Capture Mode : Poe 189 13.2.6 Up/Down Mode ot eee eee eeee 189 13.2.7 Free Running Mode ee . coos eeseeesee 189 13.2.8 Monitor Mode 190 13.29 Autoclear Mode 190 13.2.10 Bivalue Mode 190 13.211 Parallel Mode 190 13.2.12 Autodiscriminator Mode a gee 190 13.3 INPUT PIN ASSIGNMENT sosscetssetnennssnes vee 191 13.3.1 TXINA=VO-TXINB=VO o...ccseece : : ee! 13.3.2 TxINA= 1/0 - TxINB = Trigger se 191 13.3.3. TXINA= Gate TXINB = VO... 0. .cccssessee cece 194 13.3.4 TxINA= Gate - TxINB = Trigger ...... 192 18.3.5 TXINA=V/O- TxINB = Ext. Clock... cesses cocsessesses 192, SrGENERAL INDEX Pages Number 13.3.6 TxINA = Trigger - TxINB = /O. - 7 192 13.3.7 TxINA = Gate - TxINB = Ext. Clock 192 13.3.8 TxINA= Trigger - TxINB = Trigger ' = : 192 43.3.9 TxINA= Clock Up - TxINB = Clock Down... : 192 13.3.10 TxINA = Up/Down - TxINB = Ext Clock seveeee 192 13.3.1 TxINA = Trigger Up - TxINB = Trigger Down .......... ' 192 13.3.12 TxINA = Up/Down - TxINB = VO. 193 13.3.13 Autodiscrimination Mode ......... : Es 193 13.3.14 TxINA = Trigger - TxINB = Ext. Clock 193 1.3.15 TxINA = Ext. Clock - TxINB = Trigger 193 13.3.16 TxINA = Trigger - TxINB = Gate 193 13.4 OUTPUT PIN ASSIGNMENT .. cose . 194 13.5. INTERRUPT AND DMA . ce a 7 196 13.5.1. Timer Interrupt ae | ise 13.5.2. Timer DMA . 196 13.5.3 DMA Pointers. 196 13.5.4 Priority During The DMA Transactions 197 13.5.5 The DMA Swap Mode 197 13.56 The DMAEnd Of Block interrupt Routine 198 13.5.7 DMA Software Protection 198 13.6 TIMER DMA EXTERNAL MODES ON I/O PORTS. . eee 198 13.6.1 CMO Channel External Mode ...... : eS 198 13.6.2 CPO Channel In External Mode 198 43.6.3 DMAChannel Synchronization .....s...seosseesseeee ee 199 13.7 REGISTER DESCRIPTION 0.2.00. 7 7 200 13.7.1 Register 0 (REGOR) Registers. . 201 13.7.2 Register 1 (REGIA) Registers .. 201 13.7.3 Compare 0 (CMPOR) Registers .........-- - 201 13.7.4 Compare 1 (CMP1A) Registers : sees : 201 13.7.5 Timer Control Register (TCR) 202 13.7.6 Timer Mode Register (TMR) 202 13.7.7 External Input Control Register(ICR) npn e209) 13.7.8 Prescaler Register (PRSR) 204 13.7.9 Output A Control Register (OACR) sees 204 13.7.10 Output B Control Register (OBCR) oe eevee 208 13.7.11 Flag Register (FLAGR) 205 13.7.12 Interrupt/DMA Mask Register (IDMR) 206 13.7.13 DMA Counter Pointer Register (DCPR) . -- 206 1.7.14 DMA Address Pointer Register (DAPR) ........2--s-sseesseereeneeeess . 207 13.7.15 Interrupt Vector Register (IVR) 207 13.7.16 Interrupt/DMA Control Register (IDCR) - 208 1.7.17 VO Connection Register (IOCR)... 208 ‘THOMSON LECTGENERAL INDEX Pages Number 14 SERIAL COMMUNICATIONS INTERFACE soos 209 14.1. INTRODUCTION ........... . . 209 14.2 FUNCTIONAL DESCRIPTION ............ 210 14.21. Serial Frame Format see 210 14.22 Clocks And Serial Transmission Rates 213 14.23. Input Signals 215 14.2.4 Output Signals ... . 215 14.3. INTERRUPTS AND DMA 215 14.3.1 Interrupts 215 14.32 DMA 217 14.4 CONTROL REGISTERS 217 15 AID CONVERTER .. . 225 15.1 INTRODUCTION : 225 15.2 FUNCTIONAL DESCRIPTION . . 226 15.2.1. Operational Modes eevee 226 15.2.2. Synchronisation .- 226 15.2.3 Analog Watchdog 227 15.2.4 Power down Mode .. 227 15.3 INTERRUPT .. 229 15.4 REGISTERS vee 230 15.4.1 Register Mapping... 230 15.4.2 Data Registers (DiR) .. 230 15.4.3 Lower Threshold Registers (LTIR) 231 15.4.4 Compare Result Register (CRR) .. 231 15.45 Control Logic Register (CLR) 232 15.4.6 Interrupt Control Register (ICR). son. 233 15.4.7 Interrupt Vector Register (IVR)... .. 233 16 SOFTWARE DESCRIPTION 235 16.1 ADDRESSING MODES 235 16.1.1 Register Addressing Modes 238 16.1.2 Memory Addressing Modes 239 162 INSTRUCTIONSET ............ 242 16.2.1 ST9 Processor Flags 248 16.2.2 Condition Codes 248 16.2.3 Notation 249 16.3 INSTRUCTION SUMMARY 251 REGISTER MAP cae 283 17 ELECTRICAL CHARACTERISTICS -. 287 G7 Sonn 10GENERAL INDEX ST90E40 ST90T40 1 DESCRIPTION 14. GENERAL DESCRIPTION 1.2 PIN DESCRIPTION 1.3 VO PORT ALTERNATE FUNCTIONS 1.4 MEMORY 1.5 EPROM PROGRAMMING 1.5.1 Eprom Erasing 1.5.1 A/D CONVERTER ST90R40 1 DESCRIPTION 1.4 GENERAL DESCRIPTION 1.2 PIN DESCRIPTION 1.3. VO PORT ALTERNATE FUNCTIONS 1.4 | MEMORY APPLICATION NOTES (AN411/1292 SYMBOLS.INC AN413/1292 INITIALIZATION OF THE ST9 AN415/1092 USING THE I?C-bus PROTOCOL WITH THE ST9 AN418/1292 EXTERNAL DMA MODE-/O DATA TRANSFER WITH TIMER AN421/1292 STACK OVERFLOW DETECTION USING WATCHDOG/TIMER eyereuea FREQUENCY DOUBLER DEMONSTRATION YSTE! eg THOMSON __ Pages Number 308 308 309 309 312 312 312 325 329 331 331 332 332 335 337 339 413 4a7 477 483INTRODUCTION ‘ST9 APPLICATION TAILORED MCU The ST9 family of 8/16 bit Microcontrollers (MCUs) was designed afer the requirements of the most advanced applications in computer, consumer, telecom, industrial and automotive Segments. Processed with the same proprietary CMOS EPROM and EEPROM technologies that have established SGS- THOMSON as a world leading supplier of non-volatile memories, the ST9 provides high speed computing with reduced power consumption. Builtaround a high performance, registerbased core, the ST9 family offers different program and data memory sizes and a wide range of on-chip peripherals to meet the needs of most systems. Time to market is minimized with ST9's well defined, socket compatible, evolution path, from application evalu- ation with EPROMSs, to prototyping using OTPs, up to the high volume production using cost effective ROM versions. All standard ST9 devices include a Serial Peripheral interface, a Watchdog Timer to ensure system integrity against externally generated malfunctions, bit configurable I/Os, prioritizable Interrupts for real-time data han- dling, and DMA for fast data transfers with handshake (HSHK), {n addition ST9 family variants include up to three Multi-Function Timers, two Serial Communication Interfaces (SCI), an Analog to Digital converter (A/D) and On-Screen Display and Data-Slicer for TV control REGISTER BASED ARCHITECTURE The Register based architecture provides more efficient data handling and reduced code size compared to an accumulator based MCU. It also provides the capability for fast context switching. 224 of the 256 8-bit Registersin the ST9 Register File are available as accumulators, index registers, or stack pointers, andcan be cascaded to perform alll these functions as 16-bit registers. The remaining registers are dedicated to system and peripheral control This architecture is common to all ST9 devices. FLEXIBLE 1/0 The flexibilty of the ST9 V/O pins allow designers to match the MCU to the application, and not the application tothe MCU. Most /Os can be individually programmed as input (TTL or CMOS thresholds), output (open-drain or push- pull), bidirectional, or as the Alternate Function of a peripheral, such as a Timer or an A/D Converter. COMPREHENSIVE SCI Serial communication is easily implemented, using formats and facilities offered by the ST9 Serial Communi- cation Interface. MEMORY BUS | STANDARD DEDICATED t t fot’ PERIPHERALS Twin. St = sllz Brie 2! i Ale 5,| | 8 A ee El |e #3] |8 E]/e]| a] \2 ‘Big! £15) |e Zz1|¢$ Sal | “2 Rigikig: |/"3 8} Jj zo] | 5 z g ERIE: || g -yE REGISTER BUS/INTERRUPT-DMA o cl a roo 644 ‘ST9 Architectural Block Diagram 12—_________———_ INTRODUCTION This peripheral provide full flexibility in character format (5,6,7,8 databits), odd, even or no parity, address bit, 1, 1.5, o2 stop bits in asynchronous mode, and an integral baud rate generator allowing communication at up t0 370k baud in asynchronous mode or 1.5Mbyte/s in synchronous mode Industrial, telecom and communication systems users can furthermore benefit from the self-test and address bit wake-up facility offered by the character search mode. FAST A/D WITH ANALOG WATCHDOG Upto 8 analog input voltages can be sequentially converted by the Analog to Digital converter including on-chip sample and hold, The 1111s conversion time, and the possibility to trigger conversions either by the on-chip timers, or by external sources, allows real time processing of analog data. CPU loading is also reduced by the analog watchdog on two channels, the peripheral interrupts the ST9 when the analog input voltage moves out of a preset threshold window. UNIVERSAL SPI Auniversal Serial Peripheral Interface, providing basic: I°C-bus, Microwire-Bus and S-BUS: functionality, allows: efficient communication with low-cost external peripherals or serial access memories such as EEPROMSs. MULTI-FUNCTION TIMERS The 16 bit up/down counter operating in 13 modes gives the ST9 Multi-function Timer the possibility to cover most application timing requirements, Two input pins, programmable as external clock, gate or trigger, allow 16 modes of operation, including auto- discrimination of the direction of externally generated signals. Pulse Width Generation can easily be implemented, using the overflow/underflow signal and the two 16 bit ‘comparison registers, each of them able to independently set, reset, toggle or ignore two output bits. ‘The Muttifunction Timer outputs may also generate interrupts for system scheduling, and trigger DMA trans- actions of a data byte to or from a data table in memory through an I/O Port with handshake. ST90E40 yy S6ssTHOMsoN TIAOECTPOWES 13INTRODUCTION —————_____ ON-SCREEN DISPLAY Interactive information display for television control is easily implemented with the powerful ST9 On-Screen Display. With up to 34 characters in 15 rows, and colour, italic, underline, flash, tranparent and fringe options, the 128 character set can be adapted for all needs. DATA-SLICER Closed Caption Data can be easily extracted from the video signal with the ST9 Data Slicer. When used in conjunction with the ST9 On-Screen Display, a powerful TV controller can be achieved with the minimum of components. POWERFUL INSTRUCTION SET ‘The ST9 has 14 addressing modes and instructions (including multiply, divide, table search and block move) to cover all data manipulation needs, bit, byte and word, at the speed required by even the most demanding control application {ts instruction set was conceived to facilitate the software designer's task, and to improve programming efficiency. FULL DEVELOPMENT SUPPORT ST9 Development Tools are designed for application development efficiency. A high level macro assembler (with IF/THEN, DO/WHILE, SYSTEM/CASE, PROCedure C language con- structs in the assembler) is available, as well as an incremental linker able to link up to 16 Mbytes of program and data, a library maintainer for archiving common software routines and Software Simulation of the code execution, allowing off-line code development and timing analysis. The validated ANSI standard C Compiler generates optimised code for the ST9. In addition a GNU C cross- compiler and Linker allows development support under the Microsoft Windows 3™ environment. Cost effective emulation is provided either through a software module running on standard PCs, or with the ‘ST9 Starter Kit, offering hardware emulation capability. Full real time hardware emulation is provided by the ST9-HDS system. 14ST9 FAMILY OVERVIEWST9 FAMILY OVERVIEW All devices have 256 byte Register File with 224 General Purpose Registers (Accumulators/RAM), TWD and SPI Peripherals. EPROM DEVICE Rom |orPRom”| Ram | EEPROM | MFT) sci | A/D | BSS | MAX |HSHK 8 8 x8 8 Inputs v0 sT9026 16K 256 a] 40} 1 sT9027 16K 256 +] 4 so} 4 sT9028 16K 256 le 36] 1 ST90E26 16k 256 +] 4 40} 4 ST90E27 16K 256 Ma se] 4 STS0E28 16k 256 ie a6 ST90T26 16K") 256 + ]4 40} 4 ST90T27 16K" 256 14 se} 4 ST90T28 16K" 256 +] 4 as | 1 ST9OR26 : 256 +44 so] 4 sT9030 8k 246 ss | 1 STS0E30 8k 2/1} 28 se | 1 ‘ST90T30 8k" eld 8 56 | 1 ST9OR30 : - 2|1]8 40} 1 sT9032 12K : 2]/4]8 se] 4 sT9036 16K 256 2/1]6 40] 4 STS0E36 16k 256 40 ST90T36 16K" 256 40 stso40 | 16K 256 512 2}1]8 eft ‘ST90E40 16k 256 B12 2/1]. se} 1 ‘sT90T40 16K" 256 512 2/1] 56 | 1 ST90R40 - 7 256 512 2} 1 | 8 40] 4 ST9OR50 : 3 | 2]a]1 | s| 2 ‘ST90R51 - - a] 2]|eaf1|s| 2 T9054 32k 1280 3 }2]ea]14 |] .2 ‘ST90ES4 32k 1280 a}2]|s8]1 |e STOORS4 1280 a3}2]|ea 1 || 2 sTe292 24K 384 ae 4a ‘ST92E92 2ak 304 3) a sT92T92 24K") 384 3? a4 sT9293 32k 640 42) 41 ‘ST92E93 32k 640 ae a4 ST92T93 sak") 640, ae 41 Keys TWD —_Timer/Watchdog SCI Serial Communications Interface SPI Serial Peripheral interface AD bit 8 channel A/D Converter MFT Multi-Function Timer BSS —_Bankswitch logic 16M byte address range vo lin -TLUCMOS, Out : OD/PP HSHK — # Ports with Handshake Capability Alternate Functional Peripheral Notes: 1. OTP ROM = One Tima Programmable 2 BbIAD Converter GEST 7ST9 FAMILY OVERVIEW PACKAGE (Operating temperature) DEVICE Fae (Operating temperature) PAGE DIP Lec ore T9026 Pas (1.6) 9 19027 Pao (18) 9 st9028 Pad (1.6) 9 ST90E26 casw (1) " ST90E27 Caow (1) n ST90E28 caaw (1) n ST90T26 Pas (6) 1" sT90T27 Pao (6) i" ST90T28 Pas (6) " ST90R26 Psa (6) 3 sT9030 pea (1.6) | Pao (1) 5 ST90E30 caaw (1) Bow (1) 7 ST90T30 Pea (6) Peo (1) 7 ST90R30 Pos (6) 19 9032 Pes (16) | PaO (1) at T9096 Pos (1.6) | PaO (1) 23 ST90E36 co8w (1) caow (1) 25 ST90T36 P68 (6) Peo (1) 2 T9040 Pes (16) | P80 (1) 27 ST90E40 c88W (3) Bow (1) 2 ST90T40 an) Peo (1) 29 ST90R40 PsB (6) 31 ST90R50 Pee (6) a | ST90R61 Peo (1) 35 $9054 Ped (1.6) 37 ST90E54 caaw (1) 39 STOORS4 Ped (6) 4a sTe2e2 sp, STM,| PS42_ (1) 43 ST92E92 DSL, PWM} CS42W (1) 45 steetee Psa (1) 4 sTe293 Pse2_ (1) 47 ST92E93 oso, sT™m | csaaw (1) 49 sTe2T9a PSa2_(1) 48 Keys: O80 On Screen Display Pax Plastic Package STM Slice Timer PSix Plastic Shrink DIP Package DSL _Data Slicer extracting Closed Caption Data. CxxW PWM Pulse Width Modulation outputs mperature Ranges : CSexW Ceramic Package with window Ceramic Shrink DIP Package with window (1)One version available, 0t0+70°C _ (6)One version available, -40 10+85°C. (1,6)Two versions available, 0 to +70°C and -40 to+85°C. 18STA SGS-THOMSON e MICROELECTRONICS $T9026,ST9027,ST9028 16K ROM HCMOS MCUs WITH RAM = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes = Minimum instruction cycle time: 500ns (12MHz internal) = 16K bytes of ROM, 256 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = 48-pin Dual in Line Plastic package for ST9026 = 40-pin Dual in Line Plastic package for ST9027 = 44-lead Plastic Leaded Chip Carrier package for sT9028 = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features = Up to 40 fully programmable 1/0 pins # Upto 8 external plus 1 non-maskable interrupts «= 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = 16-bit Multifunction Timer, with an 8-bit prescaler and 13 operating modes = Serial Communications Interface with asynchro- nous and synchronous capability = Rich Instruction Set and 14 Addressing modes «= Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators = Real Time Operating System = Windowed and One Time Programmable EPROM parts available for prototyping and pre-produc- tion development phases January 1993, PDIP4O PDIPas (Ordering Information at the end of the Datasheet) This is short overview of an ST9 Family Member. Please contact SGS-THOMSON for further information. 19$T9026,27,28 GENERAL DESCRIPTION The ST9026, $T9027 and $T9028 (following men- tioned as ST902X) are ROM members of the STS family of microcontrollers, completely developed and produced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. The ROM parts are fully compatible with their EPROM versions, which may be used for the proto- typing and pre-production phases of development, and can be configured as: standalone microcontrol- lers with 16K bytes of on-chip ROM, microcontrollers. able to manage external memory, or as parallel proo- essing elements in a system with other processors and peripheral controllers. The nucleus of the ST902X is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescalgr, a Serial Peripheral Interface supporting S-bus, |°C-bus and IM-bus Interface, plus two 8 bit VO ports. The Core has independent memory and register buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. Figure 1. ST902X Block Diagram The powerful /O capabilities demanded by micro- controller applications are fulfilled by the ST902X with up to 40 1/0 lines dedicated to digital Input/Out- put. These lines are grouped into up to five 8 bit I/O Ports and.can be configured on abit basis under soft- ware control to provide timing, status signals, an ad- dress/data bus for interfacing external memory, timer inputs and outputs, external interrupts and se- rial or parallel V/O with or without handshake. ‘Three basic memory spaces are available to support this wide range of configurations: Program Memory (internal and external), Data Memory (internal and ex- temal) and the Register File, whichincludes the control and status registers of the on-chip peripherals. The 16 bit MultiFunction Timer, with an 8 bit Pres- caler and 12 operating modes allows simple use for complex waveform generation and measurement, PWM functions and many other system timing func- tions by the usage of the two associated DMA chan- nels for each timer. Completing the device is afull duplex Serial Commu- nications Interface with an integral 110 to 375000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programmable format) and associated addressiwake-up option, plus two DMA channels. 16k Bytes 256 Bytes 286 Bytes Recisren Fie CPU tle gil smcnoeL 20 cel alae eer] [tee bfeme eas” [wie] u ood 8 u - nr ‘SGS-THOMSONk SGS-THOMSON ST90E26,E27,E28 SF, MicRoELecTROMes ST90T26,127,128 16K EPROM HCMOS MCUs WITH RAM = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes «= Minimum instruction cycle time: 500ns (12MHz internal) = 16K bytes of EPROM or OTP ROM 256 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = 48-pin Window Dual in Line Ceramic Multilayer package for ST90E26 = 40-pin Window Dual in Line Ceramic Multilayer package for ST90E27 = 44-lead Window Ceramic Leaded Chip Carrier package for ST90E28 = 48-pin Dual in Line Plastic package for ST90T26 = 40-pin Dual in Line Plastic package for ST90T27 «= 44-lead Plastic Leaded Chip Carrier package for ST90T28 = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features (Ordering Information at the end of the Datasheet) = Up to 40 fully programmable VO pins = Up to 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = 16-bit Multifunction Timer, with an 8-bit prescaler and 13 operating modes = Serial Communications Interface with asynchro- nous and synchronous capability = Rich Instruction Set and 14 Addressing modes = Division-by-Zero trap generation « Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators «= Real Time Operating System = Compatible with ST9026/27/28 16K ROM device 21ST90E26,E27,E28 - ST90T26,T27,T28 GENERAL DESCRIPTION ‘The ST90E26, ST90E27 and STIOE2B, STIOT26, $T90T27 and ST90T28 (following mentioned as ST90E2X) are EPROM members of the ST9 family of microcontrollers, in windowed ceramic (E) and plastic OTP (T) packages respectively, completely developed and produced by SGS-THOMSON Mi- croelectronics using a proprietary n-well HMOS process. ‘The EPROM ST90E2X canbe used for the prototyp- ing and pre-production phases of development, and can be configured as: standalone microcontrollers with 16K bytes of on-chip ROM, microcontrollers able to manage external memory, or as parallel proc- essing elements in a system with other processors and peripheral controllers. The nucleus of the ST90E2X is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescaler, a Serial Peripheral interface supporting S-bus, I?C-bus and IM-bus Interface, plus two 8 bit VO ports. The Core has independent memory and register buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. Figure 1. ST90E2X Block Diagram The powerful I/O capabilities demanded by micro- controller applications are fulfilled by the ST90E2X with up to 40 I/O lines dedicated to digital Input/Out- put. These lines are grouped into up to five 8 bit YO Ports and.can be configured on abit basis under soft- ware control to provide timing, status signals, an ad- dress/data bus for interfacing external memory, timer inputs and outputs, external interrupts and se- rial or parallel /O with or without handshake. Three hasic memory spaces are available to support this wide range of configurations: Program Memory (internal and external), Data Memory (internal and external) and the Register File, which includes the control and status registers ofthe on-chip peripher- als. The 16 bit MultiFunction Timer, with an 8 bit Pres- caler and 12 operating modes allows simple use for complex waveform generation and measurement, PWM functions and many other system timing func- tions by the usage of the two associated DMA chan- nels for each timer. Completing the devices a full duplex Serial Commu- nications Interface with an integral 110 to 375000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programmable format), and associated address/wake-up option, plus two DMA channole. 1k Bytes cc EPROM 256 Bytes ecisTeR FiLe ‘Bt TIMER 7 WATCHOOG + SP tl Ti I Il ft if uo PORT o ( AddrosiData | 10 Pont 2 scr with ow wire HANDSHAKE oH ) 1 16-00 TMER | wird Dik BE OS § u Ky S5S:THOMSON ic 22SI. SGS-THOMSON MICS ® MICROELECTRO ST90R26 ROMLESS HCMOS MCU WITH RAM = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes # Minimum instruction cycle time: 500ns (12MHz internal) = 256 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = Romless to allow maximum external memory ca- pability = 48-lead Plastic Dual in Line package for ST90R26 = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features = 24 fully programmable I/O pins 1 Up to 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = 16-bit Multifunction Timer, with an 8-bit prescaler and 13 operating modes = Serial Communications Interface with asynchro- nous and synchronous capability # Rich Instruction Set and 14 Addressing modes «= Division-by-Zero trap generation «= Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators « Real Time Operating System = Compatible with ST9026 16K ROM device (also available in windowed and One Time Programmable EPROM packages danuary 1993, PpIPas |__ (Ordering inormation atthe end ofthe Datasheet) This is shor overview of an ST Family Member, Please contact SGS-THOMSON for tuther information. 23ST9OR26 GENERAL DESCRIPTION The ST90R26 is a ROMLESS member of the STO family of microcontrollers, completely developed and produced by SGS-THOMSON Microelectronics. using a proprietary n-well HCMOS process. The ROMLESS part may be used for the prototyping and pre-production phases of development, and of- fers the maximum in program flexibilty in production systems, ‘The ROMLESS ST90R26 can be configuredas.ami- crocontroller able to manage external memory, or as a parallel processing element in a system with other processors and peripheral controllers. The nucleus of the ST9OR26 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescales, a Serial Peripheral interface supporting S-BUS, |°C-bus and IM-bus Interface, plus memory interface. The Core has independent memory and register buses allowing a high degree of pipelining to, add to the efficiency of the code execution speed of the extensive instruction set. The powerful I/O capabilities demanded by micro- controller applications are fulfilled by the ST20R26 Figure 1. ST90R26 Block Diagram with up to 32 1/0 lines dedicated to digital InpuvOut- put. These lines are grouped into up to four & bit /O Ports andcan be configured on abit basis under soft- ware control to provide timing and status signals, ad- dress lines, timer inputs and outputs, analog inputs, external interrupts and serial or parallel /O with or without handshake. Three memory spaces are available: Program Mem- ory (external), Data Memory (internal and external) and the Register File, which includes the control and status registers of the on-chip peripherals. The 16 bit MultiFunction Timer, with an 8 bit Pres- caler and 12 operating modes allow simple use for complex waveform generation and measurement, PWM functions and many other system timing func toonsby the usage ofthe two associated DMA chan- nels. Completing the device is atull duplex Serial Commu- nications Interface with an integral 110 to 375000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programmable format) and associated address/wake-up option, plus two DMA channels. 258 Bytes TEBN TER) WATCHDOG + SFr aM on — re Tt | ars 24 aorere,) froze] -: ain sre} itt) [oie] ge o6GCO g gSI. SGS-THOMSON e MICROELECTRONICS ST9030 8K ROM HCMOS MCU WITH A/D CONVERTER = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes = Minimum instruction cycle time: 500ns (12MHz internal) = 8K bytes of ROM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = 80-pin Plastic Quad Flat Pack package for ST3030Q = 68-lead Plastic Leaded Chip Carrier package for ST9030C = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features = Up to 56 fully programmable V/O pins = Up to 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Two 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes = 8 channel 8 bit Analog to Digital Converter, with ‘Analog Watchdogs and external references = Serial Communications Interface with asynchro- nous and synchronous capability # Rich Instruction Set and 14 Addressing modes = Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators « Real Time Operating System = Windowed and One Time Programmable EPROM parts available for prototyping and pre-produc- tion development phases January 1993 (Ordering Information at the end of the Datasheet) This is short overview of an ST9 Family Member. Please contact SGS-THOMSON tor further information. 25ST9030 GENERAL DESCRIPTION The $T9030is ROM member of the ST9 family of mi- crocontrollers, completely developed and produced by SGS-THOMSON Microelectronics using a proprie- tary n-well HCMOS process. The ROM part is fully compatible with its EPROM versions, which may be used for the prototyping and pre-production phases of development, and can be configured as standalone microcontrollers with 8K bytes of on-chip ROM, microcontrollers able to man- age oxternal memory, or as parallel processing cle- ments in a system with other processors and peripheral controllers. The nucleus of the ST9030 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescales, a Serial Peripheral interface supporting S-BUS, I°C-bus and IMBUS Interface, plus two 8 bit VO ports. The Core has independent memory and register buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. The powerful /O capa- bilities demanded by microcontroller applications are fulfilled by the ST9030 with 56 /O lines dedicated to digital Input/Output. These lines are grouped into seven 8 bit /O Ports and can be configured on a bit Figure 1. ST9030 Block Diagram basis under software control to provide timing, status signals, an address/data bus for interfacing external memory, timer inputs and outputs, analog inputs, ex- ternal interrupts and serial or parallel /O with or with out handshake. ‘Three memory spaces are available: Program Mem- ‘ory (internal and external), Data Memory (external) and the Register File, which includes the control and status registers of the on-chip peripherals. Two 16 bit MultiFunction Timers, cach with an & bit Prescaler and 13 operating modes allow simple use for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. In addition there is an 8 channel Analog to Digital Converter with integral sample and hold, fast 1141s conversion time and 8 bit 1/2 LSB resolution. An Analog Watchdog fea- ture is included for two input channels. Completing the devices atull duplex Serial Commu- nications Interface with an integral 110 to 375000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programmable format) and associated address/wake-up option, plus two DMA channels. 2x Bytes ok 258 Bytes recisren Fue} tt LUT gt worn 4 S3 | itt t - vo Porte | 10 PORT 2 [roar Ansiog Inte Lf catiden | [wntttne wow kod of 26Er SGS-THOMSON » MICROELEC' (RONICS ST90E30 ST90T30 _8K EPROM HCMOS MCUs WITH A/D CONVERTER » Register oriented 8/16 bit CORE with RUN, WFI and HALT modes = Minimum instruction cycle time: 500ns (12MHz internal) = 8K bytes of EPROM or OTP'ROM 224 general purpose registers available as RAM, accumulators or index registers (Register File) = 80-pin Plastic Quad Flat Pack package for ST90T30Q = 68-lead Plastic Leaded Chip Carrier package for ST90T3OC ‘= 80-pin Window Ceramic Quad Flat Pack pack- age for ST90E30G = 68-lead Window Ceramic Leaded Chip Carrier package for STSOE3OL = DMA controller, Interrupt handler and Serial Po ripheral Interface as standard features = Up to 56 fully programmable /O pins = Up to 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Two 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes = 8 channel 8 bit Analog to Digital Converter, with Analog Watchdogs and external references 1» Serial Communications Interface with asynchro- nous and synchronous capability « Rich Instruction Set and 14 Addressing modes «= Division-by-Zero trap generation » Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators » Real Time Operating System = Compatible with ST9030 8K ROM device January 1993 caFPsow cLocesw (Ordering Information atthe end of the Datasheet) This is short overview of an ST9 Family Member, Please contact SGS-THOMSON for further information, 27ST90E30 - ST90T30 GENERAL DESCRIPTION The ST90E30 and ST90T30 (following mentioned as ST90E30) are EPROM members of the ST9 fam- ily of microcontrollers, in windowed ceramic (E) and plastic OTP (T) packages respectively, completely developed and produced by SGS-THOMSON Mi- croelectronics using a proprietary n-well HCMOS process. ‘The EPROM ST90E30 may be used for the prototyp- ing and pre-production phases of development, and can be configured as: standalone microcontrollers: with 8K bytes of on-chip ROM, microcontrollers able to manage external memory, or as parallel processing elements in a system with other processors and pe- ripheral controllers. The nucleus of the ST90E30 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescales, a Serial Peripheral interface supporting S-BUS, °C Bus and IM BUS Interface, plus two 8 bit VO ports. The Core has independent memory and register buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. The powerful /O capabilities demanded by micro- controller applications are fulfilled by the ST90E30 with up to 56 1/O lines dedicated to digital Inpu/Out- put. These lines are grouped into up to seven 8 bit /O Figure 1. ST90E30 Block Diagram Ports andcanbe configured on abit basis under sott- ware control to provide timing, status signals, an ad- dress/data bus for interfacing external memory, timer inputs and outputs, analog inputs, external in- terrupts and serial or parallel /O with or without handshake. ‘Three memory spaces are available: Program Mem- ory (internal and external), Data Memory (external) and the Register File, which includes the control and status registers of the on-chip peripherals. Two 16 bit MultiFunction Timers, each with an 8 bit Prescaler and 13 operating modes allow simple use for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. In addition there is an 8 channel Analog to Digital Con- verter with integral sample and hold, fast 111s conver- sion time and 8 bit resolution. An Analog Watchdog feature isincluded for two input channels. Completing the devices a ull duplex Serial Commu- nications Interface with an integral 110 to 375000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programmable format) and associated addressiwake-up option, plus two DMA channels. g 8k Bytes PROM 256 Bytes REGISTER FILE 7e-BK TIMER | WATCHOOG » SP aa vo pont 7 wort own (se CPU TItl tf REGISTER BUS Tf LI il —] woronre | [ro roars] [vo roma] [uo roma} [2x eormmen| [vo ronre ne ve vont s jc Aséesxdata | | CAdiree | | ysery | | Crimens ) wirw oun | |‘ anaoa nous —“]_converren | [wii navosnane vcore k57 S&S-THOMSON YY, wicnaszcmanes 28Gir SGS-THOMSON | IT, MICROELECTRONICS ST90R30 ROMLESS HCMOS MCU WITH A/D CONVERTER ADVANCE DATA = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes = Minimum instruction cycle time: 500ns (12MHz internal) = 224 general purpose registers available as RAM, accumulators or index registers (Register File) = Romiless to allow maximum external memory ca- pability ree = 68-lead Plastic Leaded Chip Carrier package (Ordering Information at the end of the Datasheet) = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features = 40 fully programmable /O pins = Up to 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Two 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes = 8 channel 8 bit Analog to Digital Converter, with Analog Watchdogs and external references = Serial Communications Interface with asynchro- nous and synchronous capability = Rich Instruction Set and 14 Addressing modes «= Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators = Real Time Operating System = Compatible with ST9030 8K ROM device (also available in windowed and One Time Programma- ble EPROM packages) January 1993 ‘This is short overview of an ST9 Family Member. Please contact SGS-THOMSON tor futher information 29ST90R30 GENERAL DESCRIPTION The ST9OR30 is a ROMLESS member of the ST9 family of microcontrollers, completely developed and produced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. ‘The ROMLESS part may be used for the prototyping and pre-production phases of development, and of- fers the maximum in program flexibility in production systems. ‘The ROMLESS ST90R30.can be configuredas ami- crocontroller able to manage external memory, or as a parallel processing element in a system with other processors and peripheral controllers. The nucleus of the ST90R30 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescaler, a Serial Peripheral Interface supporting S-BUS, |°C-bus and IM-bus interface, plus memory interface. The Core has independent memory and register buses allowing ahigh degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. The powerful /O capabilities demanded by micro- controller applications are fulfilled by the STSOR30 with up to 40 I/O lines dedicated to digital InpuvOut- put. These lines are grouped into up to five 8 bit /O Figure 1. ST90R30 Block Diagram Ports andcan be configuredon abitbasis under soft- ware control to provide timing and status signals, timer inputs and outputs, analog inputs, external in- terrupts and serial or parallel /O with or without handshake. Three memory spaces are available: Program Mem- ory (external), Data Memory (external) and the Reg- ister File, which includes the control and status registers of the on-chip peripherals. Two 16 bil MulliFuriction Timers, each wilh ar 8 bit Prescaler and 13 operating modes allow simple use for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. In addition there is an 8 channel Analog to Digital Converter with integral sample and hold, fast 111s, conversion time and 8 bit resolution. An Analog Watchdog feature is included for two input channels. Completing the device is afull duplex Serial Commu- nications Interface with an integral 110 to 375000 baud rate generator, asynchronous and 1 5Mbyte/s synchronous capability (fully programmable format) and associated address/wake-up option, plus two DMA channels. T J ! | set |_| vo pont Tee one) [Berm wareno0e - em] | eosrenrae| | CPU | [neo ll C LI 30 T | Trt Tf Tf T t i Le a hs ll ee = fontaine] u sg ge UOT KS: THOMSONky SGS-THOMSO! Vf, alban ST9032 12K ROM HCMOS MCU WITH A/D CONVERTER = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes # Minimum instruction cycle time: 500ns (12MHz internal) = 12K bytes of ROM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = 80-pin Plastic Quad Flat Pack package for ST9032Q = 68-lead Plastic Leaded Chip Carrier package for ST9032C = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features = Up to 56 fully programmable /O pins = Up to 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Two 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes = 8 channel 8 bit Analog to Digital Converter, with ‘Analog Watchdogs and external references « Serial Communications Interface with asynchro- nous and synchronous capability » Rich Instruction Set and 14 Addressing modes « Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators = Real Time Operating System = Windowed and One Time Programmable EPROM parts available for prototyping and pre-produc- tion development phases « Upward compatible with ST9030 January 1993 PRELIMINARY DATA (Ordering Information at the end of the Datasheet) ‘This is short overview of an ST@ Family Member. Please contact SGS-THOMSON for futher information. 31ST9032 GENERAL DESCRIPTION The ST9032 device are ROM members of the ST family of microcontrollers, completely developed and produced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. The ROM parts are fully compatible with their EPROM versions, which may be used for the proto- typing and pre-production phases of development, and can be configured as standalone microcontrol- lers with 12K bytes of on-chip ROM, microcontrollers able to manage external memory, oras parallel proc- essing elements in a system with other processors and peripheral controllers. The nucleus of the $9032 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescales, a Serial Peripheral Interface supporting ‘S-BUS, I°C Bus and IM BUS Interface, plus two 8 bit VO ports. The Core has independent memory and register buses allowing ahigh degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. The powerful l/O capa- bilities demanded by microcontroller applications are fulfilled by the ST9032 with up to 56 VO lines dedicated to digital Input/Output. These lines are grouped into up to seven 8 bit I/O Ports and can be Configured on a bit basis under software control to Figure 1. ST9032 Block Diagram provide timing, status signals, an address/data bus for interfacing external memory, timer inputs and outputs, analog inputs, external interrupts and serial or parallel /O with or without handshake. ‘Three memory spaces are available: Program Mem- ory (intemal and external), Data Memory (external) and the Register File, which includes the control and, status registers of the on-chip peripherals. ‘Two 16 bit MultiFunction Timers, each with an 8 bit Prescaler and 13 operating mades allow simple use. for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. In addition there is an 8 channel Analog to Digital Converter with integral sample and hold, fast 111s conversion time and 8 bit LSB resolution. An Analog Watchdog feature is, included for two input channels ‘Completing the device is a full duplex Serial Commu- nications Interface with an integral 110 to 375000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programmable format) and associated address/wake-up option, plus two DMA channels. rit a q eee! = t TEI TIMER 7 WATCHOOG + SPI a cone itt oma, scr) tf a ee same cH eatin | onl ne uo oE Ts Go oil go Sr st 32GS-THOMSON MICROELECTRONICS ST9036 « Register oriented 8/16 bit CORE with RUN, WFI and HALT modes = Minimum instruction cycle time: 500ns (12MHz internal) # 16K bytes of ROM, 256 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = 80-pin Plastic Quad Flat Pack package for ST9036Q_ = 68-lead Plastic Leaded Chip Carrier package for ‘$T9036C = DMA controller, Interrupt handler and Serial Pe ripheral Interface as standard features = Up to 72 fully programmable /O pins = Up to 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Two 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes = 8 channel 8 bit Analog to Digital Converter, with Analog Watchdogs and external references » Serial Communications Interface with asynchro: nous and synchronous capability «= Rich Instruction Set and 14 Addressing modes «= Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver. graphic oriented de- bugger and hardware emulators = Real Time Operating System = Windowed and One Time Programmable EPROM parts available for prototyping and pre-produc- tion development phases «= Upward compatible with ST9030 and ST9032, vanuary 1993 ~ 16K ROM HCMOS MCU WITH RAM AND A/D CONVERTER PRELIMINARY DATA (Ordering Information at the end of the Datasheet) This is chort overview of an STS Family Member, Please contact SGS-THOMSON for further information, 33ST9036 GENERAL DESCRIPTION ‘The ST9036 is a ROM member of the ST9 family of microcontrollers, completely developed and pro- duced by SGS- THOMSON Microelectronics using a proprietary n-well HCMOS process. ‘The ROM device is fully compatible with the EPROM version (ST90E36), which may be used for the pro- totyping and pre-production phases of development, and can be configured as: a standalone microcon- troller with 16K bytes of on-chip ROM, a microcon- troller able to manage external memory, or as a parallel processing element in a system with other processors and peripheral controllers. The nucleus of the ST9036 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescalgr, a Serial Peripheral Intrface supporting S-bus, |°C-bus and IM-bus Interface, plus two 8 bit VO ports. The Core has independent memory and register buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set, The powertul /O capabilities demanded by micro- controller applications are fulfiled by the ST9036 with up to 56 I/O lines dedicated to digital Input/Out- put. These lines are grouped into up to seven 8 bit VO Ports and can be configured on a bit basis under, software control to provide timing, status signals, an address/data bus for interfacing external memory, Figure 1. ST9036 Block Diagram timer inputs and outputs, analog inputs, external in- terrupts and serial or parallel /O with or without handshake. ‘Three basic memory spaces are available to support this wide range of configurations: Program Memory (internal and extemal), Data Memory (internal and external) and the Register File, which includes the control and status registers of the on-chip perpher- als. ‘Two 16 bit MultiFunction Timers, each with an 8 bit Prescaler and 13 operating modes allow simple use for complex waveform generation and measure- ment, PWM tunetions and many other system timing functions by the usage of the two associated DMA channels for each timer. In addition there is an 8 channel Analog to Digital Con- verter with integral sample and hold, fast 111s conver- sion time and 8 bit resolution. An Analog Watchdog feature isincluded for two input channels. Completing the devices atull duplex Serial Commu- nications Interface with an integral 110 to 375,000 baud rate generator, asynchronous and 1 5Mbyte/s synchronous capability (fully programmable format) and associated address/wake-up option, plus two DMA channels. a 184 Bytes OM 250 Bytes PAM 258 Bytes recisreR Fite [ [ | | f= TIMER { WATCHDOG + SPI scl wort an | faz’ (sc CPU REGISTER t Til 2 f Tt aus ves | rt vo ront | [io ronal [uo rons], [2+ om wo pont wn vo vont s cseseestatns| [Uameese)| Jc) | [icamens 4] wine ona) [arene ines), | convene | | wnt wanaanane boy y godt g TA ‘SGS-THOMSON Gr SONSky SGS-THOMSON ‘Jf, iwncroaecrromes ST90E36 ST90T36 16K EPROM HCMOS WITH RAM AND A/D CONVERTER = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes = Minimum instruction cycle time: 50ons (12MHz internal) = 16K bytes of EPROM or OTP ROM, 256 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = 80-pin Plastic Quad Flat Pack package for ST90T36Q = 80-pin Window Ceramic Quad Flat Pack pack- age for STIOES6G = 68-lead Plastic Leaded Chip Carrier package for ST90T36C = 68-lead Window Ceramic Leaded Chip Carrier Package for STOOES6L = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features = Up to 56 fully programmable V/O pins = Up to 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Two 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes «= 8 channel 8 bit Analog to Digital Converter, with ‘Analog Watchdogs and external references «= Serial Communications Interface with asynchro- nous and synchronous capability = Rich Instruction Set and 14 Addressing modes » Division-by-Zero trap generation « Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators = Real Time Operating System = Compatible with ST9036 16K ROM device January 1993 PRELIMINARY DATA CaFPsow cLocesw (Ordering information at the end of the Datasheet) This is short overview of an ST9 Family Member. Please contact SGS-THOMSON for futher information 35ST90E36 - ST9OT36 GENERAL DESCRIPTION The ST90E36 and ST90T36 (following mentioned as ST90E36) are EPROM and OTP members of the ST9 family of microcontrollers, in windowed ceramic (E) and plastic OTP (T) packages respectively, com- pletely developed and produced by SGS-THOM- SON Microelectronics using a proprietary n-well HCMOS process. ‘The EPROM ST90E36 may be used for the prototyp- ing and pre-production phases of development, and can be configured as: standalone microcontrollers with 16K bytes of on-chip ROM, microcontrollers able tomanage externai memory, or as paraliel processing elements in a system with other processors and pe- ripheral controllers, The nucleus of the ST90E36 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescaley, a Serial Peripheral Interface supporting S-BUS, I°C Bus and IM BUS interface, plus two 8 bit VO ports. The Core has independent memory and register buses allowing ahigh degree of pipelining to adi to the efficiency of the code execution speed of the extensive instruction set. The powerful /O capabilities demanded by micro- controller applications are fulfilled by the ST90E36 with up to 56 I/O lines dedicated to digital Input/Out- put. These lines are grouped into up toseven 8 bit iO Figure 1. ST90E36 Block Diagram Ports and canbe configured on a bit basis under soft- ware control to provide timing, status signals, an ad- dressidata bus for interfacing external memory, timer inputs and outputs, analog inputs, external in- terrupts and serial or parallel /O with or without handshake. Three memory spaces are available: Program Mem- ory (internal and external), Data Memory (internal and external) and the Register File, whichincludes the con- trol and status registers of the on-chip peripherals Two 16 bit MultiFunction Timers, each with an 8 bit Prescaler and 13 operating modes allow simple use for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. In addition there is an 8 channel Analog to Digital Con- verter with integral sample and hold, fast 111s conver- sion time and 8 bit resolution. An Analog Watchdog feature is included for two input channels. Completing the device is a ull duplex Serial Commu- nications Interface with an integral 110 to 375000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programmable format) and associated addressiwake-up option, plus two DMA channels. el £ 256 Byter Ra 256 Bytes REGISTER FILE EPROM Tear TWER WATCHOOG SA] wieoma sett | CPU T Oo Bea REGSTER BS 1 I ve tt ft fl ff TItl i oo wir Oma 10 PORT § $ 3g 8 g go OU 36ky SGS-THOMSON Sf. Seca ST9040 16K ROM HCMOS MCU WITH EEPROM RAM AND A/D CONVERTER = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes ‘= Minimum instruction cycle time: 500ns. (12MHz internal) «= 16K bytes of ROM, 256 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = 512 bytes EEPROM = 80-pin POFP package for ST9040Q = 68-lead PLCC package for ST9040C = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features «= Up to 56 fully programmable V/O pins = Up to 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Two 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes # 8 channel 8 bit Analog to Digital Converter, with Analog Watchdogs and external references «= Serial Communications Interface with asynchro- nous and synchronous capability «= Rich Instruction Set and 14 Addressing modes = Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators = Real Time Operating System = Windowed and One Time Programmable EPROM parts available for prototyping and pre-produc- tion development phases = Upward compatible with ST9030, ST9032 and ST9036 January 1993 | | (Ordering Information at the end of the Datasheet) ‘This is short overview of an ST9 Family Member. Please contact SGS- THOMSON for futher information. 37ST9040 GENERAL DESCRIPTION The ST9040 is a ROM member of the ST9 family of microcontrollers, completely developed and pro- duced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. The ROM device is fully compatible with its EPROM version, which may be used for the prototyping and pre-production phases of development, and can be configured as: a standalone microcontroller with 16K bytes of on-chip ROM, a microcontroller able to man- age external memory, or as a parallel processing element in a system with other processors and pe- ripheral controllers. The nucleus of the ST9040 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescalgr, a Serial Peripheral Interface supporting S-bus, I°C-bus and IM-bus Interface, plus two 8 bit VO ports. The Core has independent memory and register buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. The powerful /O capa- bilities demanded by microcontroller applications are fulfilled by the ST9040 with up to 56 I/O lines dedicated to digital Input/Output. These lines are grouped into up to seven 8 bit I/O Ports and can be configured on a bit basis under software control to Figure 1. ST9040 Block Diagram provide timing, status signals, an address/data bus for interfacing external memory, timer inputs and outputs, analog inputs, external interrupts and serial or parallel I/O with or without handshake. Three basic memory spaces are available to support this wide range of configurations: Program Memory {intemal and external), Data Memory (intemal and ex- temal) andthe Register File, whichincludes the control and status registers of the on-chip peripherals. Two 16 bit MultiFunction Timers, each with an 8 bit Proscaler and 13 operating modes allow simplo usc for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. In addition there is an 8 channel Analog to Digital Converter with ‘integral sample and hold, fast 171s conversion time and 8 bit resolution. An Analog Watchdog feature is included for two input channels. Completing the device is a full duplex Serial Commu- nications Interface with an integral 110 to 375,000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programmable format) and associated address/wake-up option, plus two DMA channels. TT g war” | [seem] [Porm] fasten FR Seg nd [win p72" | [ i —— ] ee ei) (eet ce eee eee tee te) sors] ns] [ess"] [cas ne] [Ser JH] cen | [ec Hou 8 g Ir 8 38Sr SGS-THOMSON e MICROELECTRONICS ST90E40 ST90T40 16K EPROM HCMOS MCU WITH EEPROM, RAM AND A/D CONVERTER «= Register oriented 8/16 bit CORE with RUN, WFI and HALT modes = Minimum instruction cycle time: 500ns (12MHz internal) = 16K bytes of EPROM or OTP ROM, 256 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = 512 bytes of EEPROM = 80-pin Plastic Quad Flat Pack package for ST90T40Q = 80-pin Window Ceramic Quad Flat Pack pack- age for ST9OE40G = 68-lead Plastic Leaded Chip Carrier package for ST90T40C = 68-lead Window Ceramic Leaded Chip Carrier package for STSOE40L = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features = Up to 56 fully programmable 1/0 pins = Up to 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Two 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes = 8 channel 8 bit Analog to Digital Converter, with Analog Watchdogs and external references = Serial Communications Interface with asynchro- nous and synchronous capability # Rich Instruction Set and 14 Addressing modes = Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators «= Real Time Operating System = Compatible with ST9040 16K ROM device January 1993 PQFP8O PLoces cLocesw (Ordering Information at the end of the Datasheet) This is short overview of an ST9 Family Member. Please contact SGS-THOMSON for further information. 39ST90E40 - ST90T40 GENERAL DESCRIPTION The ST90E40 and ST9OTAO (following mentioned as ST90E40) are EPROM and OTP members of the STS family of microcontrollers, in windowed ceramic (E) and plastic OTP (T) packages respectively, com- pletely developed and produced by SGS-THOM- SON Microelectronics using a n-well proprietary HCMOS process. The EPROM ST90E40 may be used for the prototyp- ing and pre-production phases of development, and can be configured as: a standalone microcontroller with 16K bytes of on-chip ROM, a microcontroller able to manage of external memory, or as a par. processing element in a system with other proces- sors and peripheral controllers. The nucleus of the ST90E40 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescalgr, a Serial Peripheral Interface supporting S-bus, I°C-bus and IM-bus Interface, plus two 8 bit VO ports. The Core has independent memory and register buses allowing ahigh degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. The powertul /O capabilities demanded by micro- controller applications are fulfilled by the ST90E40 with up to 56 /O lines dedicated to digital Input/Out- put. These lines are grouped into upto seven 8bit /O Figure 1. ST90E40 Block Diagram Ports and can be configured on abit basis under soft- ware control to provide timing, status signals, an ad- dressidata bus for interfacing external memory, timer inputs and outputs, analog inputs, external in- terrupts and serial or parallel /O with or without handshake. ‘Three basic memory spaces are available to support this wide range of configurations: Program Memory (internal and external), Data Memory (internal and ex- ternal) and the Register File, which includes the control and status registers of the on-chip peripherals. Two 16 bit Mi ‘unction Timers, each with an 8 bit Prescaler and 13 operating modes allow simple use for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. In addition there is an 8 channel Analog to Digital Converter with integral sample and hold, fast 1111s conversion time and 8 bit resolution. An Analog Watchdog feature is included fortwo input channels. Completing the device is afull duplex Serial Commu- nications Interface with an integral 110 to 375,000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programmable format) and associated addressiwake-up option, plus two DMA channels. g EEPROM 6h Bytos EPROM 256 Bytes REGISTER FILE CPU sci |, wiTH OMA [ J IJ q Ti Ir I vo eort 2] [vo roar a}_ 2x veo TMER | wr bua | Ses 7 & Br SS THOMSON 40ii SGS-THOMSON MICROELECTROMICS ST90R40 ROMLESS HCMOS MCU WITH EEPROM, RAM AND A/D CONVERTER = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes = Minimum instruction cycle time: 500ns (12MHz internal) = 256 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) « Romless to allow maximum external memory capbility = 512 bytes EEPROM = 68-lead Plastic Leaded Chip Carrier package = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features # 40 fully programmable I/O pins = Upto 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Two 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes = 8 channel 8 bit Analog to Digital Converter, with Analog Watchdogs and external references = Serial Communications Interface with asynchro- nous and synchronous capability = Rich Instruction Set and 14 Addressing modes = Division-by-Zero trap generation «= Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators = Real Time Operating System = Compatible with ST9040 16K ROM device (also available in windowed and One Time Programma- ble EPROM packages) January 1993 PLeces (Ordering Information at the end of the Datasheet) This is short overview of an ST9 Family Member. Please contact SGS-THOMSON for further information. aST90R40 GENERAL DESCRIPTION The ST9OR40 is a ROMLESS member of the ST9 family of microcontrollers, completely developed and produced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. ‘The ROMLESS part may be used for the prototyping and pre-production phases of development, and of- fers the maximum in program flexibility in production systems. The ROMLESS ST90R40 canbe configuredas.ami- crocontroller able to manage external memory, or as a parallel processing element in a system with other processors and peripheral controllers. The nucleus of the ST90R40 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescaley, a Serial Peripheral Interface supporting S-BUS, I°C-bus and IM-bus Interface, plus memory interface. The Core has independent memory and fegister buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. The powerful /O capabilities demanded by micro- controller applications are fulfilled by the ST90R40 with up to 40 I/O lines dedicated to digital Input/Out- put. These lines are grouped into up to five 8 bit /O Figure 1. ST90R40 Block Diagram Portsand can be configured on abitbasis under soft- ware control to provide timing and status signals, timer inputs and outputs, analog inputs, external in: terrupts and serial or parallel /O with or without handshake. Three memory spaces are available: Program Mem- ory (external), Data Memory (external) and the Reg- ister File, which includes the control and status registers of the on-chip peripherals. ‘Two 16 bit MultiFunction Timers, each with an 8 bit Prescaler and 13 operating modes allow simple use for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. In addition there is an 8 channel Analog to Digital Converter with integral sample and hold, fast 1141s conversion time and 8bit resolution. An Analog Watchdog feature is included for two input channels. Completing the device is afull duplex Serial Commu- nications Interface with an integral 110 to 375,000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programmable format) and associated address/wake-up option, plus two DMA channels. 512 Bytes EEPROM 258 aytes RAM 258 Bytes REGISTER FILE 16H TIMER | WATCHOOG + SP] al with OMA CPU > tt —_ ial q coe REGISTER BUS _] I | {t I ff fT secant [sa] se ear H] sar fem cowerren | | wnt nanomrane oye gy g ii g SSE 42ky SGS-THOMSON ‘TF, wvicRosuscrromes ST90R50 ROMLESS HCMOS MCU WITH BANKSWITCH AND A/D CONVERTER = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes = Minimum instruction cycle time: 500ns (12MHz internal) = 224 general purpose registers available as RAM, accumulators or index registers (Register File) = Romless to allow maximum external memory flexibility in development and production phases = Bankswitch logic allowing a maximum address- ing capability of 8Mbytes for Program and Dataspace (16Mbytes total) = 84-pin Plastic Leaded Chip Carrier package (Ordering Information at the end of the Datasheet) = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features = 56 fully programmable 1/O pins = Up to 8 external plus 1 non-maskable interrupts «= 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer «= Three 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes = 8 channel 8 bit Analog to Digital Converter, with Analog Watchdogs and external references = Two Serial Communications Interface with asyn- chronous and synchronous capability = Rich Instruction Set and 14 Addressing modes = Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators = Real Time Operating System = Compatible with ST9054, 32K ROM device (also available in windowed and one time programma- ble EPROM packages) January 1993 ‘Ths is short overview of an ST Family Member. Please contact SGS-THOMSON for futher information.ST90R50 GENERAL DESCRIPTION The ST90R50 is a ROMLESS member of the STS family of microcontrollers, completely developed and produced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. ‘The ROMLESS part may be used for the prototyping and pre-production phases of development, and of- fers the maximum in program flexibility in production systems with its 16M byte addressing space when using the Bankswitch memory expansion. The nucleus of the STIORS0 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescaigr, a Serial Peripheral Interface supporting S-bus, I°C-bus and IM-bus Interface, plus memory interface. The Core has independent memory and register buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. The powerful 1/O capabilities demanded by micro- controller applications are fulfilled by the ST9OR50 with up to 56 1/O lines dedicated to digital Input/Out- put. These lines are grouped into up to nine 8 bit YO Figure 1. ST9OR50 Block Diagram Ports and can be configured on abit basis under soft- ware control to provide timing, status signals, timer inputs and outputs, external interrupts and serial or parallel I/O with or without handshake. Three basic memory spaces are available to support this wide range of configurations: Program Memory (external), Data Memory (external) and the Register, File, which includes the control and status registers of the on-chip peripherals. ‘Three 16 bit MultiFunction Timers, each with an 8 bit Prescaler and 13 operating modes allow simple use for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. ‘Completing the device are two full duplex Serial Com- munications Interfaces, each with an integral 110 to 375000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programm. able format) and associated address/wake-up option, plus two DMA channels. i 8 § ease a eat, Ha ate of eee (scx) Peet ttt i u boo BS yy sceomson 44&r SGS-THOMSON MICROELECTRONICS ST90R51 ROMLESS HCMOS MCU WITH BANKSWITCH = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes = Minimum instruction cycle time: 500ns (12MHz internal) «= 224 general purpose registers available as RAM, accumulators or index registers (Register File) = Romless to allow maximum external memory ca- pability = Bankswitch logic allowing a maximum address- ing capability of 8Mbytes for Program and Dataspace (16Mbytes total) = 80-pin Plastic Quad Flat Pack package = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features = 54 fully programmable I/O pins = Up to8 external plus 1 non-maskablé interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Three 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes 1 Two Serial Communications Interface with asyn- chronous and synchronous capability # Rich Instruction Set and 14 Addressing modes = Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators = Real Time Operating System January 1993 PRELIMINARY DATA (Ordering Information at the end of the Datasheet) ‘This is short overview of an ST9 Family Member. Please contact SGS-THOMSON for further information. 45ST90R51 GENERAL DESCRIPTION The ST90R51 is a Romless member of the ST9fam- ily of microcontrollers, completely developed and produced by SGS-THOMSON Microelectronics us- ing a proprietary n-well HCMOS process. The Romless part may be used for the prototyping and pre-production phases of development, and of- fers the maximum in program flexibility The nucleus of the ST90R51 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescalgr, a Serial Peripheral Interface supporting S-bus, I°C-bus and IM-bus interface, plus memory interface. The Core has independent memory and register buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. The powerful /O capa- bilities demanded by microcontroller applications, are fulfilled by the ST9ORS51 with up to 54 V/O lines dedicated to digital Input/Output. These lines are grouped into up to seven 8 bit /O Ports and can be configured on a bit basis under software control to, provide timing, status signals, timer inputs and out- puts, analog inputs, external interrupts and serial or parallel I/O with or without handshake. Three basic memory spaces are available to support Figure 1. ST90R51 Block Diagram this wide range of configurations: Program Memory , Data Memory and the internal Register File, which includes the control and status registers of the on- chip peripherals. ‘Three 16 bit MultiFunction Timers, each with an 8 bit Prescaler and 13 operating modes allow simple use for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. in addition there is an 8 channel Analog to Digital Converter with integral sample and hold, fast 11j1s conversion time and 8 bit resolution. An Analog Watchdog feature is included for two input channels, Completing the device are 2 full duplex Serial Com- munications Interfaces with an integral 110 to 375,000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programm- able format) and associated address/wake-up op- tion, plus two DMA channels. gO g Te-Bh TIMER / WATGHDOG + SP 256 Bytes 2x0 wo rorts | | vo poar a vo PORT 5 with oa REGISTER FILE CPU (sie) | | (tiene) (TIMER | | Jt 3. co | l —— 3 «160i TIMER I J WITH OMA I 1 PoRT 6 | AddreserData paorss aB.Ars)] | Ades A087 ) (ane SwrcH [Ll ir | [ u u u VRoAtsHe Sr SGS-THOMSON RUERoLLaETmaMNeSsky SGS-THOMSO ‘f. Secon conan ST9054 32K ROM HCMOS MCU WITH BANKSWITCH = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes = Minimum instruction cycle time: 500ns (12MHz internal) = 32K bytes of ROM, 1280 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = Bankswitch logic allowing a maximum address- ing capability of 8Mbytes for Program and Dataspace (16Mbytes total) = 84-pin Plastic Leaded Chip Carrier package = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features = Upto 72 fully programmable 1/0 pins = Upto 6 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Three 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes = 8 channel 8 bit Analog to Digital Converter, with Analog Watchdogs and external references = Two Serial Communications Interface with asyn- chronous and synchronous capability = Rich Instruction Set and 14 Addressing modes = Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators «= Real Time Operating System = Windowed and One Time Programmable EPROM parts available for prototyping and pre-produc- fion development phases January 1993, AND A/D CONVERTER PRELIMINARY DATA (Ordering information at the end of the Datasheet) ‘This is short overview of an ST9 Family Member. Please contact SGS-THOMSON for further information, 47ST9054 GENERAL DESCRIPTION The ST9054 is a ROM member of the ST9 family of microcontrollers, completely developed and pro- duced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. The ROM part is fully compatible with its EPROM versions, which may be used for the prototyping and pre-production phases of development, and can be configured as: standalone microcontrollers with 32K bytes of on-chip ROM, microcontrollers able toman- age external memory (16M byte with the Bankswitch logic). oras parallel processing elementsin asystem with other processors and peripheral controllers. The nucleus of the ST9054 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescaler, a Serial Peripheral Interface supporting S-bus, I°C-bus and IM-bus Interface, plus two 8 bit VO ports. The Core has independent memory and register buses allowing ahigh degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. The powerful /O capabilities demanded by micro- controller applications are fulfilled by the ST9054 with up to 72 V/O lines dedicated to digital InpuOut- put. These lines are grouped into up to nine 8 bit /O Ports and canbe configured on abit basis under soft- ware control to provide timing, status signals, ad- Figure 1. ST9054 Block Diagram dress and data buses for interfacing external mem- ory, timer inputs and outputs, analog inputs, external interrupts and serial or parallel /O with or without handshake. Three basic memory spaces are available to support this wide range of configurations: Program Memory (internal and external), Data Memory (internal and external) and the Register File, which includes the control and status registers of the on-chip peripher- als. Three 16 bit MultiFunction Timers, cach with an 8 bit Prescaler and 13 operating modes allow simple use for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. in addition there is an 8 channel Analog to Digital Converter with integral sample and hold, fast 11s conversion time and 8 bit resolution. An Analog Watchdog feature is included for two input channels. Completing the device are two full duplex Serial Com- munications Interfaces, each with an integral 110 to 375000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programm- able format) and associated address/wake-up option, plus two DMA channels. g g i {EGISTER FILE : 1280 Byos aM 1694 TIMER wT Ow 1 | [ | , St I f Stn] [ra] ater | sen] [etn fete] [ents MLS] bo oY gg gg & i 48 G57 S6S:THOMSONGr SGS-THOMSON If, MICROELECTRONICS ST90E54 32K EPROM HCMOS MCU WITH BANKSWITCH AND A/D CONVERTER PRELIMINARY DATA # Register oriented 8/16 bit CORE with RUN, WFI and HALT modes = Minimum instruction cycle time: 500ns (12MHz internal) = 32K bytes of EPROM 4280 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = Bankswitch logic allowing a maximum address- ing capability of 8Mbytes for Program and Dataspace (16Mbytes total) cLecaaw = 84-pin Window Ceramic Leaded Chip Carrier package (Ordering Information at the end of the Datasheet) = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features = Up to 72 fully programmable /O pins = Up to 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Three 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes # 8 channel 8 bit Analog to Digital Converter, with Analog Watchdogs and external references = Two Serial Communications Interface with asyn- chronous and synchronous capability = Rich Instruction Set and 14 Addressing modes = Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de bugger and hardware emulators = Real Time Operating System = Compatible with ST9054 32K ROM device January 1993, ‘This is short overview of an ST9 Family Member. Please contact SGS-THOMSON for further information 49ST90E54 GENERAL DESCRIPTION The ST90ES4is an EPROM memberofthe ST9tamily of microcontrollers, in windowed ceramic package , completely developed and produced by SGS-THOM- SON Microelectronics using a proprietary n-well HCMOS process. ‘The EPROM ST90E54 may be used for the prototyp- ing and pre-production phases of development, and can be configured as: standalone microcontrollers with 32K bytes of on-chip EPROM, microcontrollers able to manage external memory (16M byte with the Bankswitch logic), or as parallel processing elements ina system with other processors and peripheral con- trollers. The nucleus of the ST9OES4 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Pres- ler, a Serial Peripheral interface supporting S-bus, F°C-bus and IM-bus Interface, plus two 8 bit /O ports. The Core has independent memory and register buses allowing a high degree of pipelining to add tothe efficiency of the code execution speedof the extensive instruction set. The powerful /O capabilities demanded by micro- controller applications are futilled by the ST90E54 with up to 72 1/0 lines dedicated to digital Input/Out- put. These lines are grouped into upto nine & bit /O Ports and canbe configured on abitbasis under soft- Figure 1. ST90E54 Block Diagram ware control to provide timing, status signals, ad- dress and data buses for interfacing external mem- ory, timerinputs and outputs, analog inputs, external interrupts and serial or parallel VO with handshake. ‘Three basic memory spaces are available to support this wide range of configurations: Program Memory (internal and external), Data Memory (internal and external) and the Register File, which includes the Control and status registers ofthe on-chip perpher- als, Three 16 bit MultiFunction Timers, each with an 8 bit Prescaler and 13 operating modes allow simple use for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA channels for each timer. In addition there is an 8 channel Analog to Digital Con- verter with integral sample and hold, fast 111s conver- sion time and 8 bit resolution. An Analog Watchdog feature is included for two input channels. Completing the device are two full duplex Serial Com- munications Interfaces, each with an integral 110 to 375000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programm- able format) and associated address/wake-up option, plus two DMA channels. g 2a6 Byes | [ 12BH TER WATCHDOG + SP REGISTER FILE 1200 Byles aM 52K B08 EPROM gf woports | | ¥ POAT 8 Lal iene raeen feof UO PORTS CPU U EY Bu TL. tJ _L I | Cv ff it of v0 PORT 0 | Aaeoss/Data 2x Sci work oa : ros ieee eee u aS GL SnotOr SGS-THOMSON Jf MICROELECTRONICS ST90R54 ROMLESS HCMOS MCU WITH BANKSWITCH AND A/D CONVERTER PRELIMINARY DATA, = Register oriented 8/16 bit CORE with RUN, WFi and HALT modes + Minimum instruction cycle time: 500ns (12MHz internal) # 1280 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = Romless to allow maximum external memory flexibility in development and production phases = Bankswitch logic allowing a maximum address- ing capability of 8Mbytes for Program and Dataspace (16Mbytes total) (Ordering Information at the end of the Datasheet) = 84-pin Plastic Leaded Chip Carrier package = DMA controller, Interrupt handler and Serial Pe- ripheral Interface as standard features = 56 fully programmable /O pins = Upto 8 external plus 1 non-maskable interrupts = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = Three 16 bit Multifunction Timers, each with an 8 bit prescaler and 13 operating modes = 8 channel 8 bit Analog to Digital Converter, with Analog Watchdogs and external references = Two Serial Communications Interface with asyn- chronous and synchronous capability = Rich Instruction Set and 14 Addressing modes = Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de bugger and hardware emulators = Real Time Operating System = Compatible with ST9054, 32K ROM device (also available in windowed EPROM packages) January 1993 This ig short overview of an ST9 Family Member. Please contact SGS- THOMSON for further information 51ST90R54 GENERAL DESCRIPTION ‘The ST9ORS4 is a ROMLESS member of the STS family of microcontrollers, completely developed and produced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. ‘The ROMLESS part may be used for the prototyping and pre-production phases of development, and of- fers the maximum in program flexibility in production systems with its 16M byte addressing space when using the Bankswitch memory expansion. The nucleus of the ST9ORS4 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16 bit Timer/Watchdog with 8 bit Prescaigr, a Serial Peripheral Interface supporting S-bus, ?C-bus and IM-bus Interface, plus memory interface. The Core has independent memory and register buses allowing ahigh degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. The powerful /O capabilities demanded by micro- controller applications are fulfilled by the ST9OR54 with up to 56 1/0 lines dedicated to digital Inpul/Out- put. These lines are grouped into upto seven 8bit /O Ports and canbe configured on abitbasis under soft- ware control to provide timing, status signals, timer Figure 1. ST90R54 Block Diagram inputs and outputs, analog inputs, external interrupts and serial or parallel /O with or without handshake. Three basic memory space: this wide range of configurations: Program Memory (external), Data Memory (external) and the Register, File, which includes the control and status registers of the on-chip peripherals. ‘Three 16 bit MultiFunction Timers, each with an 8 bit Prescaler and 13 operating modes allow simple use for complex waveform generation and measure- ment, PWM functions and many other system timing functions by the usage of the two associated DMA, channels for each timer. In addition there is an 8 channel Analog to Digital Converter with integral sample and hold, fast 114s conversion time and 8 bit resolution. An Analog Watchdog feature is included for two input channels. Completing the device are two full duplex Serial Com- munications Interfaces, each with an integral 110 to 375000 baud rate generator, asynchronous and 1.5Mbyte/s synchronous capability (fully programm- able format) and associated address/wake-up option, plus two DMA channels. h t 16-88 MER) WATCHDOG + SPI | CPU 256 Bytes aM 120 ats | Tr fol so.0e TIMER (| WITH OMA (TIMER ) vo PORT 4 U REGISTER FILE ~HienoRY aus ee Tl al wv ==] il 1 1 I J I! I vo PORT © | ncsents | [te ror (ean sure wir oma | Accessioata (Assess 40.37 u gg i ie 52OT. SGS-THOMSON MICROELECTRONICS ST9292 24K ROM HCMOS MCU WITH ON SCREEN DISPLAY AND CLOSED CAPTION DATA SLICER «= Register oriented 8/16 bit CORE with RUN, WFI and HALT modes ‘= Minimum instruction cycle time: 500ns (12MHz internal) 1 24K bytes of ROM, 384 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) «= 42-lead Shrink DIP package = Interrupt handler and Serial Peripheral Interface as standard features = 31 fully programmable V/O pins = 34 character x15 rows software programmable On Screen Display module with colour, italic, un- derline, flash, transparent and fringe attribute options «= Digital Data Slicer extracting closed caption data from video = 8 8-bit PWM D/A outputs with repetition fre- quency 2 to 32kHz and 12V Open Drain Capability = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = 16-bit programmable Slice Timer with 8-bit pres- caler = 3 channel Analog to Digital Converter, with inte- gral sample and hold, fast 5.75us conversion time, 6-bit guaranteed resolution = Rich Instruction Set and 14 Addressing modes = Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators = Real Time Operating System = Windowed EPROM parts available for prototyp- ing and pre-production development phases January 1993 PRELIMINARY DATA (Ordering Information at the end of the Datasheet) DEVICE SUMMARY Device RAM ROM ST9292J4 384 bytes 16Kbytes ST9292J5 384 bytes 2aKbytes. This is short overview of an STS Family Member. Please contact SGS-THOMSON for further information, 53ST9292 GENERAL DESCRIPTION The ST9292 is a ROM member of the ST9 family of microcontrollers, completely developed and pro- duced by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. The ROM parts are fully compatible with their EPROM versions, which may be used for the proto- typing and pre-production phases of development, and can be configured as: standalone microcontrol- lers with 24K bytes of on-chip ROM. The nucleus of the ST9292 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16-bit Timer/Watchdog with 8-bit Prescalgr, a Serial Peripheral Interface supporting S-bus, |°C-bus and IM-bus Interface. The Core has independent memory and register buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of the extensive instruc- tion set. The powerful /O capabilities demanded by micro- controller applications are fulfilled by the ST9292 with up to 31 1/0 lines dedicated to digital Input/Out- put. These lines are grouped into up to six /O Ports and can be configured on a bit basis under software control to provide timing, status signals, address and data buses for interfacing external memory, timer in- puts and outputs, analog inputs, external interrupts and serial or parallel I/O. Figure 1. ST9292 Block Diagram Three basic memory spaces are available to support this wide range of configurations: Program Memory, Data Memory and the Registar File, which includes the control and status registers of the on-chip periph- erals. The 16-bit Slice Timer with an 8-bit Prescaler. The human interface is provided by the On Screen Display module, this can produce up to 15 ines of up to 34 characters from a ROM defined 128 character set. The 9x13 character can be modified by 4 differ- ent pixel sizes, with character rounding, and formed into words with colour and format attributes. Closed Caption control for the display of information transmitted through the video input is facilitated with the Data Slicer. This module has manual and auto- matic Slicing levels for both Syne and Data and al- lows the user to select the video line containing the data relative to the Vertical synchronisation pulse. Control of TV settings is able to be made with up to eight 8-bit PWM outputs, with a frequency maximum of 23,437Hz at 8-bit resolution (INTCLK = 12MHz).. Low resolutions with higher frequency operation can be programmed. In addition there is a3 channel Analog to Digital Con- verter with integral sample and hold, fast 5.75ys con- version time and 6-bit guaranteed precision. 24k Bytes 384 Byes 256 aytes ROM al REGISTER FILE DATA auce_ | sucen TIMER CPU | C video | 7 | f i of REGISTER BUS | Addams & Dale] 1 iE ll woromt2 Lf 2/0 |[ooroms ak fonsoneen] [OrORT#] [Rm ) (io ponrs «Anes es ff converren orseeny || eM I cottren| [vem | veyne seve] vROA1749 G57 S8S:THOMSON 54 MIE{57 SGS-THOMSON ST92E92 ‘Jf, wicRosuecraomics ST92T92 24K EPROM HCMOS MCU WITH ON SCREEN DISPLAY AND CLOSED-CAPTION DATA SLICER PRELIMINARY DATA «= Register oriented 8/16 bit CORE with RUN, WFI and HALT modes « Minimum instruction cycle time: 500ns (12MHz internal) = 24K bytes of EPROM or OTP ROM, 384 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = 42-lead Plastic Shrink DIP package for ST92T92 = 42-Jead Window Ceramic Shrink DIP package for ST92E92 = Interrupt handler and Serial Peripheral Interface as standard features = 31 fully programmable /O pins PsDIP42 = 34 character x15 rows software programmable On Screen Display module with colour, italic, un- derline, Flash, transparent and fringe attribute options = Digital Data Slicer extracting closed caption data from video = 8 8-bit PWM DVA outputs with repetition fre- quency 2 to 32kHz and 12V Open Drain Capability = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer «= 16-bit programmable Slice Timer with 8-bit pres- caler cspipa2w » 3 channel Analog to Digital Converter, with inte- gral sample and hold, fast 5.75s conversion (Ordering Information at the end of the Datasheet) time, 6-bit guaranteed resolution = Rich Instruction Set and 14 Addressing modes = Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators = Real Time Operating System = Compatible with ST9292 24K ROM device January 1993 This is short overview of an ST9 Family Member. Please contact SGS-THOMSON for further information. 55ST92E92 - ST92T92 GENERAL DESCRIPTION ‘The ST92E92 and ST92T92 are EPROM member of the ST9 family of microcontrollers in windowed Ce- ramic (E) and Plastic OTP (T) packages respec- tively, completely developed and produced by SGS-THOMSON Microelectronics using a proprie- tary n-well HCMOS process. ‘The EPROM parts are fully compatible with their ROM versions, which may be used for the prototyp- ing and pre-production phases of development, and can be configured as: standalone microcontrollers with 24K bytes of on-chip EPROM, microcontrollers able to manage up to 64K bytes of external memory The nucleus of the ST92E92 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16-bit Timer/Watchdog with 8-bit Prescaigr, a Serial Peripheral Interface supporting S-bus, |°C-bus and IM-bus Interface, plus two 8-bit VO ports. The Core has independent memory and register buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of the extensive instruction set. The powerful VO capabilities demanded by micro- controller applications are fulfilled by the ST92E92, with up to 31 1/0 lines dedicated to digital InpuOut- put. These lines are grouped into up to five /O Ports and can be configured on a bit basis under software control to provide timing, status signals, timer inputs and outputs, analog inputs, external interrupts and serial or parallel /O. Figure 1. ST92E92 Block Diagram Three basic memory spaces are available to support, this wide range of configurations: Program Memory, Data Memory and the Register File, which includes the control and status registers of the on-chip periph- erals. The 16-bit Slice Timer with an 8-bit Prescaler. The human interface is provided by the On Screen Display module, this can produce up to 15 lines of up to 34 characters from a ROM defined 128 character ‘set. The 9x13 character can be modified by 4 differ- ent pixel sizes, with character rounding, and formed into words with colour and format atiributes. Closed Caption control for the display of information transmitted through the video inputs facilitated with the Data Slicer. This module has manual and auto- matic Slicing levels for both Sync and Data and al- lows the user to select the video line containing the data relative to the Vertical synchronisation pulse. Control of TV settings is able to be made with up to eight 8-bit PWM outputs, with a frequency maximum, of 23,437Hz at 8-bit resolution (INTCLK = 12MHz). Low resolutions with higher frequency operation can be programmed, Inadgition there isa3 channel Analog to Digital Con- verter with integral sample and hold, fast 5.75us con- version time and 6-bit guaranteed resolution. 24k Bytes 384 Bytes 256 Bytes rea riven warcwoos + 5°!) [ice ATA EMORY BUS (Address & Data) | | i C AECISTER BUS (Aaa Bala) | TE o WO PORT 4) PWM. I i i Bo [tg Y tl vsync Hsync} AY Br ss 56Ay7, SSouscrmcnes ST9293 32K ROM HCMOS MCUs WITH ON SCREEN DISPLAY AND A/D CONVERTER = Register oriented 8/16 bit CORE with RUN, WF! and HALT modes = Minimum instruction cycle time: 500ns (12MHz internal) = 32K bytes of ROM, 640 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = 42-lead Shrink DIP package « Interrupt handler and Serial Peripheral interface as standard features = 31 fully programmable I/O pins = 34 character x15 rows software programmable On Screen Display module with colour, italic, un- derline, Flash, transparent and fringe attribute options = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = 16-bit programmable Slice Timer with 8-bit pres- caler = 4 channel Analog to Digital Converter, with inte- gral sample and hold, fast 5.5us conversion time, 6-bit guaranteed resolution = Rich Instruction Set and 14 Addressing modes » Division-by-Zero trap generation = Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators = Real Time Operating System = Windowed EPROM parts available for prototyp- ing and pre-production development phases danuary 1993 PRELIMINARY DATA PspIPa2 (Ordering Information at the end of the Datasheet) DEVICE SUMMARY Device RAM ROM ‘sT9293J4 640 bytes 16Kbytes ‘ST9293/5 640 bytes 24Kbytes ‘sT9293/6 640 bytes 32Kbytes ‘This s short overview of an ST@ Family Member. Please contact SGS-THOMSON for further information. 57ST9293 GENERAL DESCRIPTION ‘The ST9293 is a ROM member of the ST9 family of microcontrollers, completely developed and pro- duced by SGS-THOMSON Microelectronics using a proprictary n- well HCMOS process. The ROM parts are fully compatible with their EPROM versions, which may be used for the proto- typing and pre-production phases of development, and can be configured as: standalone microcontrol- lers with 32K bytes of on-chip ROM. The nucleus of the ST9293 is the advanced Core which includes the Central Processing Unit (CPU), the Register File, a 16-bit Timer/Watchdog with 8-bit Prescalgr, a Serial Peripheral Interface supporting ‘S-bus, I°C-bus and IM-bus Interface, plus two 8-bit VO ports. The Core has independent memory and register buses allowing a high degree of pipelining to add to the efficiency of the code execution speed of, the extensive instruction set. The powerful /O capa- bilities demanded by microcontroller applications are fulfilled by the ST9293 with up to 31 VO lines dedicated to digital Input/Output. These lines are grouped into up to five I/O Ports and can be configured on a bit basis under software con- Figure 1. ST9293 Block Diagram trol to provide timing, status signals, timer inputs and outputs, analog inputs, external interrupts and serial or parallel /O. Three basic memory spaces are available to support this wide range of configurations: Program Memory, Data Memory and the Register File, which includes the control and status registers of the on-chip periph- erals. The 16-bit Slice Timer with an 8-bit Prescaler and 6 operating modes allows simple use for waveform generation and measurement, PWM functions and many other system timing functions. The human interface is provided by the On Screen Display module, this can produce up to 15 lines of of upto 34 characters from a ROM defined 128 charac- terset. The 9x13 character can be modified by 4 dif- ferent pixel sizes, with character rounding, and formed into words with colour and format attributes. Inaddition theres a4 channel Analog to Digital Con- verter with integral sample and hold, fast 5.5s con- version time and 6-bit guaranteed precision. 26 / 92 KBytes ROM 16-8n TIMER / WATOHDOG » SPI CPU SuicE TIMER if ff ISTER GUS | Asiress & Data) ] I q PLR Pur | Arenas Meet) | [bispiay” [9] "PORTS +l convenrenf lanai nputs | | (Con! Bur) Coober Z —I i au A vRoB1749, 57 SSS:THOMSON . sie 58 STASOCSk Gs- MSO IT. SES "THOMSON ST92E93 ST92T93 32K EPROM HCMOS MCUs WITH ON SCREEN DISPLAY AND A/D CONVERTER = Register oriented 8/16 bit CORE with RUN, WFI and HALT modes # Minimum instruction cycie time: 500ns (12MHz internal) = 32K bytes of EPROM or OTP ROM, 640 bytes of RAM, 224 general purpose registers available as RAM, accumulators or index registers (Register File) = 424ead Plastic Shrink DIP package for ST92T93. = 42-lead Window Ceramic Shrink DIP package for ST92E93 «= Interrupt handler and Serial Peripheral Interface as standard.features = 31 fully programmable V/O pins = 34 character x15 rows software programmable ‘On Screen Display module with colour, italic, un- Gerline, Flash, transparent and fringe attribute options = 16 bit Timer with 8 bit Prescaler, able to be used as a Watchdog Timer = 16-bit programmable Slice Timer with 8-bit pres- caler = 4 channel Analog to Digital Converter, with inte- gral sample and hold, fast 5.5us conversion time, 6-bit guaranteed resolution = Rich Instruction Set and 14 Addressing modes # Division-by-Zero trap generation « Versatile Development tools, including assembler, linker, C-compiler, archiver, graphic oriented de- bugger and hardware emulators » Real Time Operating SystemCompatible with ‘$9293 32K ROM device danuary 1993 PRELIMINARY DATA PspIP42 cspiPa2w (Ordering information at the end of the Datasheet) This is short overview of an ST9 Family Member. Please contact SGS-THOMSON for further information 59