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EC8552-CAO-mcq - Removed - Watermark
EC8552-CAO-mcq - Removed - Watermark
in
PART –A (1*20=20)
Answer: a
Explanation: An hazard causes a delay in the execution process of the processor.
Answer: d
Explanation: The stalls are a type of hazards that affect a pipe-lined system.
Answer: a
Explanation: The processor contends for the usage of the hardware and might enter into a
deadlock state.
4. The situation wherein the data of operands are not available is called ______
a) Data hazard
b) Stock
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c) Deadlock
d) Structural hazard
View Answer
Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the
destination side.
5. The stalling of the processor due to the unavailability of the instructions is called as
___________
a) Control hazard
b) structural hazard
c) Input hazard
d) None of the mentioned
View Answer
Answer: a
Explanation: The control hazard also called as instruction hazard is usually caused by a
cache miss.
6. The time lost due to the branch instruction is often referred to as ____________
a) Latency
b) Delay
c) Branch penalty
d) None of the mentioned
View Answer
Answer: c
Explanation: This time also retards the performance speed of the processor.
7. The pipeline bubbling is a method used to prevent data hazard and structural hazards.
a) True
b) False
View Answer
Answer: a
Explanation: The periods of time when the unit is idle is called a Bubble.
Answer: b
Explanation: In a scoreboard, the data dependencies of every instruction are logged. Instructions
are released only when the scoreboard determines that there are no conflicts with previously
issued and incomplete instructions.
Answer: c
Explanation: By using the cache we can reduce the speed of memory access by a factor of
10.
10. The periods of time when the unit is idle is called as _____
a) Stalls
b) Bubbles
c) Hazards
d) Both Stalls and Bubbles
View Answer
Answer: d
Explanation: The stalls are a type of hazards that affect a pipelined system.
11. The situation wherein the data of operands are not available is called ______
a) Data hazard
b) Stock
c) Deadlock
d) Structural hazard
View Answer
Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the destination
side.
Answer: c
Explanation: By using a single BUS structure we can minimize the amount of hardware
(wire) required and thereby reducing the cost.
13. ______ are used to overcome the difference in data transfer speeds of various devices.
a) Speed enhancing circuitory
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
View Answer
Answer: d
Explanation: By using Buffer registers, the processor sends the data to the I/O device at the
processor speed and the data gets stored in the buffer. After that the data gets sent to or from the
buffer to the devices at the device speed.
Answer: a
Explanation: PCI BUS is used to connect other peripheral devices that require a direct
connection with the processor.
15. The bus used to connect the monitor to the CPU is ______
a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
View Answer
Answer: b
Explanation: SCSI BUS is usually used to connect video devices to the processor.
16. In multiple Bus organisation, the registers are collectively placed and referred as ______
a) Set registers
b) Register file
c) Register Block
d) Map registers
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Answer: b
Explanation: None.
17. The main advantage of multiple bus organisation over a single bus is _____
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
d) None of the mentioned
Answer: a
Explanation: None.
Answer: c
Explanation: None.
19.What characteristics of RAM memory is not suitable for permanent storage.
a)Volatile
b)Non Volatile
c)Too bulky
d)Too slow
a)trap
b)Interrupt
c)system calls
Ans :c
PART-B (15*2=30)
Answer: b
Explanation: As they require a large number of transistors, their cost per bit increases.
2. When consecutive memory locations are accessed only one module is accessed at a time.
a) True
b) False
Answer: a
Explanation: In a modular approach to memory structuring only one module can be accessed at a
time.
3. In memory interleaving, the lower order bits of the address is used to _____________
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
d) None of the mentioned
Answer: b
Explanation: To implement parallelism in data access we use interleaving.
4. The number successful accesses to memory stated as a fraction is called as _____
a) Hit rate
b) Miss rate
c) Success rate
d) Access rate
Answer: a
Explanation: The hit rate is an important factor in performance measurement.
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5. The number failed attempts to access memory, stated in the form of a fraction is called as
_________
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate
Answer: b
Explanation: The miss rate is a key factor in deciding the type of replacement algorithm.
6. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are
incremented by one, when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
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Answer: b
Explanation: Miss usually occurs when the memory block required is not present in the cache.
7. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by
one and others remain same, in the case of ______
a) Hit
b) Miss
c) Delay
d) None of the mentioned
Answer: a
Explanation: If the referenced block is present in the memory it is called as hit.
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8. If hit rates are well below 0.9, then they’re called as speedy computers.
a) True
b) False
Answer: b
Explanation: It has to be above 0.9 for speedy computers.
9. The extra time needed to bring the data into memory in case of a miss is called as __________
a) Delay
b) Propagation time
c) Miss penalty
d) None of the mentioned
Answer: c
Explanation: None.
10. The miss penalty can be reduced by improving the mechanisms for data transfer between the
different levels of hierarchy.
a) True
b) False
Answer: a
Explanation: The extra time needed to bring the data into memory in case of a miss is called as miss
penalty.
Answer: a
Explanation: The position of each block is pre-determined in the direct mapped cache, hence no need
for replacement.
Answer: c
Explanation: The locality of reference is a key factor in many of the replacement algorithms.
Answer: b
Explanation: The above two methods of mapping the decision of which block to be removed rests
with the cache controller.
4. The algorithm which replaces the block which has not been referenced for a while is
called _____
a) LRU
b) ORF
c) Direct
d) Both LRU and ORF
Answer: a
Explanation: LRU stands for Least Recently Used first.
5. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the
others are incremented by one when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
Answer: b
Explanation: Miss usually occurs when the memory block required is not present in the cache.
Answer: a
Explanation: The LRU in case of the sequential blocks as to waste its one cycle just incrementing the
counters.
7. The algorithm which removes the recently used page first is ________
a) LRU
b) MRU
c) OFM
d) None of the mentioned
Answer: b
Explanation: In MRU it is assumed that the page accessed now is less likely to be accessed again.
Answer: a
Explanation: None.
9. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are
incremented by one and others remain same, in the case of ______
a) Hit
b
0
L) Miss
c) Delay
d) None of the mentioned
Answer: a
Explanation: If the referenced block is present in the memory it is called as a hit.
The counter that keeps track of how many times a block is most likely used is _______
a) Count
b) Reference counter
c) Use counter
d) Probable counter
View Answer
Answer: b
Explanation: None.
b) Cost
c) Speed
d) Both Performance and Cost
View Answer
Answer: d
Explanation: The performance and cost of the computer system is a key decider in the commercial
success of the system.
Answer: b
Explanation: An optimal system provides the best performance at low costs.
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Answer: d
Explanation: By using the memory Hierarchy, we can increase the performance of the system.
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6. The memory transfers between two variable speed devices are always done at the speed of the
faster device.
a) True
b) False
View Answer
7. An effective to introduce parallelism in memory access is by _______
a) Memory interleaving
b) TLB
c) Pages
d) Frames
View Answer
Avvnswer: a
Explanation: Interleaving divides the memory into modules.
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8. The performance of the system is greatly influenced by increasing the level 1 cache.
a) True
b) False
View Answer
9. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively.
Suppose A can execute an instruction with an average of 3 steps and B can execute with an
average of 5 steps. For the execution of the same instruction which processor is faster.
a) A
b) B
c) Both take the same time
d) Insufficient information
Answer: a
Explanation: None.
10. If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value
of S is (Where S is a term of the Basic performance equation).
a) 3
b) ~2
c) ~1
d) 6
View Answer
Answer: c
Explanation: Pipelining is a process of fetching an instruction during the execution of other instruction.
Answer: b
Explanation: This difference in the speeds of operation of the system caused it to be
inefficient.
The physical memory is not as large as the address space spanned by the processor.
a) True
b) False
answer: a
Explanation: This is one of the main reasons for the usage of virtual memories.
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Answer: b
Explanation: By using this technique the program execution is accomplished with a usage of less
space.
Answer: d
Explanation: The logical address is the random address generated by the processor.
c) MMU
d) None of the mentioned
Answer: c
Explanation: The MMU stands for Memory Management Unit.
Answer: a
Explanation: The MMU translates the logical address into a physical address by adding an offset.
Answer: d
Explanation: None.