Digital Integrated

Circuits

EE 431
Fall 2015 Week 12
 Multipliers

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EE141 Integrated Circuits2nd
Arithmetic Circuits 2
The Binary Multiplication

1 0 1 0 1 0 Multiplicand
x 1 0 1 1 Multiplier
1 0 1 0 1 0
1 0 1 0 1 0

0 0 0 0 0 0 Partial products

+ 1 0 1 0 1 0

1 1 1 0 0 1 1 1 0 Result

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EE141 Integrated Circuits2nd
Arithmetic Circuits 3
The Array Multiplier
X3 X2 X1 X0 Y0

X3 X2 X1 X0 Y1 Z0

HA FA FA HA

X3 X2 X1 X0 Y2 Z1

FA FA FA HA

X3 X2 X1 X0 Y3 Z2

FA FA FA HA

Z7 Z6 Z5 Z4 Z3

•N partial products of M bit size each

•N×M two bit AND; N-1 M-bit adders
•Layout need not be straggled, but routing will take care of shift

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EE141 Integrated Circuits2nd
Arithmetic Circuits 4
The MxN Array Multiplier
— Critical Path
HA FA FA HA

FA FA FA HA Critical Path 1
Critical Path 2

FA FA FA HA Critical Path 1 & 2

Many critical paths!! Critical timing determination non-trivial

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EE141 Integrated Circuits2nd
Arithmetic Circuits 5
Carry-Save Multiplier
HA HA HA HA

HA FA FA FA

HA FA FA FA

HA FA FA HA

Vector Merging Adder

•Carry passed diagonally downward

•Assumes tsum = tcarry
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EE141 Integrated Circuits2nd
Arithmetic Circuits 6
 Multiplier Floorplan
X3 X2 X1 X0

Y0
Y1 HA Multiplier Cell
C S C S C S C S
Z0

FA Multiplier Cell
Y2
C S C S C S C S
Z1 Vector Merging Cell

Y3
C S C S C S C S X and Y signals are broadcasted
Z2 through the complete array.
( )

C C C C
S S S S •Can make layout rectangular
•Regular shape and layout
Z7 Z6 Z5 Z4 Z3 •Amenable to automation

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EE141 Integrated Circuits2nd
Arithmetic Circuits 7
 Wallace-Tree Multiplier
Partial products First stage
6 5 4 3 2 1 0 6 5 4 3 2 1 0 Bit position

(a) (b)

Second stage Final adder

6 5 4 3 2 1 0 6 5 4 3 2 1 0

•Substantial Hardware Savings

FA HA •Higher Speeds
(c) (d) •Propagation delay O(log3/2N)
•Irregular; inefficient for layout

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EE141 Integrated Circuits2nd
Arithmetic Circuits 8
 Wallace-Tree Multiplier

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EE141 Integrated Circuits2nd
Arithmetic Circuits 9
 Wallace-Tree Multiplier
y0 y1
y2

y0 y1 y2 y3 y4 y5
Ci-1
FA

y3 FA FA
Ci Ci Ci-1
Ci-1
FA Ci Ci-1

y4
FA
Ci Ci-1 Ci Ci-1
FA

y5

Ci FA
FA

C S
C S

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EE141 Integrated Circuits2nd
Arithmetic Circuits 10
 Multipliers —Summary
• Optimization Goals Different Vs Binary Adder

• Once Again: Identify Critical Path

• Logarithmic versus Linear (Wallace Tree Mult)

FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION

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EE141 Integrated Circuits2nd
Arithmetic Circuits 11