E5120Q/E5120Q-C,

E5120Q/E5120Q-C, E5125/E5125-C,
E5125/E5125-C, E5128Q, E5128Q-C
 Preface

Notebook Computer

E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C

Service Manual
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 Preface

Notice
The company reserves the right to revise this publication or to change its contents without notice. Information contained
herein is for reference only and does not constitute a commitment on the part of the manufacturer or any subsequent ven-
dor. They assume no responsibility or liability for any errors or inaccuracies that may appear in this pub lication nor are
they in anyway responsible for any loss or damage resulting from the use (or misuse) of this publication.

This publication and any accompanying software may not, in whole or in part, be reproduced, translated, transmitted or
reduced to any machine readable form without prior consent from the vendor, manufacturer or creators of this publica-
tion, except for copies kept by the user for backup purposes.

Brand and product names mentioned in this publication may or may not be copyrights and/or registered trademarks of
their respective companies. They are mentioned for identification purposes only and are not intended as an endorsement
of that product or its manufacturer.
  e
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  a
   f Version 1.0
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  r  November 2010
   P

Trademarks
Intel, Intel Core, Intel Pentium and  Intel Celeron are trademarks of Intel Corporation.
Windows® is a registered trademark of Microsoft Corporation.
Other brand and product names are trademarks and /or registered trademarks of their respective companies.

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 Preface

 Ab out t hi s Manual

This manual is intended for service personnel who have completed sufficient training to undertake the maintenance and
inspection of personal computers.

It is organized to allow you to look up basic information for servicing and/or upgrading components of the  E5120Q/ 
 E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook PC.

The following information is included:

Chapter 1, Introduction, provides general information about the location of system elements and their specifications.
Chapter 2, Disassembly, provides step-by-step instructions for disassembling parts and subsystems and how to u pgrade
elements of the system.

Appendix A, Part Lists P 

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Appendix B, Schematic Diagrams  e
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Appendix C, Updating the FLASH ROM BIOS  c 
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 Preface

IMPORTANT SAFETY INSTRUCTIONS

Follow basic safety precautions, including those listed below, to reduce the risk of fire, electric shock and injury to per-
sons when using any electrical equipment:

1. Do not use this product near water, for example near a bath tub, wash bowl, kitchen sink or laundry tub, in a wet
basement or near a swimming pool.
2. Avoid using a telephone (other than a cordless type) during an electrical storm. There may be a remote risk of elec-
trical shock from lightning.
3. Do not use the telephone to report a gas leak in the vicinity of the leak.
4. Use only the power cord and batteries indicated in this manual. Do not dispose of batteries in a fire. They may
explode. Check with local codes for possible special disposal instructions.
5. This product is intended to be supplied by a Listed Power Unit with an AC Input of 100 - 240V, 50 - 60Hz, DC Output
of 19V, 3.42A or 18.5V, 3.5A ( 65W) minimum AC/DC Adapter.

  e
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This Comput er’s Optic al Device is a Laser Class 1 Produ ct

FCC Statement
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
This device may not cause harmful interference.
This device must accept any interference received, including interference that may cause undesired operation.

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 Preface

Instructions for Care and Operation

The notebook computer is quite rugged, but it can be damaged. To prevent this, follow these suggestions:

1. Don’t drop it, or expose it to shock. If the computer falls, the case and the components could be damaged.

 Do not expose the computer  Do not place it on an unstable  Do not place anything heavy
to any shock or vibration. surface. on the computer.

2. Keep it dry, and don ’t overheat it. Keep the computer and power supply away from any kind of heating element. This
is an electrical appliance. If water or any other liquid gets into it, the computer could be badly damaged.

 Do not expose it to excessive  Do not leave it in a place  Don’t use or store the com-  Do not place the computer on
P 
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heat or direct sunlight. where foreign matter or mois-  puter in a humid environment. any surface which will block  e
ture may affect the system. the vents.
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3. Follow the proper working procedures for the comp uter . Shut the computer down properly and don’t forget to save
your work. Remember to periodically save your data as data may be lost if the battery is depleted.

 Do not turn off the power  Do not turn off any peripheral  Do not disassemble the com- Perform routine maintenance
until you properly shut down devices when the computer is  puter by yourself. on your computer.
all programs. on.

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 Preface

4.  Avo id i nt erf eren ce. Keep the computer away from high capacity transformers, electric motors, and other strong mag-
netic fields. These can hinder proper performance and damage your data.
5. Take care when using peripheral devices.

Use only approved brands of Unplug the power cord before

 peripherals. attaching peripheral devices.

Power Safety
  e
  c The computer has specific power requirements:
  a
   f
  e
  r • Only use a power adapter approved for use with this computer.
   P • Your AC adapter may be designed for international travel but it still requires a steady, uninterrupted power supply. If you are
unsure of your local power specifications, consult your service representative or local power company.
Power Safety • The power adapter may have either a 2-prong or a 3-prong grounded plug. The third prong is an important safety feature; do
Warning not defeat its purpose. If you do not have access to a compatible outlet, have a qualified electrician install one.
Before you undertake • When you want to unplug the power cord, be sure to disconnect it by the plug head, not by its wire.
any upgrade proce- • Make sure the socket and any extension cord(s) you use can support the total current load of all the connected devices.
dures, make sure that • Before cleaning the computer, make sure it is disconnected from any external power supplies.
you have turned off the
power, and discon-
nected all peripherals  Do not plug in the power  Do not use the power cord if  Do not place heavy objects
and cables (including cord if you are wet. it is broken. on the power cord.
telephone lines). It is
advisable to also re-
move your battery in
order to prevent acci-
dentally turning the
machine on.

VI
 Preface

Battery Precaution s
• Only use batteries designed for this computer. The wrong battery type may explode, leak or damage the computer.
• Do not continue to use a battery that has been dropped, or that appears damaged (e.g. bent or twisted) in any way. Even if the
computer continues to work with a damaged battery in place, it may cause circuit damage, which may possibly result in fire.
• Recharge the batteries using the notebook’s system. Incorrect recharging may make the battery explode.
• Do not try to repair a battery pack. Refer any battery pack repair or replacement to your service representative or qualified service
 personnel.
• Keep children away from, and promptly dispose of a damaged battery. Always dispose of batteries carefully. Batteries may explode
or leak if exposed to fire, or improperly handled or discarded.
• Keep the battery away from metal appliances.
• Affix tape to the battery contacts before disposing of the battery.
• Do not touch the battery contacts with your hands or metal objects.

Battery Guidelines
The following can also apply to any backup batteries you may have. P 
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• If you do not use the battery for an extended period, then remove the battery from the computer for storage. f  
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• Before removing the battery for storage charge it to 60% - 70%.  c 
• Check stored batteries at least every 3 months and charge them to 60% - 70%.  e

Battery Disposal
The product that you have purchased contains a rechargeable battery. The battery is recyclable. At the end of its useful life, under var-
ious state and local laws, it may be illegal to dispose of this battery into the municipal waste stream. Check with your local solid waste
officials for details in your area for recycling options or proper disposal.

Caution
Danger of explosion if battery is incorrectly replaced. Replace only with the same or equivalent type recommended by the manufacturer.
Discard used battery according to the manufacturer’s instructions.

Battery Level

Click the battery icon in the taskbar to see the current battery level and charge status. A battery that drops below a level of 10%
will not allow the computer to boot up. Make sure that any battery that drops below 10% is recharged within one week.

VII
 Preface

Related Document s
You may also need to consult the following manual for additional information:

User’s Manual on CD/DVD

This describes the notebook PC’s features and the procedures for operating the computer and its ROM-based setup pro-
gram. It also describes the installation and operation of the utility programs provided with the notebook PC.

System Startup
1. Remove all packing materials.
2. Place the computer on a stable surface.
3. Insert the battery and make sure it is locked in position.
4. Securely attach any peripherals you want to use with the computer
(e.g. keyboard and mouse) to their ports.
  e 5. Attach the AC/DC adapter to the DC-In jack on the left of the
  c
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computer, then plug the AC power cord into an outlet, and connect
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the AC power cord to the AC/DC adapter.
   P 6. Use one hand to raise the lid/LCD to a comfortable viewing angle (do
not exceed 135 degrees); use the other hand (as illustrated in Figure
1) to support the base of the computer (Note: Never  lift the computer
by the lid/LCD).
7. Press the power button to turn the computer “on”.
Shut Down

Note that you should al-

ways shut your com-
puter down by
choosing Shut Down
135 from the Start Menu.

This will help prevent

Figure 1
hard disk or system
Opening the Li d/LCD/Computer with AC/DC Adapter
problems.
Plugged-In

VIII

Contents
Introduction ..............................................1-1
Overview .........................................................................................1-1
Specifications ..................................................................................1-2
External Locator - Top View with LCD Panel Open ...................... 1-4
External Locator - Front & Right Side Views ................................. 1-5
External Locator - Left Side & Rear View ..................................... 1-6
External Locator - Bottom View .....................................................1-7
Mainboard Overview - Top (Key Parts) ......................................... 1-8
Mainboard Overview - Bottom (Key Parts) ................................. ...1-9
Mainboard Overview - Top (Connectors) .....................................1-10
Mainboard Overview - Bottom (Connectors) ............................... 1-11
Disassembly ...............................................2-1
Overview .........................................................................................2-1
Maintenance Tools ..........................................................................2-2
Connections .....................................................................................2-2
Maintenance Precautions .................................................................2-3
Disassembly Steps ...........................................................................2-4
Removing the Battery ......................................................................2-5
Removing the Hard Disk Drive .......................................................2-6
Removing the Optical (CD/DVD) Device ....... ............................... 2-8
Removing the System Memory (RAM) ..........................................2-9
Removing and Installing a Processor ............................................2-11
Removing the 3G Module .............................................................2-14
Removing the Wireless LAN Module ...........................................2-15
Removing the Bluetooth Module ..................................................2-16
Removing the Keyboard ................................................................2-17
Part Lists ..................................................A-1
Part List Illustration Location ........................................................ A-2
Top (E5120Q) ...................................................................... .......... A-3
Preface
Top (E5125) ................................................................................... A-4
Top (E5128Q) ................................................................................ A-5
Bottom ........................................................................................... A-6
DVD Dual Drive ............................................................................ A-7
LCD ............................................................................................ ... A-8
Schematic Diagrams.................................B-1
System Block Diagram ...................................................................B-2
Clock Generator ..............................................................................B-3
CPU 1/7 (DMI, PEG, FDI) ............................................ .................B-4
CPU 2/7 (CLK, MISC, JTAG) ....................................................... B-5
CPU 3/7 (DDR3) ............................................................................ B-6
P 
CPU 4/7 (Power) .............................................................................B-7 r 
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CPU 5/7 (Graphics Power) ............................................. ................B-8 f  
 a
CPU 6/7 (GND) ..............................................................................B-9  c 
CPU 7/7 (RESERVED) ................................................................B-10  e
DDR3 SO-DIMM_0 .....................................................................B-11
DDR3 SO-DIMM_1 .....................................................................B-12
LVDS, Inverter .............................................................................B-13
HDMI, CRT ..................................................................................B-14
IBEXPEAK- M 1/9 .......................................................................B-15
IBEXPEAK - M 2/9 ......................................................................B-16
IBEXPEAK - M 3/9 ......................................................................B-17
IBEXPEAK - M 4/9 ......................................................................B-18
IBEXPEAK - M 5/9 ......................................................................B-19
IBEXPEAK - M 6/9 ......................................................................B-20
IBEXPEAK - M 7/9 ......................................................................B-21
IBEXPEAK - M 8/9 ......................................................................B-22
IBEXPEAK - M 9/9 ......................................................................B-23
 New Card, Mini PCIE ...................................................................B-24
3G, CCD, TPM .............................................................................B-25
IX
 Preface

Card Reader/LAN JMB251C ....................................................... B-26

LAN (JMC251C), SATA HDD, ODD ......................................... B-27
Audio Codec VIA1812 ................................................................. B-28
KBC-ITE IT8502E ....................................................................... B-29
LED, MDC, BT ............................................................................ B-30
USB, Fan, TP, Multi-Conn ........................................................... B-31
5VS, 3VS, 1.5VS .......................................................................... B-32
Power 3.3V/5V ............................................................................. B-33
Power 1.5V/0.75V, 1.8VS ............................................................ B-34
Power 1.1VS_VTT ....................................................................... B-35
Power VGFX_Core ...................................................................... B-36
V-Core .......................................................................................... B-37
AC_IN, Charger ........................................................................... B-38
  e Click Board .................................................................................. B-39
  c Audio Board/USB ........................................................................ B-40
  a
   f
  e Power Switch & LED Board ............................................ ............ B-41
  r External ODD Board .................................................................... B-42
   P
Sequence ....................................................................................... B-43
Updating the FLASH ROM BIOS......... C-1
To update the FLASH ROM BIOS you must: C-1
Download the BIOS ................................... .................................... C-1
Unzip the downloaded files to a bootable CD/DVD/ or USB Flash
drive .................................................................................... ............ C-1
Set the computer to boot from the external drive ........................... C-1
Use the flash tools to update the BIOS .......................................... C-2
Restart the computer (booting from the HDD) .............................. C-2

X
 Introduction

Chapter 1: Intro duct ion

Overview
This manual covers the information you need to service or upgrade the  E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/ 
 E5128Q-C  series notebook computer. Information about operating the computer (e.g. getting started, and the Setup util-
ity) is in the User’s Manual. Information about dri-vers (e.g. VGA & audio) is also found in the User’s Manual. The
manual is shipped with the computer.

Operating systems (e.g. Windows Vista/ Window 7, etc.) have their own manuals as do application softwares (e.g. word
 processing and database programs). If you have questions about those programs, you should consult those manuals.
1 
.I  
The E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C series notebook is designed to be upgradeable. See Dis- n
 t  
r 
 assembly on page 2 - 1 for a detailed description of the upgrade procedures for each specific component. Please take note  o
of the warning and safety information indicated by the “ ” symbol.  d 
 u
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The balance of this chapter reviews the computer’s technical specifications and features.  t  
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n

Overview 1 - 1
 Introduction

Specifications Processor Options BIOS

Intel® Core™ i7 Processor  One 32Mb SPI Flash ROM

i7-640M (2.80GHz), i7-620M (2.66GHz) Phoenix™ BIOS
4MB L3 Cache & 1066MHz FSB
Storage
Intel® Core™ i5 Processor 
Latest Specification Information
i5-540M (2.53GHz), i5-520M (2.4GHz), (Factory Option) One Changeable 12.7mm(h) Super Multi
The specifications listed here are correct at the i5-450M (2.4GHz), i5-430M (2.26GHz) Optical Device Drive
time of sending them to the press. Certain items One Changeable 2.5" 9.5 mm (h) SATA HDD
3MB L3 Cache & 1066MHz FSB
(particularly processor types/speeds) may be
changed, delayed or updated due to the manu- Intel® Core™ i3 Processor   Audi o
facturer's release schedule. Check with your i3-370M (2.4GHz), i3-350M (2.26GHz), i3-330M (2.13GHz)
service center for more details. High Definition Audio Compliant Interface
3MB L3 Cache & 1066MHz FSB
2 * Built-In Speakers
Intel® Pentium® Processor 
Built-In Microphone
  n P6000 (1.86GHz)
  o
   i 3MB L3 Cache & 1066MHz FSB Keyboard
   t
  c Intel® Celeron® Processor 
Full-size “WinKey” keyboard (with numeric keypad)
  u P4500 (1.86GHz)
   d Pointing Device
  o CPU 2MB L3 Cache & 1066MHz FSB
  r
   t The CPU is not a user serviceable part. Ac- Built-in Touchpad
  n
   I
LCD
 . cessing the CPU in any way may violate your
   1 warranty. 15.6" (39.62) HD TFT LCD Security

Memory Security (Kensington® Type) Lock Slot

BIOS Password
Two 204 Pin SO-DIMM Sockets Supporting DDR3 1066/
1333 MHz Memory Interface
Memory Expandable up to 8GB
Three USB 2.0 Ports
Core Logic One HDMI-Out Port
One Headphone-Out Jack
Intel ® HM55 Chipset
One Microphone-In Jack
Video Adapter  One RJ-45 LAN Jack
One DC-in Jack
Intel ® HM55 Integrated Video
One External Monitor Port
Shared Memory Architecture of up to 1748MB
MS DirectX® 10 compatible

1 - 2 Specifications
 Introduction

Card Reader  Environmental Spec

Embedded Multi-In-1 Card Reader  Temperature

MMC (MultiMedia Card) / RS MMC Operating: 5°C - 35°C
SD (Secure Digital) / Mini SD / SDHC/ SDXC Non-Operating: -20°C - 60°C
Compatible Relative Humidity
MS (Memory Stick) / MS Pro / MS Duo Operating: 20% - 80%

Communication Non-Operating: 10% - 90%

Built-In Gigabit Ethernet LAN Dimensions & Weight

(Factory Option) 300K/ 1.3M Pixel USB PC Camera Mod- 374mm (w) * 250mm (d) * 14.3 - 34.1mm (h)
ule
2.3 kg (with 48.84WH Battery and ODD)
(Factory Option) Bluetooth 2.1 + EDR Module
(Factory Option) 3.75G/HSPA Half Mini-Card Module
1 
(Factory Option) Combo WLAN (802.11b/g/n) and Blue- .I  
tooth 3.0 Module n
(Factory Option) Intel® WiFi Link 1000 (802.11b/g/n) Wire-
 t  
r 
less LAN Half Mini-Card Module
 o
 d 
(Factory Option) Third-Party 802.11b/g/n Wireless LAN Half  u
Mini-Card Module  c 
 t  
i  
Power   o
n
6 Cell Smart Lithium-Ion Battery Pack, 48.84WH
(Factory Option) 6 Cell Smart Lithium-Ion Battery Pack,
62.16WH
(Factory Option) 4 Cell Smart Lithium-Ion Battery Pack,
32.56WH

Full Range AC/DC Adapter 

 AC Input: 100 - 240V, 50 - 60Hz
DC Output: 19V, 3.42A or 18.5V, 3.5A (65W)

Energy Star 5.0 Compliant

Specifications 1 - 3
 Introduction

Figure 1
External Loc ator - Top View wit h LCD Panel Open
Top View
1
1. PC Camera
(Optional)
2. LCD
3. Power Button
4. LED Status
Indicators
5. Keyboard 2
6. Built-In
Microphone
  n 7. Touchpad &
  o
   i
   t Buttons
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 . 4 3
   1

1 - 4 External Locator - Top View with LCD Panel Open

 Introduction

External Locato r - Fron t & Right Side Views Figure 2

Front View
1. LED Indicators

FRONT VIEW

1 
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Figure 3  o
Right Side View n

1. Microphone-In
RIGHT SIDE VIEW Jack
2. Headphone-Out
Jack
3. USB 2.0 Port
4. Optical Device
1 2 3 Drive Bay
4 5 5. Emergency Eject
Hole

External Locator - Front & Right Side Views 1 - 5

 Introduction

External Loc ator - Left Side & Rear View

Figure 4
Left Side View
1. DC-In Jack
2. External Monitor /
Port LEFT SIDE VIEW
3. RJ-45 LAN Jack
4. HDMI-Out Port
5. 2 * USB 2.0 Ports
6. Vent
7. Multi-in-1 Card 1 2 3 4 5 5 7
Reader  6
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Figure 5 REAR VIEW

Rear View
1. Security Lock Slot
2. Battery
1 2

1 - 6 External Locator - Left Side & Rear View

 Introduction

External Locator - Bottom View

Figure 6 
Bottom View
1. Battery
2. Component Bay
Cover 
3. Vent
4. Hard Disk Bay
1 Cover 
5. Speakers
6. USIM Card 1 
Cover  .I  
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r 
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2  c 
3  t  
i  
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6 n
3

3 3
4
Overheating
5 5 To prevent your com-
puter from overhea-
ting, make sure no-
thing blocks any vent
while the computer is
in use.

External Locator - Bottom View 1 - 7

 Introduction

Figure 7  Mainboard Overvi ew - Top (Key Parts)

Mainboard Top
Key Parts

1. JMC251C
2. Clock Generator 
3. KBC-ITE IT8502E

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1 - 8 Mainboard Overview - Top (Key Parts)

 Introduction

Mainbo ard Overview - Bottom (Key Parts) Figure 8 

Mainboard Bottom
Key Parts

1. Memory Slots
DDR3 SO-DIMM
2. Mini-Card
Connector (3.5G
Module)
3. Audio Codec
4. USIM Card
5. Mini-Card
Connector (WLAN 1 
.I  
1 Module) n
8  t  
r 
6. Multi-in-1 Card  o
Reader   d 
7. Platform Controller  u
 c 
Hub  t  
i  
 o
8. CPU Socket (CPU n
installed)
7

2 4 6
5

Mainboard Overview - Bott om (Key Parts) 1 - 9

 Introduction

Figure 9 Mainboard Overview - Top (Connector s)

Mainboard Top
Connectors

1. HDMI-Out Port
2. USB Ports
3. Speaker Cable
Connector 
4. Microphone
Cable Connector 
9
5. TouchPad Cable
Connector 
  n 6. Click Board
  o
   i Connector 
   t
  c 7. Audio Board 1
  u Connector 
   d 8
  o 8. Keyboard Cable
  r
   t Connector
  n
   I 2
 . 9. Switch Board
   1 Cable Connector 

4 6
5

1 - 10 Mainboard Overview - Top (Connectors)

 Introduction

Mainboard Overview - Bottom (Connectors) Figure 10

Mainboard Bottom
8 Connectors

1. Battery
10 9 7 Connector 
2. ODD Connector 
1
3. HDD Connector
4. Bluetooth Cable
6 Connector 
5. CPU Fan Cable
Connector 
6. RJ-45 LAN Jack 1 
.I  
7. External Monitor n
 t  
r 
Port  o
8. DC-In Jack  d 
9. CCD Cable  u
 c 
Connector   t  
i  
11  o
10.LCD Cable n
2
Connector 
11. CMOS Battery
Connector 
5
4

Mainboard Overview - Bottom (Connectors) 1 - 11

 Introduction

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1 - 12
 Disassembly

Chapter 2: Disassembl y
Overview
This chapter provides step-by-step instructions for disassembling the  E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/ 
 E5128Q-C series notebook’s parts and subsystems. When it comes to reassembly, reverse the procedures (unless other-
wise indicated).

We suggest you completely review any procedure before you take the computer apart.

2 
Procedures such as upgrading/replacing the RAM, optical device and hard disk are included in the User’s Manual but are .D
repeated here for your convenience. i  
 s 
 a
 s 
To make the disassembly process easier each section may have a box in the page margin. Information contained under  s 
the figure # will give a synopsis of the sequence of procedures involved in the disassembly procedure. A box with a  e
m
lists the relevant parts you will have after the disassembly process is complete. Note: The parts listed will be for the dis-  b 
assembly procedure listed ONLY, and not any previous disassembly step(s) required. Refer to the part list for the previ-
Information l  
 y 
ous disassembly procedure. The amount of screws you should be left with will be listed here also.

A box with a will also provide any possible helpful information. A box with a contains warnings.

An example of these types of boxes are shown in the sidebar.

Warning

Overview 2 - 1
 Disassembly

NOTE: All disassembly procedures assume that the system is turned OFF, and disconnected from any power supply (the
 battery is removed too).

Maintenance Tools
The following tools are recommended when working on the notebook PC:

• M3 Philips-head screwdriver 
• M2.5 Philips-head screwdriver (magnetized)
• M2 Philips-head screwdriver 
• Small flat-head screwdriver 
• Pair of needle-nose pliers
• Anti-static wrist-strap

  y
   l
   b
Connections
  m Connections within the computer are one of four types:
  e
  s
  s Locking collar sockets for ribbon connectors To release these connectors, use a small flat-head screwdriver to
  a
  s
   i gently pry the locking collar away from its base. When replac-
   D
 . ing the connection, make sure the connector is oriented in the
   2 same way. The pin1 side is usually not indicated.

Pressure sockets for multi-wire connectors To release this connector type, grasp it at its head and gently
rock it from side to side as you pull it out. Do not pull on the
wires themselves. When replacing the connection, do not try to
force it. The socket only fits one way.

Pressure sockets for ribbon connectors To release these connectors, use a small pair of needle-nose pli-
ers to gently lift the connector away from its socket. When re-
 placing the c onnection, make sure the connector is oriented in
the same way. The pin1 side is usually not indicated.

Board-to-board or multi-pin sockets To separate the boards, gently rock them from side to side as
you pull them apart. If the connection is very tight, use a small
flat-head screwdriver - use just enough force to sta rt.

2 - 2 Overview
 Disassembly

Maintenance Precautions
The following precautions are a reminder. To avoid personal injury or damage to the computer while performing a re-
moval and/or replacement job, take the following precautions: Power Safety
Warning
1. Don't drop it. Perform your repairs and/or upgrades on a stable surface. If the computer falls, the case and other
Before you undertake
components could be damaged. any upgrade proce-
2. Don't overheat it. Note the proximity of any heating elements. Keep the computer out of direct sunlight. dures, make sure that
3.  Avo id in terf erenc e. Note the proximity of any high capacity transformers, electric motors, and other strong mag- you have turned off the
netic fields. These can hinder proper performance and damage components and/or data. You should also monitor power, and discon-
nected all peripherals
the position of magnetized tools (i.e. screwdrivers).
and cables (including
4. Keep it dry. This is an electrical appliance. If water or any other liquid gets into it, the computer could be badly telephone lines). It is
damaged. advisable to also re-
5. Be careful with power . Avoid accidental shocks, discharges or explosions. 2 
move your battery in .D
•Before removing or servicing any part from the computer, turn the computer off and detach any power supplies. order to prevent acci-
i  
 s 
•When you want to unplug the power cord or any cable/wire, be sure to disconnect it by the plug head. Do not pull on the wire. dentally turning the
 a
6. Peripherals – Turn off and detach any peripherals. machine on.  s 
7. Beware of static disc harge. ICs, such as the CPU and main support chips, are vulnerable to static electricity.  s 
 e
Before handling any part in the computer, discharge any static electricity inside the computer. When handling a m
printed circuit board, do not use gloves or other materials which allow static electricity buildup. We suggest that  b 
l  
 y 
you use an anti-static wrist strap instead.
8. Beware of corrosi on. As you perform your job, avoid touching any connector leads. Even the cleanest hands pro-
duce oils which can attract corrosive elements.
9. Keep your work environ ment clean. Tobacco smoke, dust or other air-born particulate matter is often attracted
to charged surfaces, reducing performance.
10. Keep track of the components . When removing or replacing any part, be careful not to leave small parts, such as
screws, loose inside the computer.

Cleaning
Do not apply cleaner directly to the computer, use a soft clean cloth.
Do not use volatile (petroleum distillates) or abrasive cleaners on any part of the computer.

Overview 2 - 3
 Disassembly

Disassembly Steps
The following table lists the disassembly steps, and on which page to find the related information. PLEASE PERFORM
THE DISASSEMBLY STEPS IN THE ORDER INDICATED.

To remove the Battery: To remove the Bluetooth Module:

1. Remove the battery  page 2 - 5 1. Remove the battery  page 2 - 5
2. Remove the Bluetooth Module  page 2 - 16 
To remove t he HDD:
1. Remove the battery  page 2 - 5 To remove the Keyboard:
2. Remove the HDD  page 2 - 6  1. Remove the battery  page 2 - 5
2. Remove the keyboard   page 2 - 17 
  y
   l
To remove the Optic al Device:
   b 1. Remove the battery  page 2 - 5
  m 2. Remove the Optical device  page 2 - 8
  e
  s
  s To remove the System Memory:
  a
  s
   i 1. Remove the battery  page 2 - 5
   D
 . 2. Remove the system memory  page 2 - 9
   2
To remove and install a Processor:
1. Remove the battery  page 2 - 5
2. Remove the processor   page 2 - 11
3. Install the processor   page 2 - 13

To remove th e 3G Modul e:
1. Remove the battery  page 2 - 5
2. Remove the 3G module  page 2 - 14

To remove the Wireless LAN Module:

1. Remove the battery  page 2 - 5
2. Remove the WLAN module  page 2 - 15

2 - 4 Disassembly Steps
 Disassembly

Removing the Battery Figure 1

Battery Removal
1. Turn the computer of f , and turn it over.
2. Slide the latch 1 in the direction of the arrow ( Figure 1a).
a. Slide latch at point 1 to-
3. Slide the latch 2 in the direction of the arrow, and hold it in place ( Figure 1a).
wards the unlock symbol
4. Slide the battery 63 in the direction of the arrow 4 ( Figure 1b ). and hold it in place.
b. Slide the battery in the di-
rection of the arrow.
a. b.
2
1 3

2 
.D
i  
 s 
 a
4  s 
 s 
 e
m
 b 
l  
 y 

3. Battery

Removing the Battery 2 - 5

 Disassembly

Removing the Hard Disk Drive

Figure 2 The hard disk drive can be taken out to accommodate other 2.5" serial (SATA) hard disk drives with a height of 9.5mm
HDD Assembly (h). Follow your operating system’s installation instructions, and install all necessary drivers and utilities (as outlined in
Removal Chapter 4 of the User’s Manual ) when setting up a new hard disk.

a. Locate the HDD bay cover Hard Disk Upgrade Process

and remove the screws.
1. Turn of f  the computer, and remove the battery ( page 2 - 5).
2. Locate the hard disk bay cover and remove screws 1 & 2 ( Figure 2a).

  y
   l a.
   b
HDD System Warning
  m
  e
  s New HDD’s are blank. Before you
  s begin make sure:
  a
  s
   i You have backed up any data
   D
 . you want to keep from your old
   2 HDD.

You have all the CD-ROMs and

FDDs required to install your op-
1 2 erating system and programs.

If you have access to the internet,

download the latest application
and hardware driver updates for
the operating system you plan to
install. Copy these to a remov-
able medium.
• 2 Screws

2 - 6 Removing the Hard Disk Drive

 Disassembly

3. Remove the hard disk bay cover 63 (Figure 3b ).

4. Grip the tab and slide the hard disk in the direction of arrow 4 ( Figure 3c ). Figure 3
HDD Assembly
5. Lift the hard disk 5 out of the bay 6 ( Figure 3d ).
Removal (cont’d.)
6. Remove the screw 7 - 10 and the mylar cover 11 from the hard disk 12 ( Figure 3e).
7. Reverse the process to install a new hard disk (do not forget to replace all the screws and covers).
b. Remove the HDD bay
cover.
b. d. c. Grip the tab and slide the
HDD in the direction of
the arrow.
d. Lift the HDD assembly
out of the bay.
6 5 e. Remove the screws and
mylar cover.
2 
.D
e. i  
 s 
 a
 s 
 s 
 e
m
 b 
l  
 y 
3

c. e.
7
8 3. HDD Bay Cover 
10 11. Adhesive Cover 
11
12.HDD
4 9
• 4 Screws
12

Removing the Hard Disk Drive 2 - 7

 Disassembly

Figure 4 Removing the Optical (CD/DVD) Device

Optical Device
1. Turn of f  the computer, remove the battery ( page 2 - 5) and hard disk (page 2 - 6).
Removal
2. Remove the screw at point 1 (Figure 4a).
a. Remove the screw at 3. Use a screwdriver to carefully push out the optical device 3 at point 2 ( Figure 4b ).
point 1 . 4. Insert the new device and carefully slide it into the computer (the device only fits one way. DO NOT FORCE IT; The
b. Use a screwdriver to screw holes should line up).
carefully push out the 5. Restart the computer to allow it to automatically detect the new device.
optical device at point
2 .
a. b.

  y
   l 3
   b
  m
  e
  s
  s 1
  a
  s
   i
   D
 .
   2

2 2

3. Optical Device

• 1 Screw

2 - 8 Removing the Optical (CD/DVD) Device

 Disassembly

Removing the System Memory (RAM) Figure 5

 RAM Module
The computer has two memory sockets for 200 pin Small Outline Dual In-line Memory Modules (SO-DIMM) supporting
Removal
DDRIII (DDR3) Up to 1066/1333 MHz. The main memory can be expanded up to 8GB. The SO-DIMM modules sup-
 ported are 1024MB and 2048MB DDRIII Modules. The total memory size is automatically detected by the POST rou- a. Remove the screws
tine once you turn on your computer. from the component
bay cover.
Memory Upgrade Process b. The RAM modules will
1. Turn of f  the computer, turn it over and remove the battery ( page 2 - 5). be visible at point 5
2. Remove screws 1 - 4 from the component bay cover ( Figure 5a). on the mainboard.
c. Pull the release lat-
3. The RAM modules will be visible at point 5 on the mainboard (Figure 5b).
ches.
4. Gently pull the two release latches ( 6 & 7 ) on the sides of the memory socket in the direction indicated by the d. Remove the module.
arrows (Figure 5c). The RAM module 8 will pop-up (Figure 5d ), and you can then remove it . 2 
.D
a. c. d. i  
1  s 
 a
2  s 
Contact Warning  s 
6  e
Be careful not to touch m
3 the metal pins on the  b 
module’s connecting l  
 y 
8 edge. Even the cleanest
4 hands have oils which
can attract particles, and
7 degrade the module’s
b. performance.

5
8. RAM Module

• 4 Screws

Removing the System Memory (RAM) 2 - 9

 Disassembly

5. Pull the latches to release the second module if necessary.

6. Insert a new module holding it at about a 30° angle and fit the connectors firmly into the memory slot.
7. The module will only fit one way as defined by its pin alignment. Make sure the module is seated as far into the slot
as it will go. DO NOT FORCE IT; it should fit without much pressure.
8. Press the module in and down towards the mainboard until the slot levers click into place to secure the module.
9. Replace the component bay cover and the screws (see page 2 - 8).
10. Restart the computer to allow the BIOS to register the new memory configuration as it starts up.

  y
   l
   b
  m
  e
  s
  s
  a
  s
   i
   D
 .
   2

2 - 10 Removing the System Memory (RAM)

 Disassembly

Removing and Installing a Processor  Figure 6 

Processor Removal Procedure Processor Removal
1. Turn of f  the computer, turn it over, and remove the battery ( page 2 - 5) and the component bay cover ( page 2 - 8). a. Locate the heat sink.
2. Locate the heat sink. b. Remove the screws from
3. Loosen the CPU heat sink screws in the order 3 , 2 & 1 (the reverse order as indicated on the label Figure the CPU heatsink.
6b). c. Remove the CPU heat
4. Carefully lift up the heat sink 4 ( Figure 6c) off the computer. sink.

a. c.

4 2 
.D
 A i  
 s 
 a
 s 
 s 
 e
m
 b 
l  
 y 

b.

2 4. Heat Sink

• 3 Screws

Removing and Installing a Processor 2 - 11

 Disassembly

5. Turn the release latch 5 towards the unlock symbol to release the CPU ( Figure 7d).
Figure 7  6. Carefully (it may be hot) lift the CPU 6 up and out of the socket ( Figure 7e).
Processor Removal 7. Reverse the process to install a new CPU.
(cont’d) 8. When re-inserting the CPU, pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE IT!).
d. Turn the release latch to
unlock the CPU. d.
e. Lift the CPU out of the
socket.

5
5

  y
   l
   b
  m
  e
  s
  s
  a
  s
   i Unlock Lock
   D
 .
   2
e.

Caution

6 The heat sink, and CPU area in

general, contains parts which are
subject to high temperatures. Allow
the area time to cool before remov-
ing these parts.

6. CPU

2 - 12 Removing and Installing a Processor 

 Disassembly

Processor Installation Procedure Figure 8 

1. Insert the CPU  A (Figure 8a), pay careful attention to the pin alignment, it will fit only one way (DO NOT FORCE Processor
IT!), and turn the release latch B towards the lock symbol ( Figure 8b). Installation
2. Remove the sticker  C (Figure 8c) from the heat sink.
3. Insert the heat sink D as indicated in Figure 8d. a. Insert the CPU.
4. Tighten the CPU heat sink screws in the order 1 , 2 & 3 (the order as indicated on the label and Figure 8d). b. Turn the release latch to-
wards the lock symbol.
5. Replace the component bay cover (don’t forget to replace the fan cable) and tighten the screws ( page 2 - 9).
c. Remove the sticker from
the heat sink and insert
a. c. the heat sink.
d. Tighten the screws.

 A
C 2 
.D
i  
 s 
 a
 s 
 s 
 e
m
 b 
l  
 y 
b. d.

3 D
B

2 Note:
 A. CPU
Tighten the screws D. Heat Sink
in the order as indi-
cated on the label. • 3 Screws

Removing and Installing a Processor 2 - 13

 Disassembly

Figure 9 Remov ing the 3G Module

3G Module Removal
1. Turn of f  the computer, turn it over, and remove the battery ( page 2 - 5) and the component bay cover ( page 2 - 9).
2. The 3G module will be visible at point 1 on the mainboard (Figure 9a).
a. Locate the 3G module.
b. Disconnect the cable
3. Carefully disconnect the cable 2 , and then remove the screw 3 (Figure 9b).
and remove the screw. 4. The 3G module 4 (Figure 9c) will pop-up, and you can remove it from the computer ( Figure 9d).
c. Remove the 3G module.

a. c. d.
 Note: Make sure you
reconnect the antenna
cable to socket ( Fig-
ure 9b).
  y
   l 4
   b
  m
  e
  s
  s
  a
  s
   i 1
   D
 .
   2  no 3g

b.
4

2
4. 3G Module

• 1 Screw
3

2 - 14 Removing the 3G Module

 Disassembly

Removing the Wireless LAN Module Figure 10

Wireless LAN
1. Turn of f  the computer, turn it over, and remove the battery ( page 2 - 5) and the component bay cover ( page 2 - 9).
Module Removal
2. The Wireless LAN module will be visible at point 1 on the mainboard (Figure 10a).
3. Carefully disconnect the cables 2 & 3 , and then remove the screw 4 (Figure 10b).
a. Locate the WLAN.
4. The Wireless LAN module 5 (Figure 10c) will pop-up, and you can remove it from the computer ( Figure 10d). b. Disconnect the cables
and remove the screw.
c. c. The WLAN module will
a. pop up.
d. Remove the Wireless
LAN module.

 Note: Make sure you 2 

.D
5
reconnect the antenna
i  
 s 
cable to the “1 + 2”
 a
socket ( Figure 10b).  s 
 s 
 e
m
1  b 
l  
 y 

b. d.

4
5
3
5.Wireless LAN Module

• 1 Screw
2

Removing the Wireless LAN Module 2 - 15

 Disassembly

Figure 11 Removing the Bluetooth Module

 Bluetooth Module 1. Turn of f  the computer, turn it over, and remove the battery ( page 2 - 5) and the component bay cover ( page 2 - 8).
Removal 2. The Bluetooth module will be visible at point 1 on the mainboard (Figur e 11a).
3. Remove screw 2 (Figu re 11b) and turn the module over ( Figur e 11c).
a. Locate the Bluetooth 4. Carefully disconnect the cable 3 and separate the connector 4 ( Figur e 11c) from the Bluetooth Module.
module.
5. Lift the Bluetooth Module 5 (Figu re 11d) up and off the computer.
b. Remove the screw and
turn the module over.
c. Disconnect the cable a. c. d.
and the connector from
the Bluetooth module.
d. Lift the Bluetooth module
out. 3
  y
   l
   b
  m
  e
  s
  s
  a
  s
   i 1 4
   D
 .
   2

b.

5. Bluetooth Module
2

• 1 Screw

2 - 16 Removing the Bluetooth Module

 Disassembly

Removing the Keyboard Figure 12

Keyboard Removal
1. Turn of f  the computer, and remove the battery ( page 2 - 5).
2. Remove screws 1 - 2 from the bottom of the computer. Press at point 3 to unsnap the LED cover module (you a. Remove screws from the
may need to use a small screwdriver to do this Figure 12a). bottom of the computer.
b. Turn the computer over,
3. Turn the computer over, unsnap up the LED cover module 4 from point 5 on the left of the computer, towards the
unsnap up the LED cov-
right (Figure 12b). er module from point 5
4. Remove screws 6 - 10 from the keyboard ( Figure 12c). towards the right .
5. Carefully lift the keyboard up, being careful not to bend the keyboard ribbon cable 11. Disconnect the keyboard c. Remove screws from
ribbon cable 11 from the locking collar socket 12 (Figure 12d) the keyboard.
6. Carefully lift up the keyboard 13 (Figure 12e) off the computer. d. Carefully lift the key-
board up and disconnect
a. d. the keyboard ribbon ca-
11
ble from the locking col- 2 
lar socket. .D
12
e. Remove the keyboard. i  
 s 
1 3 2  a
 s 
 s 
b.  e
m
5  b 
Re-Inserting the
4 l  
 y 
Keyboard
e.
When re-inserting the
keyboard firstly align the
four  keyboard tabs at the
bottom (Figure 12c) at
the bottom of the key-
c. board with the slots in the
case.
6 7 8 9 10

13

4. LED Cover Module

13. Keyboard

• 7 Screws
Keyboard Tabs

Removing the Keyboard 2 - 17

 Disassembly

  y
   l
   b
  m
  e
  s
  s
  a
  s
   i
   D
 .
   2

2 - 18
 Ap
 A p p end
en d i x A : Part
Par t L i s t s
the  E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C  series notebook’s construc-
This appendix breaks down the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C 
tion into a series of illustrations. The component part numbers are indicated in the tables opposite the drawings.

Note: This section indicates the manufacturer’s part numbers. Your organization may use a different system, so be sure
to cross-check any relevant documentation.

Note: Some assemblies may have parts in common (especially screws). However, the part lists DO NOT indicate the
total number of duplicated parts used.

Note: Be sure to check any update notices. The parts shown in these illustrations are appropriate for the system at the A 
time of publication. Over the product life, some parts may b e improved or re-configured, resulting in new part numbers. .P 
 a
r 
 t  
L 
i  
 s 
 t  
 s 

A - 1
 Part
Part Lis t Illustration Location
The following table indicates where to find the appropriate part list illustration.
Table A - 1
Part List Illustration
E5120Q/E5120Q-C/E5125/
Location Part
E5125-C/E5128Q/E5128Q-C

Top (E5120Q)  page A - 3

Top (E5125)  page A - 4
Top (E5128Q)  page A - 5
Bottom  page A - 6 
  s
   t
  s DVD Dual Drive  page A - 7 
   i
   L
   t
  r
LCD  page A - 8
  a
   P
 .
   A

 A - 2
Top (E5120Q)

Figure A - 1 A 
Top (E5120Q) .P 
 a
r 
 t  
L 
i  
 s 
 t  
 s 

 非耐落

灰色

Top (E5120Q) A - 3
 Top (E5125)

Figure A - 2
  s
   t Top (E5125)
  s
   i
   L
   t
  r
  a
   P
 .
   A

 非耐落

灰色

 A - 4 Top (E5125)
Top (E5128Q)

Figure 3 A 
Top (E5128Q) .P 
 a
r 
 t  
 非耐落
L 
i  
 s 
 t  
 非耐落
 非耐落

 s 
 非耐落
 非耐落

灰色
灰色

 非耐落

灰色

Top (E5128Q) A - 5
 Bottom

Figure A - 4
  s
   t Bottom
  s
   i
   L
   t
  r
  a
   P
 .
   A

 A - 6 Bott om
DVD Dual Driv e

Figure A - 5
DVD Dual Drive
A 
.P 
 a
r 
 t  
L 
i  
 s 
非耐落
 t  
 s 
志精

DVD Dual Drive A - 7

 LCD

Figure A - 6 
  s
   t LCD
  s
   i
頭厚

   L
非耐落

   t
  r
非耐落
頭厚

  a
   P
 .
   A

 A - 8 LCD
 Schematic Diagrams

 Appendix B: Schematic Diagrams

This appendix has circuit diagrams of the E5120Q/E5120Q-C/E5125/E5125-C/E5128Q/E5128Q-C  notebook’s PCB’s.
The following table indicates where to find the appropriate schematic diagram.

Diagram - Page
System Block Diagram - Page B - 2
Clock Generator - Page B - 3
CPU 1/7 (DMI, PEG, FDI) - Page B - 4
CPU 2/7 (CLK, MISC, JTAG) - Page B - 5
CPU 3/7 (DDR3) - Page B - 6   IBEXPEAK - M 6/9 - Page B - 20
CPU 4/7 (Power) - Page B - 7   IBEXPEAK - M 7/9 - Page B - 21
CPU 5/7 (Graphics Power) - Page B - 8
CPU 6/7 (GND) - Page B - 9
CPU 7/7 (RESERVED) - Page B - 10
 DDR3 SO-DIMM_0 - Page B - 11
 DDR3 SO-DIMM_1 - Page B - 12
 LVDS, Inverter - Page B - 13
 HDMI, CRT - Page B - 14
 IBEXPEAK- M 1/9 - Page B - 15
Table B - 1
SCHEMATIC
Diagram - Page Diagram - Page
DIAGRAMS
 IBEXPEAK - M 2/9 - Page B - 16   LED, MDC, BT - Page B - 30 B 
.
 S 
 IBEXPEAK - M 3/9 - Page B - 17  USB, Fan, TP, Multi-Conn - Page B - 31
 c 
 IBEXPEAK - M 4/9 - Page B - 18  5VS, 3VS, 1.5VS - Page B - 32 h 
 e
 IBEXPEAK - M 5/9 - Page B - 19  Power 3.3V/5V - Page B - 33 m
 a
 Power 1.5V/0.75V, 1.8VS - Page B - 34  t  
i  
 c 
 Power 1.1VS_VTT - Page B - 35
D
 IBEXPEAK - M 8/9 - Page B - 22  Power VGFX_Core - Page B - 36  i  
 a
Version Note  g
 IBEXPEAK - M 9/9 - Page B - 23 V-Core - Page B - 37  r 
 a
 New Card, Mini PCIE - Page B - 24  AC_IN, Charger - Page B - 38
The schematic dia- m
grams in this chapter
 s 
 3G, CCD, TPM - Page B - 25 Click Board - Page B - 39 are based upon ver-
Card Reader/LAN JMB251C - Page B - 26   Audio Board/USB - Page B - 40
sion 6-7P-E51Q5-003.
If your mainboard (or
 LAN (JMC251C), SATA HDD, ODD - Page B - 27   Power Switch & LED Board - Page B - 41 other boards) are a la-
 Audio Codec VIA1812 - Page B - 28  External ODD Board - Page B - 42
ter version, please
check with the Service
 KBC-ITE IT8502E - Page B - 29 Center for updated di-
agrams (if required).

B - 1
 Schematic Diagrams

System Block Diagram

CLICK BOARD
6-71-E51Q2-D01A  Calpella System Bl ock Diagram  VDD3,VDD5

POWER SWITCH BOARD 14.318 MHz

POWER SWITCH+HOTKEY X 3 POWER GPU 1.8VS
6-71-E51QS-D01A  Clock Generator
 Memory Termination
RTM875N-632-VB-GRT
 AUDIO BOARD  Arrandale 800/1067 MHz 5V,3V,5VS,3VS,1.5VS,
USB+EARPHONE+EXT.MIC DDR3 / 1.5V 
6-71-C4508-D02A  PROCESSOR  DDRIII
SO-DIMM0
EXTERNAL ODD BOARD rPGA989/988 SYSTEM SMBUS 1.5V,0.75VS(VTT_MEM)
EXT. ODD
6-71-E51QN-D01
0.1"~13 DDRIII
SO-DIMM1
SHEET 11  VCORE 1.1VS_VTT
  s FDI DMI*4
  m HDMI
  a 0.5"~6.5" <=8"
  r
  g <15"  AUDIO BOARD
  a
   i Sheet 1 of 42
CLICK BOARD
TOUCH PAD CRT C ONNECTOR 
CRT SWITCH
INTERNAL
GRAPHICS Ibex Peak-M
   D System Block Synaptic
810602-1703 Platform RJ-11
 MIC
IN
HP
OUT

  c
   i Diagram
LCD CONNECTOR, <8"
INTERNAL
Controller
   t
LVD S SWI TCH
GRAPHICS

  a Hub (PCH)

 AZALIA  INT SPK R 

  m 32.768 KHz

 MDC  AMP

  e EC
SPI TPM   MODULE
 Azalia Codec  N7101

   h ITE 8502E  VIA VT1812 INT SPK L

  c
128pins LQFP
 MDC CON
14*14*1.6mm 33 MHz
   S
 . LPC 27x27mm  INT MIC

   B 0.5"~11" BIOS

SPI
1071 Ball FCBGA   AZALIA LINK 24 MHz
INT. K/B EC SMBUS
PCIE 100 MHz <12"
THERMAL SMART SMART
SENSOR  FAN BATTERY
32.768KHz
 W83L771AWG
 New Card   Mini PCIE
3G CARD JMICRO
SOCKET SOCKET
USB2.0 (USB9) JMC251 C
SATA I/II 3.0Gb/s <12"
480 Mbps
(USB3) (USB2)
LAN CARD READER 
25
1"~16"
 MHz

7IN1
RJ-45
SOCKET
USB0 USB1 USB4 Bluetooth CCD
SATA HDD SATA ODD
(USB11) (USB5)

 AUDIO
BOARD

B - 2 System Block Diagram

 Schematic Diagrams

Clock Generator 

CLKGEN POWER 
CLOCK GENERATOR 
CL K _ V CC 1 CL K_ V CC 2 3 .3 V S
CL K _ VCC1
U7

1 15 L15 * 15 m i _l s ho rt_ 0 6

5 VD D_ DO T V DD_ S R C_ I/O 18
17 VD D_ 2 7 V DD_ CP U_ I/O C2 0 5 C 19 7 C2 07
24 VD D_ S RC
29 VD D_ CPU 3 0 .1u _ 1 6V _ Y5 V_ 0 4 0 .1 u_ 1 6 V_Y 5V _ 0 4 1u _ 6.3 V _ X5R _0 4
VD D_ REF D OT _ 96 4 C LK _B U F _D OT 9 6_ P 1 5
DO T_ 9 6# C LK _B U F _D OT 9 6_ N 15

6
27M 7
XO UT 27 2 7 M_ SS
XT AL _O UT
XIN 28
XT AL _IN
0.1uF near the every power pin
10
S RC _1 /SA T A C LK _S AT A 1 5
11

B 
S RC_ 1 #/S ATA# 13 C LK _S AT A# 1 5
30 S RC _2 14 C LK _P C IE_ ICH 1 5
15 CL K_ BUF _ R E F 14 R 13 4 3 3_ 0 4 REF _ 0 /CP U_ S EL C LK _PC IE_ ICH# 1 5
R E F _ 0/C PU_ S E L S R C_ 2#

CL K _ SDAT A 31
SD A
.
 S 
 c 
CL K _ SCL K 32 16 CP U _S T O P # R148 2 .2 1 K _ 1% _ 0 4
SC L CP U_ S T OP# 3 .3 V S 1 .1 V S_V TT
2 20 C LK _V C C2

h 
8 VS S _D OT CPU _1 19
9 VS S _2 7 CP U_ 1# 23 L 14 * 1 5 m i l _ s h o r t _ 06
C LK _B U F _B CL K _P 15

 e
12 VS S _SA T A CPU _0 22
21 VS S _SR C CP U_ 0# C LK _B U F _B CL K _N 1 5
C2 06 C1 9 6
VS S _C PU

m
26
VS S _R EF CK P W RGD /P D#
25 CL K _ P W RG D  VDD_I /O c an be

Sheet 2 of 42
33 0.1 u _ 16 V_ Y5 V _ 04 1 u_ 6 .3 V _X 5 R_ 0 4
G ND ranging from 
3 .3 V S 1.05V to 3.3V 

 a
SL G 8S P5 8 5

Clock Generator 
 t  
Slego SLG8SP585 6-02-08585-EQ0

i  
R 14 9
Realte k RTM875N-632- VB- GRT

 c 
0.1uF near the every power pin
1 0 K_1 % _ 04

   D

Q1 2 R 14 6 D
i  
G
SMBus 36 CL KE N #

 a
MT N7 00 2 Z HS3 1 M_ 0 4
    S
Q1 1A
EMI
 g
MT DN 70 0 2Z H S6 R
   2
   D    S
15 SMB _ CL K
   6 1
CL K _ SCL K
CL K _ S CL K 1 0 ,11
6-22-1 4R31- 1B7
6-22-1 4R31- 1B6
r 
 a
   G 3 .3V S

5 VS 1 4 RN 15 XIN
X1

2
HS X5 30G_ 1 4.31 818M Hz

1 X OUT
m
 s 
2 3 2 .2K _ 4 P 2 R_ 04 R E F _ 0/C P U_ S EL C 19 4 * 1 0 p _5 0 V _ N P O _ 0 6
   G
   3 4
C1 99 C 20 2
CL K _ SDAT A
15 SMB _ DAT A CL K _ S DA TA 1 0 ,11
33 p _5 0V_ NP O_ 0 4 3 3 p_ 5 0 V _N PO_ 0 4 EMI Capactior
   D    S
   5
Q1 1B
MT DN 70 0 2Z H S6 R

CPU_SEL_During CK_PEWGD Latch Pinl

3 .3V S
PIN _3 0 CPU_0 C P U_ 1
R 13 6 * 4. 7 K _0 4 RE F _0 /CP U _ S EL
0(default) 133MHz 133MHz
R 13 7 1 0K _ 0 4
1(0.7V-1.5V) 100MHz 100MHz 5VS 1 3 ,17 ,2 0,2 1 ,2 6,2 7 ,30,3 1,35 ,36
3.3 V 3 ,4 ,12 ,1 ,41 5 ,1 6,1 8,1 9,2 0 ,21 ,2 3 ,24,2 5 ,29 ,3 ,0 31 ,3 3,3 4,3 5
3.3 VS 1 0 ,11 ,1 2,1 3 ,1 4,1 5 ,1 6,1 7 ,18 ,1 9 ,20 ,2 1 ,23 ,2 4,2 5 ,2 6,2 7 ,2 8,2 9 ,30 ,3 1 ,35,3 6
1.1 VS _ VT T 4 ,6 ,7 ,14 ,1 5 , 16 ,1 9, 20 ,2 1,3 4 ,3 5,3 6

Clock Generator B - 3
 Schematic Diagrams

CPU 1/7 (DMI, PEG, FDI)

PROCESSOR 1/7 ( DMI,PEG,FDI )

U 16 A
B2 6 20 mil PEG_ IR CO MP_ R R 20 9 4 9 .9 _ 1 % _ 04
PEG_ IC OM PI A2 6
A2 4 PEG _ ICO MPO B2 7
16 DM I_T XN0 C2 3 DM I_ RX# [0 ] PEG_ R CO MPO A2 5 EXP _R BIAS R 20 8 7 50 _ 1 % _0 4
16 DM I_T XN1 B2 2 DM I_ RX# [1 ] PE G_ RBI AS
16 DM I_T XN2 A2 1 DM I_ RX# [2 ] K3 5
16 DM I_T XN3 DM I_ RX# [3 ] PE G_ RX# [0 ] J34
B2 4 PE G_ RX# [1 ] J33
16 DM I_T XP0 D2 3 DM I_ RX[0 ] PE G_ RX# [2 ] G 35
16 DM I_T XP1 B2 3 DM I_ RX[1 ] D  PE G_ RX# [3 ] G 32
16 DM I_T XP2 A2 2 DM I_ RX[2 ] M PE G_ RX# [4 ] F34
16 DM I_T XP3 DM I_ RX[3 ] I   PE G_ RX# [5 ] F31
D2 4 PE G_ RX# [6 ] D 35
16 D MI_ R XN 0 G2 4 DM I_ T X# [0 ] PE G_ RX# [7 ] E3 3
16 D MI_ R XN 1 F23 DM I_ T X# [1 ] PE G_ RX# [8 ] C 33
16 D MI_ R XN 2 H2 3 DM I_ T X# [2 ] PE G_ RX# [9 ] D 32
16 D MI_ R XN 3 DM I_ T X# [3 ] PEG_ R X# [1 0 ] B3 2

  s
D2 5 PEG_ R X# [1 1 ] C 31
16 D MI_ R XP 0 F24 DM I_ T X[0 ] PEG_ R X# [1 2 ] B2 8
16 D MI_ R XP 1 DM I_ T X[1 ] PEG_ R X# [1 3 ]
E2 3 B3 0
16 D MI_ R XP 2 DM I_ T X[2 ] PEG_ R X# [1 4 ]

  m
G2 3 A3 1
16 D MI_ R XP 3 DM I_ T X[3 ] PEG_ R X# [1 5 ]

  a
J35
PEG _ RX[0 ] H 34

  r
PEG _ RX[1 ] H 33
E2 2 PEG _ RX[2 ] F35

  g
16 F D I_ T XN 0 F D I_T X# [0 ] PEG _ RX[3 ]
D2 1 G 33
16 F D I_ T XN 1 D1 9 F D I_T X# [1 ] PEG _ RX[4 ] E3 4

  a
16 F D I_ T XN 2 D1 8 F D I_T X# [2 ] PEG _ RX[5 ] F32

   i
16 F D I_ T XN 3 G2 1 F D I_T X# [3 ] PEG _ RX[6 ] D 34
16 F D I_ T XN 4 E1 9 F D I_T X# [4 ] PEG _ RX[7 ] F33
16 F D I_ T XN 5 F21 F D I_T X# [5 ]    S PEG _ RX[8 ] B3 3

   D    C
16 F D I_ T XN 6 G1 8 F D I_T X# [6 ] I   PEG _ RX[9 ] D 31

Sheet 3 of 42 16 F D I_ T XN 7 F D I_T X# [7 ] n
   I
   H
PE G_ RX[1 0 ]
PE G_ RX[1 1 ]
A3 2
C 30

  c
t  
PE G_ RX[1 2 ]
D2 2
   P A2 8

   i
16 F D I_ T XP0
 e
CPU 1/7 C2 1 F D I_T X[0 ]
   A
PE G_ RX[1 3 ] B2 9

   t
16 F D I_ T XP1 F D I_T X[1 ]
l   PE G_ RX[1 4 ]
D2 0 A3 0
16 F D I_ T XP2
   R
C1 8 F D I_T X[2 ]
 (   PE G_ RX[1 5 ]
   G
  a
16 F D I_ T XP3 F D I_T X[3 ]
G2 2
R  L33

(DMI, PEG, FDI) 16

16
F D I_ T
F D I_ T
XP4
XP5
E2 0
F20
F D I_T X[4 ]
F D I_T X[5 ]
 )  
  -
PEG _ TX# [0 ]
PEG _ TX# [1 ]
M 35
M 33
  -
  m
16 F D I_ T XP6 F D I_T X[6 ] PEG _ TX# [2 ]
G1 9
F  M 30
16 F D I_ T XP7 F D I_T X[7 ] D  PEG _ TX# [3 ] L31
   S PEG _ TX# [4 ]

  e
It applies to Au
burnd
ale and Cl arksfi eld discrete graphic designs. F17
I   K3 2
If discrete graphic chip is used for Auburnd
ale, VAXG(GFX core) rail can beconnected
16
16
F DI_ F SY NC 0
F DI_ F SY NC 1
E1 7 F D I_F SYN C[0 ]
F D I_F SYN C[1 ]    S PEG _ TX# [5 ]
PEG _ TX# [6 ]
M 29
J31
   E
   h
to GNDif motherboardonly supports discrete graphics andal soi na com mon C1 7 PEG _ TX# [7 ] K2 9
motherboarddesign if GFXVRis notst uff ed. Onthe otherhand , if the VR is stuff ed, 16 F DI_ IN T F D I_IN T    R PEG _ TX# [8 ] H 30

  c VAX G canbe l eft fl oati ngi n a comm

on m
otherboard design( Gfx VRkeeps VAXGfrom F18    P PEG _ TX# [9 ] H 29
fl oating).
16 F DI_ L SYN C0 D1 7 F D I_L SY NC [0 ]    X PE G_ T X# [1 0 ] F29
   E
   S
16 F DI_ L SYN C1 F D I_L SY NC [1 ] PE G_ T X# [1 1 ] E2 8
In addition, FDI_RXN_[7: 0] andFDI_RXP_[7: 0] canbe left fl oatingon the PCH
.

 .
PE G_ T X# [1 2 ] D 29
FDI_TX[7:0] andFDI_ TX#[7:0] canbe left fl oati ng on the Auburndale.
 TheGFX _I MON
, FDI_ FSYNC[0], FDI_ FSYNC[1], FDI_ LSYNC[0], FDI_LSYNC[1], and    I PE G_ T X# [1 3 ] D 27
   C PE G_ T X# [1 4 ] C 26

   B
FDI_INTsi gnals should bet i edt o GND(thr ough 1 K ? %resistors) in t hecomm
on PE G_ T X# [1 5 ]
motherboarddesign case. Please not that if these signals are lef t fl oati ng, there are no    P L34
PEG _T X[0 ] M 34
f uncti onal i mpacts but a small amount of po w
er (~15 m
W) maybe wasted. VAXG_SENSE PEG _T X[1 ] M 32
andVSSAXG_SENSEon Auburndale can be left as noconnect. PEG _T X[2 ] L30
DPLL_REF_SSC LK andDPLL_REF_SSCLK#can be c onnected to GND on Auburndale PEG _T X[3 ] M 31
directly i f motherboard only supports dis crete graphics. I n a comm
on motherboard PEG _T X[4 ] K3 1
PEG _T X[5 ] M 28
design, t hese pins are driven via PCH(even if G
raphics is disabled by BIOS) thus no
PEG _T X[6 ] H 31
external terminati oni s required. PEG _T X[7 ] K2 8
PEG _T X[8 ] G 30
PEG _T X[9 ] G 29
PEG _ TX[1 0 ] F28
PEG _ TX[1 1 ] E2 7
Thermal Sensor near U16 PEG _ TX[1 2 ] D 28
PEG _ TX[1 3 ] C 27
PEG _ TX[1 4 ] C 25
PEG _ TX[1 5 ]

PZ 9 8 9 2 7-3 6 4 1 -01 F

3 .3 V

 Analog Thermal Sensor

C 35 7 R 2 28 * 1 0 m i l s_ ho rt _ 04 3 .3 V
C RIT _ TE MP_ RE P# 19
Q 14
* 0.1 u _ 16 V_ Y 5V _0 4 2 1 1:2 (4mi ls:8m ils)
VCC OU T T HER M_ VO L T 2 8
T HER M_ AL ER T # 2 8 4 ,1 2,1 4 ,1 5 ,16 ,1 8 ,1 9 ,20 ,2 1 , 2 3,2 4 ,2 5 ,2 9,3 0 ,3 1 ,33 ,3 4 ,3 5 3.3 V
U1 8
1 4 C A C359 3 C3 6 0
2 VDD T HE RM 6 P M _ E X T T S #_ E C 4 GN D
    C D+ AL ER T D1 6 * C D B U 0 30 4 0 0 .1 u _ 16 V_ Y 5V _0 4 0. 1u _ 1 6V _Y 5 V_ 04
B G7 1 1 ST9 U
1
Q 10 3
*2 N3 9 0 4 3 7
   E 5 D- SDA TA 8 SM D_ CPU _ T HER M 1 5 ,2 8
GN D SC LK SM C_ CPU _ T HER M 1 5 ,2 8

*W 8 3 L 7 71 AW G PL ACE NEAR U16 2

B - 4 CPU 1/7 (DMI, PEG, FDI)

 Schematic Diagrams

CPU 2/7 (CLK, MISC, JTAG)

PROCESSOR 2/7 ( CLK,MISC,JTAG ) 1.5 V

Processor Compensation
R 2 03
Signals * 1 K_ 1% _ 0 4

R 23 8 4 9 . 9 _ 1% _ 0 4 H_ CO MP 0 R 20 6 * 10 m il_ s h ort_ 0 4

R 21 3 4 9 . 9 _ 1% _ 0 4 H_ CO MP 1 DDR3 Compensation Signals BSS138( VGS 1.5V )

SM _R CO MP_ 0 R 22 9 1 0 0 _ 1% _ 0 4 Q1 3
*R J U0 0 3N 0 3T 1 0 6
SM _R CO MP_ 1 R 23 0 2 4 . 9 _ 1% _ 0 4 SM_ DR AMR ST # S D
H_ CO MP 2 DD R3 _ DR AM RST # 1 0,1 1
R 2 37 2 0 _ 1% _ 0 4
SM _R CO MP_ 2 R 23 1 1 3 0 _ 1% _ 0 4
R 2 36 2 0 _ 1% _ 0 4 H_ CO MP 3 R2 0 7
*1 0 0K _1 %    G
 _ 04

DR AMR ST _C T RL 9 ,1 9
TRACE WIDTH 10MIL, LENGTH <500MILS

C3 1 1 ? ? IBEXCONTR
OL

U 1 6B
*4 7 n _5 0 V_ 0 4
B 
.
H_ C OM P3 A T2 3

 S 
C OM P3 A1 6
M BC L K BCL K_ CP U_ P 1 9
H_ C OM P2 A T2 4 B1 6
Processor Pullups C OM P2 BCL K# BCL K_ CP U_ N 1 9

 c 
I  
H_ C OM P1 G1 6  S  AR 30
C OM P1 BCL K_ IT P AT 3 0

h 
1 .1 VS_ VT T H_ C OM P0 A T2 6
 C     S BCL K_ IT P#

R 21 9 4 9 . 9 _ 1% _ 0 4 H_ CA TER R# AH2 4
C OM P0
   K
   C
PEG _C L K
PEG _ CL K#
E1 6
D 16 CL K_ EXP_ P 1 5
CL K_ EXP_ N 1 5 Sheet 4 of 42  e
   O
m
SKT O CC # A1 8
R 2 39 6 8 _ 04 H_ PR OC HO T# _ D
H_ C AT ERR # AK1 4 T     L
DPL L _ REF _ SSC L K
DP LL _ RE F _S SCL K #
A1 7
CL K_ DP_P 15
C L K _ DP _ N 1 5 CPU 2/7
C ATE RR #
H     C
 a
R 2 47 * 68 _ 0 4 H_ CP UR ST#

(CLK, MISC, JTAG)

 t  
E  F6 S M_ DR AMR ST #
A T1 5 SM_ D RAM RST # 1.1 VS_ VT T
19 ,2 8 H_ PEC I PEC I AL 1 S M_ RC OM P_ 0
i  
 c 
R 
M SM_ RC OM P[0 ] AM 1 S M_ RC OM P_ 1 R 23 3 10 K _ 0 4
SM_ RC OM P[1 ] AN 1 S M_ RC OM P_ 2
A  R5 4 10 K _0 4
SM_ RC OM P[2 ]
R 24 8 * 10 m i _l s h ort_ 0 4 H_ PRO CH OT # _ D AN2 6
   3   C
D
3 6 H_ PRO CH OT # PR OC HO T# L  AN 15 P M_ EXTT S# [0 ]
I f PROCHOT# is not used, then it must be terminated    R   S P M_ EXT_ T S# [0 ] AP1 5 P M_ EXTT S# [1 ]
R5 3
R 23 2
*0 _0 4
* 0_0 4
PM _EXT T S# _E C 3
   D   I T S# _D IMM 0 _1 1 0 ,1 1

i  
P M_ EXT_ T S# [1 ]
witha 50-O pull -up resistor to VTT
_ 1.1 rail.
   D   M
 a
AK1 5 R 23 4 * 1 2 . 4 K_ 1 % _ 0 4
1 9 H_ T HR MT R IP# T HER MT R IP#

P RD Y#
AT 2 8
AP2 7 XD P_ PREQ #  g
H_ C PUR ST # AP2 6
PRE Q#
AN 28
T C K   AP 2 8
XD P_ TC L K
XD P_ TM S
r 
 a
m
R ESET _O BS# P  T M S AT 2 7
XD P_ TR ST #
W T RST #
A L1 5 AT 2 9
   M
1 6 H_ PM _ SYN C XD P_ TD I_ R
PM _S YN C TDI
R 
 s 
AR 27 XD P_ TD O_ R
   P T DO
T DI _M
AR 29 XD P_ TD I_ M 1.1 VS_ VT T
1 6,3 6 D ELA Y_ PW R GD R 24 9 * 0 _0 4 SY S_ AGEN T_ PW RO K AN1 4
VC CPW R GO OD _ 1
M
A     B T DO _M
AP2 9 XD P_ TD O_ M
XD P_ T MS R 25 2 * 51_ 0 4
R 25 0 * 10 m il_ s ho rt_ 0 4 AN 25 XD P_ T DO _M R 24 4 51 _ 0 4
AN2 7
   & DB R# XD P_ T DI_ R R 25 1 * 51_ 0 4
N 
19 H _C PU PW RG D VC CPW R GO OD _ 0 XD P_ PRE Q#
A  R 24 2 * 51_ 0 4
AJ 2 2 XD P_ T DO _R R 24 1 * 51_ 0 4
AK1 3
   G B PM# [0 ] AK2 2
1 6 PM_ D RAM _ PW RG D R 52 * 10 m il_ s ho rt_ 0 4 VD DPW R GO OD _ R
 G 
SM _D RA MPW R OK B PM# [1 ]
   A AK2 4
E 
B PM# [2 ] AJ 2 4
   T B PM# [3 ]
AM1 5
M AJ 2 5
16 H _V TT PW R GD VT T PW R GOO D
   J B PM# [4 ] AH 22
E 
B PM# [5 ] AK2 3 XD P_ T CL K
Connect to the P rocessor (VTTPWRGOOD) VTT_1.1 VR pow er N  R 24 5 * 51_ 0 4
goodsi gnal to processor. Si gnal vol tage level is 1.1 V. H_ PW RG D_ XDP AM2 6 B PM# [6 ] AH 23 XD P_ T RST # R 24 0 51 _ 0 4
T APPW R GO OD T  B PM# [7 ]

R 60 1 . 5 K _ 1 % _ 04 PL T _R ST # _R A L1 4
1 8 ,23 ,2 5 ,2 8 B UF _ PL T _R ST # R STI N#
Signal fromPCHt oPr ocessor
Connect to PCH( PLT_RST#) R 61
(need s to be level translated 7 5 0 _1 % _ 04 PZ 98 9 2 7-3 6 4 1 -01 F
f r o m3 . 3 V t o 1 . 1 V ) .

XD P_ T DO _M R 24 3 * 10 m il_ s h ort_ 0 4XDP_ T DI_ M

1 .5 VS_ CPU

3.3 V
R5 0

1 .1 K_1 % _ 0 4 R 2 35 * 8. 2 K _ 04
3 .3V 3 ,1 2,1 4 ,1 5 ,16 ,1 8 ,1 9,2 0 ,2 1 ,23 ,2 4 ,2 5,2 9 ,3 0 ,31 ,3 3 ,3 4,3 5
VD DPW R GO OD _ R
   5 1 .5V 9 ,1 0,11 ,2 1 ,23 ,2 7 ,2 9,3 1 ,3 3 ,36
U17 1 .5V S_C PU 7,3 1
1 IN 3 .3V
4 1 .1V S_V TT 2 ,6 ,7 ,1 4,1 5 ,1 6, 19 ,2 0 ,2 1,3 4 ,3 5, 36
R6 2 R 24 6 * 1 . 5 K _ 1 % _ 04 DRA MPW R GD _ CPU
2
1 .1 VS_ VT T _P W RG D 1 6 ,3 3 ,34
3 K_ 1% _ 0 4
   3
* MC 7 4VH C1 G 08 D F T 1G

Intel change
4.75K -->1.1K
12K -->3K

CPU 2/7 (CLK, MISC, JTA G) B - 5

 Schematic Diagrams

CPU 3/7 (DDR3)

PROCESSOR 3/7 ( DDR3 )
U16C
U16D

 AA6
SA_CK[0]  AA7 M_CLK_DDR0 10 W8
10 M_A_DQ[63:0] SA_CK#[0] M_CLK_DDR#0 10 11 M_B_DQ
[ 63
: 0] SB_CK[0] M_CLK_DDR2 11
P7 W9
SA_CKE[0] M_CKE0 10 SB_CK#[0] M_CLK_DDR#2 11
M_A_DQ0  A1 0 M_B_DQ0 B5 M3
SA_DQ[0] SB_DQ[0] SB_CKE[ 0] M_CKE2 11
M_A_DQ1 C1 0 M_B_DQ1  A5
M_A_DQ2 C7 SA_DQ[1] M_B_DQ2 C3 SB_DQ[1]
M_A_DQ3  A7 SA_DQ[2] Y6 M_B_DQ3 B3 SB_DQ[2] V7
B1 0 SA_DQ[3] SA_CK[1] Y5 M_CLK_DDR1 10 E4 SB_DQ[3] SB_CK[1] V6 M_CLK_DDR3 11
M_A_DQ4 M_B_DQ4
D1 0 SA_DQ[4] SA_CK#[1] P6 M_CLK_DDR#1 10  A6 SB_DQ[4] SB_CK#[1] M2 M_CLK_DDR#3 11
M_A_DQ5 M_B_DQ5
M_A_DQ6 E1 0 SA_DQ[5] SA_CKE[1] M_CKE1 10 M_B_DQ6  A4 SB_DQ[5] SB_CKE[ 1] M_CKE3 11
M_A_DQ7  A8 SA_DQ[6] M_B_DQ7 C4 SB_DQ[6]
M_A_DQ8 D8 SA_DQ[7] M_B_DQ8 D1 SB_DQ[7]
M_A_DQ9 F10 SA_DQ[8]  AE2 M_B_DQ9 D2 SB_DQ[8]
SA_DQ[9] SA_CS#[0] M_CS#0 10 SB_DQ[9]
M_A_DQ10 E6  AE8 M_B_DQ10 F2  AB8
F7 SA_DQ[10] SA_CS#[1] M_CS#1 10 F1 SB_DQ[10] SB_CS#[0]  AD6 M_CS#2 11
M_A_DQ11 M_B_DQ11

  s
E9 SA_DQ[11] C2 SB_DQ[11] SB_CS#[1] M_CS#3 11
M_A_DQ12 M_B_DQ12
B7 SA_DQ[12] F5 SB_DQ[12]
M_A_DQ13 M_B_DQ13
M_A_DQ14 E7 SA_DQ[13]  AD8 M_B_DQ14 F3 SB_DQ[13]
M_ODT
0 10

  m
M_A_DQ15 C6 SA_DQ[14] SA_ODT[0]  AF9 M_B_DQ15 G4 SB_DQ[14]  AC7
SA_DQ[15] SA_ODT[1] M_ODT
1 10 SB_DQ[15] SB_ODT[0] M_ODT2 11
M_A_DQ16 H1 0 M_B_DQ16 H6  AD1
M_ODT3 11

  a
M_A_DQ17 G8 SA_DQ[16] M_B_DQ17 G2 SB_DQ[16] SB_ODT[1]
K7 SA_DQ[17] J6 SB_DQ[17]

  r
M_A_DQ18 M_B_DQ18
M_A_DQ19 J
8 SA_DQ[18] M_B_DQ19 J3 SB_DQ[18]
G7 SA_DQ[19] G1 SB_DQ[19]

  g
M_A_DQ20 M_B_DQ20 M_
B_DM[7:0] 11
M_A_DQ21 G1 0 SA_DQ[20] M_B_DQ21 G5 SB_DQ[20] D4 M_B_DM0
SA_DQ[21] M_A
_DM[7
: 0] 10 SB_DQ[21] SB_DM[0]
M_A_DQ22 J
7 B9 M_A_DM0 M_B_DQ22 J2 E1 M_B_DM1

  a M_A_DQ23 J10 SA_DQ[22] SA_DM[0] D7 M_A_DM1 M_B_DQ23 J1 SB_DQ[22] SB_DM[1] H3 M_B_DM2

   i Sheet 5 of 42 M_A_DQ24 L

7 SA_DQ[23] SA_DM[1] H7 M_A_DM2 M_B_DQ24 J5 SB_DQ[23] SB_DM[2] K1 M_B_DM3
M_A_DQ25 M6 SA_DQ[24] SA_DM[2] M7 M_A_DM3 M_B_DQ25 K2 SB_DQ[24] SB_DM[3]  AH1 M_B_DM4

   D
M_A_DQ26 M8 SA_DQ[25] SA_DM[3]  AG6 M_A_DM4 M_B_DQ26 L3 SB_DQ[25] SB_DM[4]  AL
2 M_B_DM5

CPU 3/7 L
9 SA_DQ[26] SA_DM[4]  AM7 M1 SB_DQ[26] SB_DM[5]  AR4
M_A_DQ27 M_A_DM5 M_B_DQ27 M_B_DM6
M_A_DQ28 L
6 SA_DQ[27] SA_DM[5]  AN10 M_A_DM6 M_B_DQ28 K5 SB_DQ[27] SB_DM[6]  AT
8 M_B_DM7
SA_DQ[28] SA_DM[6] SB_DQ[28] SB_DM[7]

  c
M_A_DQ29 K8  AN13 M_A_DM7 M_B_DQ29 K4

   i
SA_DQ[29] SA_DM[7] SB_DQ[29]

(DDR3)
M_A_DQ30 N8 M_B_DQ30 M4
SA_DQ[30] SB_DQ[30]

   t
M_A_DQ31 P9 M_B_DQ31 N5
M_A_DQ32  AH5 SA_DQ[31] M_B_DQ32  AF3 SB_DQ[31]
 AF5 SA_DQ[32]  AG1 SB_DQ[32]

  a
M_A_DQ33 M_B_DQ33
 AK6 SA_DQ[33] C9 M_A
_DQS#[7:0] 10  AJ3 SB_DQ[33] D5 M
_B_DQS
#[7:0] 11
M_A_DQ34 M_A_DQS#0 M_B_DQ34 M_B_DQS#0
 AK7 SA_DQ[34] SA_DQ
S#[0] F8  AK1 SB_DQ[34] SB_DQS#[0] F4
M_A_DQ35 M_A_DQS#1 M_B_DQ35 M_B_DQS#1
M_A_DQ36  AF6 SA_DQ[35]    A SA_DQ
S#[1] J9 M_A_DQS#2 M_B_DQ36  AG4 SB_DQ[35] SB_DQS#[1] J4 M_B_DQS#2

  m M_A_DQ37  AG 5 SA_DQ[36] SA_DQ

S#[2] N9 M_A_DQS#3 M_B_DQ37  AG3 SB_DQ[36] SB_DQS#[2] L4 M_B_DQS#3
M_A_DQ38  AJ 7 SA_DQ[37]
   Y SA_DQ
S#[3]  AH7 M_A_DQS#4 M_B_DQ38  AJ4 SB_DQ[37] SB_DQS#[3]  AH2 M_B_DQS#4

  e    R
M_A_DQ39  AJ 6 SA_DQ[38] SA_DQ
S#[4]  AK9 M_A_DQS#5 M_B_DQ39  AH4 SB_DQ[38] SB_DQS#[4]  AL4 M_B_DQS#5
M_A_DQ40  AJ1 0 SA_DQ[39]
   O SA_DQ
S#[5]  AP11 M_A_DQS#6 M_B_DQ40  AK3 SB_DQ[39]    B SB_DQS#[5]  AR5 M_B_DQS#6

   h    M
M_A_DQ41  AJ 9 SA_DQ[40] SA_DQ
S#[6]  AT13 M_A_DQS#7 M_B_DQ41  AK4 SB_DQ[40] SB_DQS#[6]  AR8 M_B_DQS#7
M_A_DQ42  AL1 0 SA_DQ[41]
   E
SA_DQ
S#[7]
M_B_DQ42  A M6 SB_DQ[41]
  - SB_DQS#[7]

  c
M_A_DQ43  AK1 2 SA_DQ[42] M_B_DQ43  AN2 SB_DQ[42]
SA_DQ[43]    M SB_DQ[43]
M_A_DQ44  AK8 M_B_DQ44  AK5
   Y
   S
SA_DQ[44] SB_DQ[44]
M_A_DQ45  AL 7
   M M_A
_DQS[7:0] 10
M_B_DQ45  AK2
   R
 .
SA_DQ[45] SB_DQ[45]
M_A_DQ46  AK1
 AL
1
8 SA_DQ[46]    E SA_DQ
S[0]
C8
F9
M_A_DQS0 M_B_DQ46  AM4
 AM3 SB_DQ[46]    O
M_A_DQ47
M_A_DQ48  AN8 SA_DQ[47]    T SA_DQ
S[1] H9
M_A_DQS1
M_A_DQS2
M_B_DQ47
M_B_DQ48  AP3 SB_DQ[47]    M C5 M_B_DQS0
M
_B_DQS
[7: 0] 11

   B M_A_DQ49  AM1 0 SA_DQ[48]

   S SA_DQ
S[2] M9 M_A_DQS3 M_B_DQ49  AN5 SB_DQ[48]    E SB_DQS[0] E3 M_B_DQS1
M_A_DQ50  AR1 1 SA_DQ[49]
   Y SA_DQ
S[3]  AH8 M_A_DQS4 M_B_DQ50  AT4 SB_DQ[49]    M SB_DQS[1] H4 M_B_DQS2
SA_DQ[50] SA_DQ
S[4] SB_DQ[50] SB_DQS[2]
M_A_DQ51
M_A_DQ52
 AL1
 AM
1
9 SA_DQ[51]    S SA_DQ
S[5]
 AK10
 AN11
M_A_DQS5
M_A_DQS6
M_B_DQ51
M_B_DQ52
 AN6
 AN4 SB_DQ[51]    M SB_DQS[3]
M5
 AG2
M_B_DQS3
M_B_DQS4
M_A_DQ53  AN9 SA_DQ[52]
   R
SA_DQ
S[6]  AR13 M_A_DQS7 M_B_DQ53  AN3 SB_DQ[52]
   E SB_DQS[4]  AL
5 M_B_DQS5
M_A_DQ54  AT1 1 SA_DQ[53]
   D
SA_DQ
S[7] M_B_DQ54  AT5 SB_DQ[53]
   T SB_DQS[5]  AP5 M_B_DQS6
M_A_DQ55  AP1 2 SA_DQ[54]
SA_DQ[55]    D
M_B_DQ55  AT6 SB_DQ[54]
SB_DQ[55]    S SB_DQS[6]
SB_DQS[7]
 AR7 M_B_DQS7
M_A_DQ56
M_A_DQ57
 AM1
 AN1
2
2 SA_DQ[56]
M_B_DQ56
M_B_DQ57
 AN7
 AP6 SB_DQ[56]    Y
M_A_DQ58  AM1 3 SA_DQ[57] Y3 M_A_A0
M_A
_A[15:0] 10
M_B_DQ58  AP8 SB_DQ[57]    S
M_A_DQ59  AT1 4 SA_DQ[58] SA_MA[0] W1 M_A_A1 M_B_DQ59  AT9 SB_DQ[58]
M_A_DQ60  AT1 2 SA_DQ[59] SA_MA[1]  AA8 M_A_A2 M_B_DQ60  AT7 SB_DQ[59]    R
M_A_DQ61  AL1 3 SA_DQ[60] SA_MA[2]  AA3 M_A_A3 M_B_DQ61  AP9 SB_DQ[60]    D
M_A_DQ62  AR1 4 SA_DQ[61] SA_MA[3] V1 M_A_A4 M_B_DQ62  AR10 SB_DQ[61]    D M_
B_A[15:0] 1
1
M_A_DQ63  AP1 4 SA_DQ[62] SA_MA[4]  AA9 M_A_A5 M_B_DQ63  AT10 SB_DQ[62] U5 M_B_A0
SA_DQ[63] SA_MA[5] V8 SB_DQ[63] SB_MA[0] V2
M_A_A6 M_B_A1
SA_MA[6] T1 M_A_A7 SB_MA[1] T5 M_B_A2
SA_MA[7] Y9 M_A_A8 SB_MA[2] V3 M_B_A3
 AC3 SA_MA[8] U6 M_A_A9 SB_MA[3] R1 M_B_A4
10 M_A_BS0 SA_BS[0] SA_MA[9] SB_MA[4]
 AB2  AD4 M_A_A10  AB1 T8 M_B_A5
10 M_A_BS1 U7 SA_BS[1] SA_MA[10] T2 11 M_B_BS0 W5 SB_BS[0] SB_MA[5] R2
M_A_A11 M_B_A6
10 M_A_BS2 SA_BS[2] SA_MA[11] U3 11 M_B_BS1 R7 SB_BS[1] SB_MA[6] R6
M_A_A12 M_B_A7
SA_MA[12]  AG 8 11 M_B_BS2 SB_BS[2] SB_MA[7] R4
M_A_A13 M_B_A8
SA_MA[13] T3 M_A_A14 SB_MA[8] R5 M_B_A9
 AE1 SA_MA[14] V9 M_A_A15  AC5 SB_MA[9]  AB5 M_B_A10
10 M_A_CAS# SA_CAS# SA_MA[15] 11 M_B_CAS# SB_CAS# SB_MA[ 10]
 AB3 Y7 P3 M_B_A11
10 M_A_RAS# SA_RAS# 11 M_B_RAS# SB_RAS# SB_MA[ 11]
 AE9  AC6 R3 M_B_A12
10 M_A_WE# SA_WE# 11 M_B_WE# SB_WE# SB_MA[ 12]  AF7 M_B_A13
SB_MA[ 13] P5 M_B_A14
SB_MA[ 14] N1 M_B_A15
SB_MA[ 15]

PZ98927-3641-0 1F

PZ98927-3641-0 1F

B - 6 CPU 3/7 (DDR3)

 Schematic Diagrams

CPU 4/7 (Power)

PROCESSOR 4/7 ( POWER )
U 1 6F

PROCESSOR CORE POWER  PROCESSOR UNCORE POWER 

VC O RE 1 .1 V S_ V TT
48A   V TT TOTAL 2 1A 
AG 3 5 A H1 4
AG 3 4 V C C1 VT T 0 _ 1 A H1 2
ICCMAX Maximum Processor SV 48 V C C2 VT T 0 _ 2
AG 3 3 A H1 1 C29 C3 0 C 3 24 C3 5 C 33 C301 C334
AG 3 2 V C C3 VT T 0 _ 3 A H1 0
AG 3 1 V C C4 VT T 0 _ 4 J14 1 0 u _ 6. 3V _X5 R _ 0 6 *1 0 u _ 6. 3V _ X5 R _ 0 6 1 0 u _ 6. 3V _ X5 R _ 0 6 *1 0 u _ 6. 3V _ X5 R _ 0 6 *1 0 u _ 6 .3 V_ X5 R_ 0 6 2 2 u _ 6 .3V _ X5 R _ 0 8 2 2 u _ 6 .3 V_ X 5 R_ 0 8
V CO RE AG 3 0 V C C5 VT T 0 _ 5 J13
AG 2 9 V C C6 VT T 0 _ 6 H14
C3 2 3 C331 C335 C337 AG 2 8 V C C7 VT T 0 _ 7 H12
AG 2 7 V C C8 VT T 0 _ 8 G14
       8        8        8 V C C9 VT T 0 _ 9
       8
       0        0
       0
       0
AG 2 6 G13
_ _
_ _ AF35 V C C1 0 V TT 0 _ 1 0 G12
       R        R        R
       R       5 AF34 V C C1 1 V TT 0 _ 1 1 G11
      5       5       5
       X        X        X
       X
_ _ _ AF33 V C C1 2 V TT 0 _ 1 2 F 14
_
       V        V        V
C36 C303 C3 4 C3 2 8 ICCMAX_VTT Max Current
       V        3        3        3 AF32 V C C1 3 V TT 0 _ 1 3 F 13
       3
 .  .  .  .
       6
       6        6        6
AF31 V C C1 4 V TT 0 _ 1 4 F 12 1 0 u _ 6. 3V _X5 R _ 0 6 1 0 u _ 6 .3 V_ X5R _ 0 6 10 u _ 6 .3 V _ X5 R_ 0 6 *1 0 u _ 6 .3 V_ X 5R _ 0 6 for VTT Rail
_ _ _
_      u AF30 V C C1 5 V TT 0 _ 1 5 F 11
     u      u
     u        2
       2
       2
       2
       2
       2
       2
       2 AF29 V C C1 6 V TT 0 _ 1 6 E 14
SV 18

B 
       *
AF28 V C C1 7 V TT 0 _ 1 7 E 12
AF27 V C C1 8 V TT 0 _ 1 8 D14
AF26 V C C1 9 V TT 0 _ 1 9 D13

.
AD 3 5 V C C2 0 V TT 0 _ 2 0 D12
 R
 S 
C3 4 2 C352 C329 C318 AD 3 4 V C C2 1 V TT 0 _ 2 1 D11
AD 3 3 V C C2 2  E V TT 0 _ 2 2 C14
       8        8        8 AD 3 2 V C C2 3  W V TT 0 _ 2 3 C13

 c 
       8
       0
       0
_
       0        0
V C C2 4  O V TT 0 _ 2 4
 P
_ _ AD 3 1 C12
_
       R        R
       R        R V C C2 5 V TT 0 _ 2 5
      5       5       5 AD 3 0 C11
      5
 L The decoupling capacitors, filter
h 
       X        X
       X
       X _ _ AD 2 9 V C C2 6 V TT 0 _ 2 6 B 14
_
       V
_
       V V C C2 7  I V TT 0 _ 2 7
       V AD 2 8  A B 12 recommendations and sense resistors on the
Sheet 6 of 42
       V
       3        3        3        3
 .  .
 R
 . V C C2 8 V TT 0 _ 2 8

 e
 .        6        6 AD 2 7 A 14
       6        6
_
     u
_
     u
_
     u
_
AD 2 6 V C C2 9 V TT 0 _ 2 9 A 13 CPU/PCH Rails are specific to the CRB
 V
     u
       2        2        2        2 V C C3 0 V TT 0 _ 3 0
AC 3 5 A 12
       2        2        2
 1 Implementation. Customers need to follow the
m
       2
       *        *
V C C3 1 V TT 0 _ 3 1
 .
CPU 4/7
AC 3 4 A 11
AC 3 3 V C C3 2  1 V TT 0 _ 3 2 recommendations in the Calpella Platform 
AC 3 2 V C C3 3 1. 1V S_ V T T
V C C3 4 Design Guide

 a
AC 3 1

(Power)
AC 3 0 V C C3 5 AF10
C3 3 2 C356 C355 C354
V C C3 6 V TT 0 _ 3 3

 t  
AC 2 9 A E1 0
       8        8        8 AC 2 8 V C C3 7 V TT 0 _ 3 4 A C1 0
       8
       0        0        0        0
 C C304 C3 0 5 C3 1 2

i  
_
_ _ _ V C C3 8 V TT 0 _ 3 5
       R
AC 2 7 P A B1 0

 c 
       R        R        R
      5
      5
       X
      5
      5 AC 2 6 V C C3 9  U V TT 0 _ 3 6 Y10 2 2 u _ 6 .3 V_ X5R _ 0 8 22 u _ 6 .3 V_ X 5 R _ 0 8 2 2 u_ 6 .3 V_ X5 R _0 8
       X        X        X V C C4 0 V TT 0 _ 3 7
_ A A3 5 W 10
_ _ _
       V
       V
       3
       V        V A A3 4 V C C4 1  C V TT 0 _ 3 8 U10
       3  .        3        3  O
 .
       6
 .  .
A A3 3 V C C4 2
R
V TT 0 _ 3 9 T10 1.1VS_VTT
D
       6        6        6
_
_ _ _
     u
     u
       2
     u
       2
     u
       2
A A3 2 V C C4 3 E V TT 0 _ 4 0 J12
       2
       2        2        2        2 A A3 1 V C C4 4 V TT 0 _ 4 1 J11
       *        *
A A3 0 V C C4 5  S V TT 0 _ 4 2 J16
Please note that the

i  
V C C4 6  U V TT 0 _ 4 3
+ VT T_ 4 3 R 216 * 15 m li _ s h o rt_ 0 6
A A2 9 P J15 + VT T_ 4 4  VTT Rail Values are
 a
R 215 * 15 m li _ s h o rt_ 0 6
A A2 8 V C C4 7 P V TT 0 _ 4 4
A A2 7 V C C4 8 L
Y

 g
A A2 6 V C C4 9
V C C5 0
 Auburndale VTT=1.05V 
Y3 5
V C C5 1

r 
Y3 4
Y3 3 V C C5 2 1 .1 V S_ VT T

 a
V CO RE Y3 2 V C C5 3
V C C5 4
Y3 1 1K PU to VTT and 1K P D to GND

m
Y3 0 V C C5 5
C3 4 8 C346 C345 C344 Y2 9 V C C5 6 for POC R 2 25
Y2 8 V C C5 7
       6 V C C5 8
       6
       0
       6        6 Y2 7 VCORE * 1 K_ 1% _ 0 4

 s 
       0 _        0        0
_ _ _ Y2 6 V C C5 9
       R        R        R        R
      5
      5
      5       5 V3 5 V C C6 0 A N3 3 PSI #
       X
       X
_
       X        X V C C6 1 P SI# P SI # 36
_ _ _ V3 4
       V        V        V V C C6 2
       V V3 3 1 .1 V S_ VT T
       3        3        3        3
 .  .  .
 . V3 2 V C C6 3 A K3 5
       6        6_        6        6 R 2 26

     R
_      u _ _ V C C6 4 VID [0 ] H _V ID0 3 6
     u
       0
     u      u V3 1 A K3 3
       0        0        0 V C C6 5 VID [1 ] H _V ID1 3 6
       1 V3 0 A K3 4 1 K_ 1 % _ 0 4
       1        1        1

     E
       *        * H _V ID2 3 6
V2 9 V C C6 6 VID [2 ] A L3 5 R2 2 3
V2 8 V C C6 7 VID [3 ] A L3 3 H _V ID3 3 6
V2 7
V2 6
V
V
C C6 8
C C6 9      W D
 S
 I
VID [4 ]
VID [5 ]
A
A
M3 3
M3 5
H
H
_V
_V
ID4
ID5
3
3
6
6
1 K_ 1 % _0 4

C3 2 6 C325 C327 C347 U35

U34
V
V
C C7 0
C C7 1      O V VID [6 ]
PR O C_ D PR S L PVR
A M3 4 H _V ID6 3 6
PM _ DP RS LP V R 3 6
       6
       0
       6
       0
_
       6
       0
_
       6
       0
U33 V
V
C C7 2
C C7 3
     P U
 P
 C
_ _ U32 R2 2 2
       R        R        R
       R       5       5 U31 V C C7 4 G15
      5 H _ VT TV ID1
      5
       X        X        X V C C7 5 VT T _ SE L EC T
       X _ U30
_ _ *1 K_ 1 % _ 0 4
_        V        V        V
       V
       3        3        3 U29 V C C7 6
       3  .  .  .
 .
       6
       6
_
       6        6 U28 V C C7 7
_ _ V C C7 8
_      u      u      u U27
     u        0        0
       0
       0
       1
       1        1
       1 U26 V C C7 9
       *        *
R35 V C C8 0
R34 V C C8 1  TO V
CORE POW
ER CONT
ROL
R33 V C C8 2
R32 V C C8 3 A N3 5
V C C8 4 ISE NS E IM O N 36
C3 4 0 C339 C338 C333 R31
       4 R30 V C C8 5
       0
       4
       6 _        6 R29 V C C8 6
       0        0        R        0
_ V C C8 7
_       7 _ R28 A J3 4
       R        X        R
       R VC C _ S EN SE 3 6
      7
      5
       X        V
_       5
       X
R27 V C C8 8  S VC C_ SE NS E A J3 5
       X
_        0 _ R26 V C C8 9  E VSS_ SE NS E VS S _ SEN S E 36
 N
_
       V        V       5        V V C C9 0
       3 _        3 P3 5
       0  .
     u
 .
V C C9 1  I
 L
       1        6        6
_ _
       1
_
P3 4 B 15
     u      u
       0
 .      u P3 3 V C C9 2 V T T_SE NS E A 15 V T T_ S E N S E 3 4
       1
       0        0        0
 .
       0        1        1 P3 2 V C C9 3  E VSS _S E N SE_ V T T
P3 1 V C C9 4  S
V C C9 5  N
P3 0  E
P2 9 V
V
C C9 6
C C9 7
 S VCOR E 36
P2 8
V C C9 8 1 .1V S_ V T T 2 ,4 ,7 ,1 4 ,1 5 ,1 6,1 9 ,2 0 ,2 1 ,3 4 , 3 5 ,3 6
P2 7
P2 6 V C C9 9
V C C1 0 0

PZ 98 9 2 7 -3 6 4 1- 01 F

CPU 4/7 (Power) B - 7

 Schematic Diagrams

CPU 5/7 (Graphics Power)

PROCESSOR 5/7 ( GRAPHICS POWER )

VG F X_ CO RE U 1 6G

AT 2 1
AT 1 9 VAXG 1 AR2 2
AT 1 8 VAXG 2 VAXG _ SEN SE AT 2 2 GP UVC C SEN SE 3 5
C364 C 34 9 GP UVS SSEN SE 35
   9 AT 1 6 VAXG 3 VSSAXG _ SEN SE
 .
   5      E     S
    * 1 0 u _ 6. 3V _ X5 R _ 0 6 1 0 u _6 .3 V_ X5 R _0 6 AR 2 1 VAXG 4      S     E
   6
 . AR 1 9 VAXG 5      N     N
   6
    * VAXG 6      E     I
   6
AR 1 8      S     L
 . VAXG 7
   6
_
AR 1 6 AM2 2
A P2 1 VAXG 8 GF X_ VI D[0 ] AP2 2 DF GT _ VID _ 0 3 5
   V DF GT _ VID _ 1 3 5
   5 VAXG 9 GF X_ VI D[1 ]
 . A P1 9 AN2 2
 s
   2 DF GT _ VID _ 2 3 5
_ A P1 8 VAXG 10 GF X_ VI D[2 ] AP2 3
   u
 D DF GT _ VID _ 3 3 5

  s
   0 C 3 50 C3 6 2 A P1 6 VAXG 11 GF X_ VI D[3 ] AM2 3
   6
   5 + AN 2 1 VAXG 12
 G  I GF X_ VI D[4 ] AP2 4 DF GT _ VID _ 4 3 5
AN 1 9 VAXG 13  V GF X_ VI D[5 ] AN2 4
DF GT _ VID _ 5 3 5
2 2 u _ 6. 3V _X5 R _ 08 2 2 u_ 6 .3 V_ X5 R_ 0 8
VAXG 14 R GF X_ VI D[6 ] DF GT _ VID _ 6 3 5

  m
AN 1 8
   1 AN 1 6 VAXG 15 A  S
   7
   3 AM 2 1 VAXG 16 P  C AR2 5 1 .1 VS_ VT T

  a
    C
AM 1 9 VAXG 17 H  I G F X_ VR _E N AT 2 5 GF XVR _ D PRS LP VR R 36 1 * 1K _ 0 4
D F GT _VR _ EN 35
I
  r
AM 1 8 VAXG 18  H G F X_ DP RSL PV R AM2 4 T P_ GF X_ IM ON R 45 1 00 _ 1 % _ 0 4
AM 1 6 VAXG 19  C  P GF X_ IM O N GF X_ IM O N 3 5
 S  A
  g
AL 2 1 VAXG 20
AL 1 9 VAXG 21  R
 G
  a
AL 1 8 VAXG 22 1. 5V S_ CP U

   i Sheet 7 of 42 AL 1 6 VAXG 23

VAXG 24  VDDQ 6A 
A K2 1 AJ 1
A K1 9 VAXG 25 V DD Q1 AF 1

   D
VAXG 26 V DD Q2

CPU 5/7
A K1 8 AE7 C5 5 C3 3 6 C330 C6 1 C5 8
VAXG 27
 S
A K1 6 V DD Q3 AE4
AJ 2 1 VAXG 28
 L
V DD Q4 AC1

  c
1u _ 6 .3 V_ X5 R_ 0 4 2 2 u_ 6 .3 V_ X5 R_ 0 8 2 2 u _ 6. 3V _ X5 R _ 08 10 u _ 6 .3 V_ X5 R_ 0 6 1 0 u_ 6 .3 V_ X5 R_ 0 6
Please note that the AJ 1 9 VAXG 29 V DD Q5
 I
AB7

   i (Graphics Power) VAXG 30

 A
V DD Q6
 VTT Rail Values are AJ 1 8 AB4

   t
VAXG 31
 R
AJ 1 6 V DD Q7 Y1
AH 2 1 VAXG 32 V DD Q8 W7

  a AH 1 9 VAXG 33 V DD Q9
 V
W4
 Auburndale VTT=1.05V  VAXG 34 VDD Q1 0
Clarksfield VTT=1.1V 
AH 1 8
AH 1 6 VAXG 35
 5 U1 C3 4 1 C3 4 3 C39 C6 0 + C5 3
 .
VDD Q1 1 T7
     R
  m
VAXG 36 VDD Q1 2
 1
T4 1u _ 6 .3 V_ X5 R_ 0 4 1 u _6 .3 V_ X5 R _0 4 1 u _ 6 .3 V_ X5R _ 0 4 1u _ 6 .3 V_ X5 R_ 0 4 10 0 u _ 6 .3 V_ B_ A
VDD Q1 3
     E
P1

  e  -
VDD Q1 4 N7
VDD Q1 5
     W
N4

   h
VDD Q1 6 L1

     O  3
J24 VDD Q1 7 H1
F

  c
1 .1 VS_ VT T J23 VT T 1 _ 45 VDD Q1 8 1 .1 VS _V TT
D  R
     P
H25 VT T 1 _ 46 I
C3 1 4 C3 0 8  D
 D
   S
VT T 1 _ 47

 .
22 u _ 6 .3 V_ X5 R_ 0 8 22 u _ 6 .3 V_ X5 R_ 0 8
P1 0 C3 2 0 C6 4
VT T 0 _5 9 N1 0

   B
VT T 0 _6 0 L1 0 10 u _ 6 .3 V_ X5 R_ 0 6 1 0 u_ 6 .3 V_ X5 R_ 0 6
VT T 0 _6 1 K1 0
VT T 0 _6 2

1 .1 VS_ VT T

J2 2
K2 6
 V
VT T 1 _6 3 J2 0
1 .1 VS_ VT T J27 VT T 1 _ 48 VT T 1 _6 4
 1
J1 8 C3 1 5 C3 1 3
VT T 1 _ 49 P VT T 1 _6 5
J26
 .
C3 0 6 C3 0 7 E H2 1
VT T 1 _ 50
 1
J25  G VT T 1 _6 6 H2 0 22 u _ 6 .3 V_ X5 R_ 0 8 2 2 u_ 6 .3 V_ X5 R_ 0 8
22 u _ 6 .3 V_ X5 R_ 0 8 22 u _ 6 .3 V_ X5 R_ 0 8 H27 VT T 1 _ 51 VT T 1 _6 7 H1 9
1 .1 VS _V T T G28 VT T 1 _ 52  & VT T 1 _6 8
G27 VT T 1 _ 53
D
G26 VT T 1 _ 54 M 1 .8 VS
F26 VT T 1 _ 55 I
VT T 1 _ 56  VCCPLL 0.6A 
E2 6 L2 6
C3 0 9 C3 0 2 E2 5 VT T 1 _ 57 VC CP LL 1 L2 7
VT T 1 _ 58
 V
C3 9 6 C3 5 1 VC CP LL 2 M2 6 C4 1 C3 7 C38 C52 C56 C5 4
VC CP LL 3
0 .0 1u _ 5 0 V_ X7 R_ 0 4 0. 01 u _ 5 0 V_ X7R _ 0 4 22 u _ 6 .3 V_ X5 R_ 0 8 22 u _ 6 .3 V_ X5 R_ 0 8  8
 .
1u _ 6 .3 V_ X5 R_ 0 4 1 u _6 .3 V_ X5 R _0 4 2 .2 u _ 1 6V _ X5 R _ 06 4 .7 u _ 6 .3 V_ X5 R _ 0 6 1 0 u _ 6 .3V _ X5 R _ 0 6 10 u _ 6 .3 V_ X5 R_ 0 6
 1

PZ 98 9 2 7 -3 6 41-0 1 F

1 .5 VS _ CPU 4 ,3 1
1 . 8V S 2 0 , 33
V GF X_ C OR E 3 5
1 .1 VS _ VT T 2 ,4, 6, 14 ,1 5 ,1 6 ,1 9 ,2 0 ,21 ,3 4 ,3 5 ,3 6
1 .5 V 4 , 9 , 10 , 1 ,12 1 , 23 , 2 7, 2 9 , 31 , 33 , 3 6

B - 8 CPU 5/7 (Graphic s Power)

 Schematic Diagrams

CPU 6/7 (GND)

PROCESSOR 6/7 ( GND )

U16H U16I

 AT20  AE34
 AT17 VSS1 VSS81  AE33
 AR31 VSS2 VSS82  AE32 K27
 AR28 VSS3 VSS83  AE31 K9 VSS161
 AR26 VSS4 VSS84  AE30 K6 VSS162
 AR24 VSS5 VSS85  AE29 K3 VSS163
 AR23 VSS6 VSS86  AE28 J32 VSS164
 AR20 VSS7 VSS87  AE27 J30 VSS165
 AR17 VSS8 VSS88  AE26 J21 VSS166
 AR15 VSS9 VSS89  AE6 J19 VSS167
 AR12 VSS10 VSS90  AD10 H35 VSS168

B 
 AR9 VSS11 VSS91  AC8 H32 VSS169
 AR6 VSS12 VSS92  AC4 H28 VSS170
 AR3 VSS13 VSS93  AC2 H26 VSS171
 AP20
 AP17
 AP13
VSS14
VSS15
VSS16
VSS94
VSS95
VSS96
 AB35
 AB34
 AB33
H24
H22
H18
VSS172
VSS173
VSS174
.
 S 
 AP10
 AP7
VSS17
VSS18
VSS97
VSS98
 AB32
 AB31
H15
H13
VSS175
VSS176  c 
 AP4
 AP2
VSS19
VSS20
VSS99
VSS100
 AB30
 AB29
H11
H8
VSS177
VSS178 h 
 AN34 VSS21
VSS22
VSS101
VSS102
 AB28 H5 VSS179
VSS180  e
m
 AN31  AB27 H2
VSS23 VSS103 VSS181
 AN23
 AN20 VSS24
VSS25
VSS104
VSS105
 AB26
 AB6
G34
G31 VSS182
VSS183
Sheet 8 of 42
 a
 AN17  AA10 G20

CPU 6/7 (GND)

 AM29 VSS26 VSS106 Y8 G9 VSS184

 t  
 AM27 VSS27 VSS107 Y4 G6 VSS185
VSS28 VSS108 VSS186

i  
 AM25 Y2 G3

 c 
 AM20 VSS29 VSS109 W35 F30 VSS187
 AM17 VSS30 VSS110 W34 F27 VSS188
 AM14 VSS31 VSS111 W33 F25 VSS189

D
 AM11 VSS32 VSS112 W32 F22 VSS190
 AM8 VSS33 VSS113 W31 F19 VSS191
VSS34 VSS114 VSS192

i  
 AM5 W30 F16

 a
 AM2 VSS35 VSS115 W29 E35 VSS193
 AL34 VSS36 VSS116 W28 E32 VSS194
 AL31
 AL23
VSS37
VSS38  V SS VSS117
VSS118
W27
W26
E29
E24
VSS195
VSS196  VS S  g
r 
 AL20 VSS39 VSS119 W6 E21 VSS197
VSS40 VSS120 VSS198

 a
 AL17 V10 E18
 AL12 VSS41 VSS121 U8 E13 VSS199

m
 AL9 VSS42 VSS122 U4 E11 VSS200
 AL6 VSS43 VSS123 U2 E8 VSS201
 AL3 VSS44 VSS124 T35 E5 VSS202

 s 
 AK29 VSS45 VSS125 T34 E2 VSS203  AT35
 AK27 VSS46 VSS126 T33 D33 VSS204 VSS_NC TF1  AT1
 AK25 VSS47 VSS127 T32 D30 VSS205 VSS_NC TF2  AR34
 AK20 VSS48 VSS128 T31 D26 VSS206 VSS_NC TF3 B34
 AK17 VSS49 VSS129 T30 D9 VSS207 VSS_NC TF4 B2
 AJ31 VSS50 VSS130 T29 D6 VSS208 VSS_NC TF5 B1
VSS51 VSS131 VSS209     F VSS_NC TF6
 AJ23 T28 D3     T  A35
 AJ20 VSS52 VSS132 T27 C34 VSS210     C VSS_NC TF7
 AJ17 VSS53 VSS133 T26 C32 VSS211     N
 AJ14 VSS54 VSS134 T6 C29 VSS212
 AJ11 VSS55 VSS135 R10 C28 VSS213
 AJ8 VSS56 VSS136 P8 C24 VSS214
 AJ5 VSS57 VSS137 P4 C22 VSS215
 AJ2 VSS58 VSS138 P2 C20 VSS216
 AH35 VSS59 VSS139 N35 C19 VSS217
 AH34 VSS60 VSS140 N34 C16 VSS218
 AH33 VSS61 VSS141 N33 B31 VSS219
 AH32 VSS62 VSS142 N32 B25 VSS220
 AH31 VSS63 VSS143 N31 B21 VSS221
 AH30 VSS64 VSS144 N30 B18 VSS222
 AH29 VSS65 VSS145 N29 B17 VSS223
 AH28 VSS66 VSS146 N28 B13 VSS224
 AH27 VSS67 VSS147 N27 B11 VSS225
 AH26 VSS68 VSS148 N26 B8 VSS226
 AH20 VSS69 VSS149 N6 B6 VSS227
 AH17 VSS70 VSS150 M1 0 B4 VSS228
 AH13 VSS71 VSS151 L35  A29 VSS229
 AH9 VSS72 VSS152 L32  A27 VSS230
 AH6 VSS73 VSS153 L29  A23 VSS231
 AH3 VSS74 VSS154 L8  A9 VSS232
 AG10 VSS75 VSS155 L5 VSS233
 AF8 VSS76 VSS156 L2
 AF4 VSS77 VSS157 K34
 AF2 VSS78 VSS158 K33
 AE35 VSS79 VSS159 K30
VSS80 VSS160

PZ98927-3641-01F PZ98927-3641-01F

CPU 6/7 (GND) B - 9

 Schematic Diagrams

CPU 7/7 (RESERVED)

PROCESSOR 7/7 ( RESERVED )

1 .5 V

U1 6 E
AP2302GN
A J1 3 R36
RS V D3 2 A J1 2
RS V D3 3
PCI- Express Configurat i on Sel ect A P2 5
Q8 * 1 K_ 1% _ 0 4
*A O3 4 0 2L
A L2 5 R S VD 1 A H2 5 V R E F _ CH _ A_ DIM M S D MV R EF _ D Q_ DIM 0
A L2 4 R S VD 2 RS V D3 4 A K 26
CFG0 1 : Single PEG A L2 2 R S VD 3 RS V D3 5
0 : Bif urcati on enable A J3 3 R S VD 4 A L2 6 R 2 12
    G
R37
A G9 R S VD 5 RS V D3 6 AR 2 * 1 00 K _ 1 % _ 0 4
M2 7 R S VD 6 R SV D _ NC TF _3 7
* 1 K_ 1% _ 0 4
L2 8 R S VD 7 A J2 6
J1 7 R S VD 8 RS V D3 8 A J2 7 DR A MR ST _ CT R L 4,1 9

  s
CFG0 R 22 7 * 3. 0 1K _ 04 R 35 *0 _ 04 VR EF _ C H_ A _ DI MM
1 0 MVR EF _ D Q_ DI M0 VR EF _ C H_ B _ DI MM H1 7 R S VD 9 RS V D3 9
1 1 MVR EF _ D Q_ DI M1 R 39 *0 _ 04
G2 5 R S VD 1 0 ? ? IBEXCONTROL
G1 7 R S VD 1 1

  m
R S VD 1 2
CFG3 - PCI - Express Stat i c Lane Reversal E3 1
E3 0 R S VD 1 3 R SV D _ NC TF _4 0
AP1
A T2

  a
R S VD 1 4 R SV D _ NC TF _4 1 1 .5 V
1 : Normal Operati on
CFG3 A T3

  r 0 : Lane Numbers Revers ed R SV D _ NC TF _4 2 AR 1

R SV D _ NC TF _4 3

  g Sheet 9 of 42 15 - > 0 , 14 - > 1 , . . . AP23 02GN R38

  a
A L2 8 Q9 * 1 K_ 1% _ 0 4

   i CPU 7/7 CFG3 R 22 1 * 3. 0 1K _ 04 C F G0 A M3 0

A M2 8
A P3 1
C F G [0]
C F G [1]
RS V D4 5
RS V D4 6
RS V D4 7
A L2 9
A P 30
A P 32
V R E F _ CH _ B _ DI M M S
*A O3 4 0 2L
D MV R E F _ D Q_ D I M 1

   D
A L3 2 C F G [2] RS V D4 8 A L2 7

(RESERVED) CFG4 - Di spl ay Port Pres ence

C F G3
C F G4 A L3 0
A M3 1
C F G [3]
C F G [4]
RS V D4 9
RS V D5 0
A T3 1
A T3 2
R 2 14
* 1 00 K _ 1 % _ 0 4    G
R40

  c
A N2 9 C F G [5] RS V D5 1 A P 33 * 1 K_ 1% _ 0 4

   i
C F G7 A M3 2 C F G [6] RS V D5 2 A R3 3
1 : Disablled; No physi cal Display Port DR A MR ST _ CT R L 4,1 9

   t
A K3 2 C F G [7] RS V D5 3 A T3 3
  attached to Embedded Displ ay Port A K3 1 C F G [8] R SV D _ NC TF _5 4 A T3 4
C F G [9] R SV D _ NC TF _5 5 ? ? IBEXCONTROL

  a CFG4 A K2 8 A P 35
0 : Enabled; An external Dis pl ay Port
A J2 8 C F G [10 ]    D R SV D _ NC TF _5 6 A R3 5
A N3 0 C F G [11 ]    E R SV D _ NC TF _5 7 A R3 2
devi ce i s connected to the Em
bedded A N3 2 C F G [12 ]    V RS V D5 8

  m    R
A J3 2 C F G [13 ]
ispl ay Port
A J2 9 C F G [14 ]
   E E 15

  e    S
A J3 0 C F G [15 ] R S VD _ TP _5 9 F 15
C F G [16 ] R S VD _ TP _6 0
A K3 0
   E A2

   h
C F G [17 ] K EY
CFG4 R 22 0 * 3. 0 1K _ 04 R 211 *0 _ 0 4 R SVD8 6 H1 6
R S VD _ TP _8 6    R RS V D6 2
D15
C15
RS V D6 3

  c
RSVD86 A J1 5 RSV D 6 4 _R R 2 17 * 15 m i _l s h o rt _ 06
Connect t o GND RS V D6 4 A H1 5 RSV D 6 5 _R R 2 18 * 15 m i _l s h o rt _ 06
RS V D6 5

   S
B1 9

 .
A1 9 R S VD 15
R S VD 1 6
CFG7 R 22 4 * 3. 0 1K _ 04
R 20 5 * 15 m li_ s h ort _0 6 H _R S VD 1 7_ R A2 0

   B
B2 0 R S VD 1 7
CFG7 R 20 4 * 15 m li_ s h ort _0 6 H _R S VD 1 8_ R
R S VD 1 8 AA5
Cl arksfi eld (onl y f or early samples U9 R S VD _ TP _6 6 AA4
T9 R S VD 19 R S VD _ TP _6 7 R8
pre- ES1) - Connect to GND wit h 3.01K Ohm/ 5% R S VD 2 0 R S VD _ TP _6 8 AD 3
AC 9 R S VD _ TP _6 9 AD 2
r e si s t or AB 9 R S VD 21 R S VD _ TP _7 0 AA2
R S VD 2 2 R S VD _ TP _7 1 AA1
R S VD _ TP _7 2 R9
R S VD _ TP _7 3 A G7
C1 R S VD _ TP _7 4 AE3
A3 R S VD _ NC TF _2 3 R S VD _ TP _7 5
R S VD _ NC TF _2 4
V4
R S VD _ TP _7 6 V5
R S VD _ TP _7 7 N2
J2 9 R S VD _ TP _7 8 AD 5
J2 8 R S VD 26 R S VD _ TP _7 9 AD 7
R S VD 2 7 R S VD _ TP _8 0 W 3
A3 4 R S VD _ TP _8 1 W 2
A3 3 R S VD _ NC TF _2 8 R S VD _ TP _8 2 N3
R S VD _ NC TF _2 9 R S VD _ TP _8 3 AE5
C3 5 R S VD _ TP _8 4 AD 9
B3 5 R S VD _ NC TF _3 0 R S VD _ TP _8 5
R S VD _ NC TF _3 1
A P 34 TP _R S VD 8 6
VSS  VSS (AP34) can be left NC is
CRB implementation ; EDS/DG
recommendation to GND
PZ 9 89 2 7 -3 6 41 -0 1 F

1.5 V 4 ,1 0, 11 ,21 ,2 3,2 7,29 ,3 1,3 3, 36

B - 10 CPU 7/7 (RESERVED)

 Schematic Diagrams

DDR3 SO-DIMM_0

SO-DIMM A  CHANGE TO STANDARD

J DIM M2 A
5 M_ A_ A[1 5 :0 ] M _A_ A0 98 5 M _A _D Q0 M_ A_ DQ [6 3:0] 5
J DIM M2 B
M _A_ A1 97 A0 DQ 0 7 M _A _D Q1
M _A_ A2 96 A1 DQ 1 15 M _A _D Q2
M _A_ A3 95 A2 DQ 2 17 M _A _D Q3 1 .5V
M _A_ A4 92 A3 DQ 3 4 M _A _D Q4
M _A_ A5 91 A4 DQ 4 6 M _A _D Q5 75 44
M _A_ A6 90 A5 DQ 5 16 M _A _D Q6 76 VDD 1 VS S1 6 48
M _A_ A7 86 A6 DQ 6 18 M _A _D Q7 81 VDD 2 VS S1 7 49
M _A_ A8 89 A7 DQ 7 21 M _A _D Q8 82 VDD 3 VS S1 8 54
Layout Note: M _A_ A9 85 A8 DQ 8 23 M _A _D Q9 87 VDD 4 VS S1 9 55
M _A_ A1 0 107 A9 DQ 9 33 M _A _D Q1 0 88 VDD 5 VS S2 0 60
signal/space/signa l: M _A_ A1 1 84 A1 0 /AP D Q1 0 35 M _A _D Q1 1 93 VDD 6 VS S2 1 61
M _A_ A1 2 83 A1 1 D Q1 1 22 M _A _D Q1 2 94 VDD 7 VS S2 2 65
8 / 4/ 8 M _A_ A1 3 119 A1 2 /BC# D Q1 2 24 M _A _D Q1 3 3 .3 VS 99 VDD 8 VS S2 3 66

B 
M _A_ A1 4 80 A1 3 D Q1 3 34 M _A _D Q1 4 1 00 VDD 9 VS S2 4 71
M _A_ A1 5 78 A1 4 D Q1 4 36 M _A _D Q1 5 20mils 1 05 VDD 10 VS S2 5 72
A1 5 D Q1 5 39 1 06 VDD 11 VS S2 6 12 7

.
M _A _D Q1 6
109 D Q1 6 41 M _A _D Q1 7 1 11 VDD 12 VS S2 7 12 8

 S 
5 M_ A_ BS0 C96 C9 7
108 BA0 D Q1 7 51 M _A _D Q1 8 1 12 VDD 13 VS S2 8 13 3
5 M_ A_ BS1 79 BA1 D Q1 8 53 M _A _D Q1 9 1 17 VDD 14 VS S2 9 13 4
1 u _ 6 .3V _X5 R_ 0 4 0.1 u _ 1 0V _X7 R_ 0 4

 c 
5 M_ A_ BS2 114 BA2 D Q1 9 40 M _A _D Q2 0 1 18 VDD 15 VS S3 0 13 8
5 M_ C S# 0 121 S0 # D Q2 0 42 1 23 VDD 16 VS S3 1 13 9
M _A _D Q2 1
5 M_ C S# 1 S1 # D Q2 1 VDD 17 VS S3 2

h 
101 50 M _A _D Q2 2 1 24 14 4
5 M _ CL K_ DD R0 103 CK 0 D Q2 2 52 VDD 18 VS S3 3 14 5
M _A _D Q2 3
5
5
5
M
M
M
_ CL K_ DD R# 0
_ CL K_ DD R1
_ CL K_ DD R# 1
102
104
73
CK 0#
CK 1
CK 1#
D Q2 3
D Q2 4
D Q2 5
57
59
67
M
M
M
_A _D Q2 4
_A _D Q2 5
_A _D Q2 6 3 .3 VS
1 99

77
VDD SPD
VS
VS
VS
S3
S3
S3
4
5
6
15 0
15 1
15 5
Sheet 10 of 42  e
m
5 M_ C KE0 CK E0 D Q2 6 NC 1 VS S3 7

DDR3 SO-DIMM_0
74 69 M _A _D Q2 7 1 22 15 6
5 M_ C KE1 115 CK E1 D Q2 7 56 1 25 NC 2 VS S3 8 16 1
M _A _D Q2 8 R 72 1 0 K _ 1% _ 0 4
5 M _A _C AS# 110 CA S# D Q2 8 58 M _A _D Q2 9 NC TE ST VS S3 9 16 2
5 M _A _R AS#

 a
113 RA S# D Q2 9 68 M _A _D Q3 0 1 98 VS S4 0 16 7
5 M _A _W E# SA0 _ DIM 0 197 W E# D Q3 0 70 M _A _D Q3 1 4,1 1 T S# _ DIM M0 _ 1 30 E V E N T# VS S4 1 16 8
SA0 D Q3 1 4,1 1 D DR 3_ D RAM RS T# RESE T# VS S4 2

 t  
SA1 _ DIM 0 201 129 M _A _D Q3 2 17 2
202 SA1 D Q3 2 131 20mils VS S4 3 17 3

i  
2 ,1 1 C L K_ SCL K M _A _D Q3 3 C 1 8 2 . 2u _6 . 3 V _ X 5R _ 06
200 SC L D Q3 3 141 M _A _D Q3 4 1 VS S4 4 17 8

 c 
2,1 1 C LK _S DAT A C 1 9 0 . 1u _1 0V _ X 7R _ 04
SD A D Q3 4 143 M _A _D Q3 5 1 26 VREF _D Q VS S4 5 17 9
3 .3 VS 116 D Q3 5 130 M _A _D Q3 6 VREF _C A VS S4 6 18 4
5 M_ O DT 0 120 OD T 0 D Q3 6 132 M _A _D Q3 7 R2 0 *0 _ 0 4 R19 * 15 m il _ sh o r t _ 0 6 VS S4 7 18 5

D
5 M_ O DT 1 OD T 1 D Q3 7 140 9 M VR EF _ DQ _D IM 0 2 VS S4 8 18 9
M _A _D Q3 8
5 M_ A_ D M[7 :0 ] M _A_ D M0 11 D Q3 8 142 M _A _D Q3 9 M VREF _D IM0 3 VSS1 VS S4 9 19 0
RN 3
28 DM 0 D Q3 9 147 8 VSS2 VS S5 0 19 5

i  
1 0 K_ 8 P4R _ 0 4 M _A_ D M1 M _A _D Q4 0 C8 2 2 . 2u _6 . 3V _ X5 R _ 06
1 8 SA1 _ DIM 1 M _A_ D M2 46 DM 1 D Q4 0 149 M _A _D Q4 1 9 VSS3 VS S5 1 19 6

 a
SA1 _D IM 1 1 1 C8 1 0 . 1u _1 0V _ X7 R _ 04
2 7 SA0 _ DIM 1 M _A_ D M3 63 DM 2 D Q4 1 157 M _A _D Q4 2 13 VSS4 VS S5 2
3 6 SA0 _D IM 1 1 1 136 DM 3 D Q4 2 159 14 VSS5
SA1 _ DIM 0 M _A_ D M4 M _A _D Q4 3

 g
4 5 SA0 _ DIM 0 M _A_ D M5 153 DM 4 D Q4 3 146 M _A _D Q4 4 19 VSS6
M _A_ D M6 170 DM 5 D Q4 4 148 M _A _D Q4 5 20 VSS7 VTT _ M EM

r 
M _A_ D M7 187 DM 6 D Q4 5 158 M _A _D Q4 6 25 VSS8
DM 7 D Q4 6 160 M _A _D Q4 7 26 VSS9 20 3

 a
5 M_ A_ D QS[7 :0 ] M _A_ D QS0 12 D Q4 7 163 M _A _D Q4 8 31 VSS1 0 VT T 1 20 4
M _A_ D QS1 29 DQ S0 D Q4 8 165 M _A _D Q4 9 32 VSS1 1 VT T 2

m
M _A_ D QS2 47 DQ S1 D Q4 9 175 M _A _D Q5 0 37 VSS1 2 GN D1
M _A_ D QS3 64 DQ S2 D Q5 0 177 M _A _D Q5 1 38 VSS1 3 G1 GN D2
M _A_ D QS4 137 DQ S3 D Q5 1 164 M _A _D Q5 2 43 VSS1 4 G2

 s 
M _A_ D QS5 154 DQ S4 D Q5 2 166 M _A _D Q5 3 VSS1 5
M _A_ D QS6 171 DQ S5 D Q5 3 174 M _A _D Q5 4 AS0 A6 2 1-U 2 SN- 7 F
188 DQ S6 D Q5 4 176
M _A_ D QS7 M _A _D Q5 5
DQ S7 D Q5 5 181 M _A _D Q5 6
5 M_ A_ D QS# [7 : 0 ] 10 D Q5 6 183
M _A_ D QS# 0 M _A _D Q5 7
M _A_ D QS# 1 27 DQ S0 # D Q5 7 191 M _A _D Q5 8
M _A_ D QS# 2 45 DQ S1 # D Q5 8 193 M _A _D Q5 9
M _A_ D QS# 3 62 DQ S2 # D Q5 9 180 M _A _D Q6 0
M _A_ D QS# 4 135 DQ S3 # D Q6 0 182 M _A _D Q6 1
M _A_ D QS# 5 152 DQ S4 # D Q6 1 192 M _A _D Q6 2
M _A_ D QS# 6 169 DQ S5 # D Q6 2 194 M _A _D Q6 3
M _A_ D QS# 7 186 DQ S6 # D Q6 3
DQ S7 # CLOSE TO SO-DIMM_0
1 .5 V AS0 A6 2 1 -U2 SN -7 F

R 63 1K _1 % _ 0 4 M VR EF _ DIM 0
1.5 V
C3 5 3 +  C 3 2 1 C57 C6 2 C7 8 C 47 C68 C70 +   C 3 16
+
5 60 u _ 2 .5V _6 .6 * 6.6 * 5.9 R65 C8 6
*2 2 0 u_ 2 .5 V_ B_ A 1 0 u _ 6.3 V_ X5 R_ 0 6 10 u _ 6 .3V _X5 R_ 0 6 *1 0 u _6 .3 V_ X5 R_ 0 6 1 u _6 .3 V_ X5 R_ 0 4 1 u _ 6. 3V_ X5 R_ 0 4 * 1 u_ 6 .3 V_ X5R _ 0 4 * 5 60 u _ 2. 5V_ 6 .6 *6 .6 *5 .9
1 K_ 1 % _0 4 0 .1 u_ 1 0 V _ X7 R _ 04

1.5 V

C7 3 C4 8 C 44 C67 C4 6 C7 5 C 43
4 ,9 ,1 1, 21 ,2 3 , 2 7,2 9 ,3 1 ,3 3,3 6 1 .5 V
1 1,3 3 VT T _ MEM
0 .1u _ 1 0 V _ X7 R _0 4 0 .1 u_ 1 0 V_ X7R _ 04 * 0.1 u _ 1 0V _X7 R_ 0 4 0 .1 u _ 10 V_ X7 R_ 0 4 0.1 u _ 1 0V _X7 R_ 0 4 0 .1u _ 1 0 V _ X7 R _0 4 *0 .1 u _ 1 0V_ X7 R_ 0 4
2 ,1 1,1 2 ,1 3 ,14 ,1 5 ,1 6 , 17 ,1 8 ,1 9 ,20 ,2 1 ,2 3 ,24 ,2 5 , 2 6, 27 ,2 8 ,2 9,3 0 ,3 1 , 3 5,3 63 .3 VS

VT T _M EM

C1 0 1 C1 0 5 C 10 4 C106

1 0u _ 6 .3 V _ X5 R _0 6 *1 u _ 6 .3V _X5 R_ 0 4 1 u _ 6.3 V_ X5 R_ 0 4 1 u _ 6 .3V _X5 R_ 0 4

DDR3 SO-DIMM_0 B - 11
 Schematic Diagrams

DDR3 SO-DIMM_1
SO-DIMM B CHANGE TO STANDARD

J DIM M1 A
5 M_ B_ A[1 5 :0] M _B _A 0 98 5 M_ B_ DQ 0 M_ B _ D Q[ 6 3 : 0 ] 5 J DIM M1 B
97 A0 DQ 0 7
M _B _A 1 M_ B_ DQ 1
M _B _A 2 96 A1 DQ 1 15 M_ B_ DQ 2 1 .5V
M _B _A 3 95 A2 DQ 2 17 M_ B_ DQ 3
M _B _A 4 92 A3 DQ 3 4 M_ B_ DQ 4
M _B _A 5 91 A4 DQ 4 6 M_ B_ DQ 5 75 44
M _B _A 6 90 A5 DQ 5 16 M_ B_ DQ 6 76 VD D1 VSS1 6 48
M _B _A 7 86 A6 DQ 6 18 M_ B_ DQ 7 81 VD D2 VSS1 7 49
M _B _A 8 89 A7 DQ 7 21 M_ B_ DQ 8 82 VD D3 VSS1 8 54
L a y o u t N o t e: M _B _A 9 85 A8 DQ 8 23 M_ B_ DQ 9 87 VD D4 VSS1 9 55
M _B _A 10 107 A9 DQ 9 33 M_ B_ DQ 1 0 88 VD D5 VSS2 0 60
signal/spac e/signal: M _B _A 11 84 A1 0 /AP DQ 1 0 35 M_ B_ DQ 1 1 93 VD D6 VSS2 1 61
M _B _A 12 83 A1 1 DQ 1 1 22 M_ B_ DQ 1 2 94 VD D7 VSS2 2 65
8/4/8 M _B _A 13 119 A1 2 /BC# DQ 1 2 24 M_ B_ DQ 1 3 99 VD D8 VSS2 3 66
M _B _A 14 80 A1 3 DQ 1 3 34 M_ B_ DQ 1 4 100 VD D9 VSS2 4 71
M _B _A 15 78 A1 4 DQ 1 4 36 M_ B_ DQ 1 5 105 VD D1 0 VSS2 5 72
A1 5 DQ 1 5 39 M_ B_ DQ 1 6 106 VD D1 1 VSS2 6 1 27
109 DQ 1 6 41 M_ B_ DQ 1 7 111 VD D1 2 VSS2 7 1 28
5 M _ B_ BS0 108 BA0 DQ 1 7 51 M_ B_ DQ 1 8 112 VD D1 3 VSS2 8 1 33
5 M _ B_ BS1 79 BA1 DQ 1 8 53 117 VD D1 4 VSS2 9 1 34
M_ B_ DQ 1 9
5 M _ B_ BS2 114 BA2 DQ 1 9 40 M_ B_ DQ 2 0 118 VD D15 VSS3 0 1 38
5 M _ CS# 2

  s
121 S0 # DQ 2 0 42 M_ B_ DQ 2 1 123 VD D1 6 VSS3 1 1 39
5 M _ CS# 3 101 S1 # DQ 2 1 50 M_ B_ DQ 2 2 124 VD D1 7 VSS3 2 1 44
3.3 VS
5 M_ C LK_ D DR 2 103 CK 0 DQ 2 2 52 M_ B_ DQ 2 3 VD D1 8 VSS3 3 1 45
5 M_ C LK_ D DR # 2 102 CK 0# DQ 2 3 57 20mils 199 VSS3 4 1 50

  m
M_ B_ DQ 2 4
5 M_ C LK_ D DR 3 104 CK 1 DQ 2 4 59 M_ B_ DQ 2 5 VD DSPD VSS3 5 1 51
5 M_ C LK_ D DR # 3 73 CK 1# DQ 2 5 67 77 VSS3 6 1 55

  a
M_ B_ DQ 2 6 C9 8 C99
5 M _ CKE2 74 CK E0 DQ 2 6 69 M_ B_ DQ 2 7 122 NC 1 VSS3 7 1 56

  r
5 M _ CKE3 CK E1 DQ 2 7 NC 2 VSS3 8
115 56 M_ B_ DQ 2 8 1 u_ 6 .3 V_ X5 R _0 4 0 .1 u _ 10 V_ X7 R_ 0 4 125 1 61
5 M_ B_ CAS # 110 CA S# DQ 2 8 58 M_ B_ DQ 2 9 NC T EST VSS3 9 1 62

  g Sheet 11 of 42 5
5
M_ B_ RAS #
M_ B_ W E#
10 SA0 _D IM 1
SA0 _ D IM1
113
197
RA S#
W E#
SA0
DQ 2 9
DQ 3 0
DQ 3 1
68
70
M_ B_ DQ 3 0
M_ B_ DQ 3 1
4 ,1 0 TS# _ DI MM 0_ 1
4 ,1 0 DDR 3 _ DR AMR ST #
198
30 EVEN T #
RE SET #
VSS4
VSS4
VSS4
0
1
2
1 67
1 68

  a
SA1 _ D IM1 201 1 29 M_ B_ DQ 3 2 1 72
10 SA1 _D IM 1

   i DDR3 SO-DIMM_1

202 SA1 DQ 3 2 1 31 M_ B_ DQ 3 3 C2 2 2 . 2u _6 . 3V _ X5 R _ 06 VSS4 3 1 73
2,1 0 CL K_ SC LK 200 SC L DQ 3 3 1 41 M_ B_ DQ 3 4 1 VSS4 4 1 78
2 ,1 0 CL K_ SDA TA C2 3 0 . u1 _ 10 V _ X 7 R _0 4
SD A DQ 3 4 1 43 M_ B_ DQ 3 5 126 VR EF _ DQ VSS4 5 1 79

   D
116 DQ 3 5 1 30 M_ B_ DQ 3 6 VR EF _ CA VSS4 6 1 84
5 M _ OD T2 120 OD T 0 DQ 3 6 1 32 M_ B_ DQ 3 7 R23 * 0_ 0 4 R 22 *1 5 m li_ s h ort_ 0 6 VSS4 7 1 85
5 M _ OD T3 OD T 1 DQ 3 7 1 40 9 M VREF _D Q_ D IM1 2 VSS4 8 1 89
M_ B_ DQ 3 8

  c
5 M _B _D M[7 :0 ] M _B _D M0 11 DQ 3 8 1 42 M_ B_ DQ 3 9 MV REF _ D IM1 3 VSS1 VSS4 9 1 90

   i
M _B _D M1 28 DM 0 DQ 3 9 1 47 M_ B_ DQ 4 0 C8 4 2 . 2u _6 . 3V _ X5 R _ 06 8 VSS2 VSS5 0 1 95
DM 1 DQ 4 0 VSS3 VSS5 1

   t
M _B _D M2 46 1 49 M_ B_ DQ 4 1 C8 3 0 . u1 _ 10 V _ X 7 R _0 4 9 1 96
M _B _D M3 63 DM 2 DQ 4 1 1 57 M_ B_ DQ 4 2 13 VSS4 VSS5 2
DM 3 DQ 4 2 VSS5

  a
M _B _D M4 136 1 59 M_ B_ DQ 4 3 2010/01/08 14
M _B _D M5 153 DM 4 DQ 4 3 1 46 M_ B_ DQ 4 4 19 VSS6
M _B _D M6 170 DM 5 DQ 4 4 1 48 M_ B_ DQ 4 5 20 VSS7 VT T_ M EM
M _B _D M7 187 DM 6 DQ 4 5 1 58 M_ B_ DQ 4 6 25 VSS8

  m
DM 7 DQ 4 6 1 60 M_ B_ DQ 4 7 26 VSS9 2 03
5 M _B _D QS [7:0 ] M _B _D QS 0 12 DQ 4 7 1 63 M_ B_ DQ 4 8 31 VSS1 0 VT T 1 2 04

  e
M _B _D QS 1 29 DQ S0 DQ 4 8 1 65 M_ B_ DQ 4 9 32 VSS1 1 VT T 2
M _B _D QS 2 47 DQ S1 DQ 4 9 1 75 M_ B_ DQ 5 0 37 VSS1 2 GN D1

   h
M _B _D QS 3 64 DQ S2 DQ 5 0 1 77 M_ B_ DQ 5 1 38 VSS1 3 G1 GN D2
M _B _D QS 4 137 DQ S3 DQ 5 1 1 64 M_ B_ DQ 5 2 43 VSS1 4 G2

  c
M _B _D QS 5 154 DQ S4 DQ 5 2 1 66 M_ B_ DQ 5 3 VSS1 5
M _B _D QS 6 171 DQ S5 DQ 5 3 1 74 M_ B_ DQ 5 4 AS0 A6 2 1 -UAS N-7 F
M _B _D QS 7 188 DQ S6 DQ 5 4 1 76 M_ B_ DQ 5 5

   S
 .
5 M _ B_ DQ S # [7:0 ] M _B
M _B
_D
_D
QS #0
QS #1
10
27
DQ

DQ
DQ
S7

S0
S1
#
#
DQ 5 5
DQ 5 6
DQ 5 7
DQ 5 8
1 81
1 83
1 91
M_ B_ DQ 5 6
M_ B_ DQ 5 7
M_ B_ DQ 5 8

   B
M   _B _D QS #2 45 1 93 M_ B_ DQ 5 9
M _B _D QS #3 62 DQ S2 # DQ 5 9 1 80 M_ B_ DQ 6 0
M _B _D QS #4 135 DQ S3 # DQ 6 0 1 82 M_ B_ DQ 6 1
M _B _D QS #5 152 DQ S4 # DQ 6 1 1 92 M_ B_ DQ 6 2
M _B _D QS #6 169 DQ S5 # DQ 6 2 1 94 M_ B_ DQ 6 3
M _B _D QS #7 186 DQ S6 # DQ 6 3
DQ S7 #
AS0 A6 2 1 -UASN -7 F
CLOSE TO SO-DIMM_1
Layout Note:
R 64 1 K _ 1% _ 0 4 MVR EF _ DIM 1
1 .5 V SO-DIMM_1 is place d farther from t he GMCH than SO-DIMM_0 1.5 V

R66 C8 7

C8 5 C 63 C 42 C 51 C 71 C76 C79 1 K_ 1 % _0 4 0 .1 u_ 1 0 V_ X7 R _0 4

*1 0 u _ 6.3 V_ X5 R_  0 6 1 0 u_ 6 .3 V_ X5 R _ 06 1 0 u_ 6 .3 V_ X5R _ 06 1 u _6 .3 V_ X5 R _ 0 4 1 u _ 6.3 V_ X5 R_ 0 4 1 u _ 6.3 V_ X5 R_ 0 4 * 1u _ 6 .3 V_ X5 R _0 4

1 .5V

C1 0 9 C 25 C 66 C 22 8 C 49 C69 C72 C77 C50 C45

4 ,9 ,1 0,2 1 ,2 3 ,2 7,2 9 ,3 1 ,33 ,3 6 1 .5 V
10 ,3 3 VT T _M EM
0 .1 u_ 1 0 V _ X7 R _0 4 0 .1 u_ 1 0 V_ X7 R _ 04 0 .1 u_ 1 0 V_ X7R _ 04 0 .1 u _1 0 V_ X7R _ 04 0 .1 u _1 0 V_ X7R _ 04 0 .1 u _1 0 V_ X7R _ 0 4 0 .1 u _1 0 V_ X7 R _ 0 4 0 .1 u _ 10 V_ X7 R _ 0 4 0 .1 u _ 10 V_ X7 R_ 0 4 0 .1 u _ 10 V_ X7 R _ 0 4
2 ,1 0 ,12 ,1 3 ,1 4, 15 ,1 6 ,1 7,1 8 ,1 9 , 20 ,2 1 ,2 3 ,24 ,2 5 ,2 6,2 7 , 2 8 ,2 9,3 0 ,3 1 , 35 ,3 63 .3 VS

VT T _ MEM

C1 0 2 C 10 7 C 10 8 C 10 3

1 0 u_ 6 .3 V _ X5 R _0 6 1 u _6 .3 V_ X5R _ 0 4 *1 u _ 6 .3V _X5 R_ 0 4 1 u _6 .3 V_ X5 R _ 0 4

B - 12 DDR3 SO-DIMM_1
 Schematic Diagrams

LVDS, Invert er 

3 .3 VS
EDID Mode
PANEL CONNECTOR  2
1
3 RN 6
4 2 .2 K_ 4P2 R _0 4

VIN VIN _L CD

J _ LC D1
L 25 * 1 5 m il _ s ho r t _ 0 6
80m ils 1 2 P_ DD C_ DAT A
3 1 2 4 P_ DD C_ CL K P _ D D C _ D A TA 1 7
5 3 4 6 P_ D DC_ C K L 17
7 5 6 8 BRI GHT N ESS
9 7 8 10 BRIG HTNESS 28
C3 0 0 C2 9 7 C2 9 4
11 9 10 12 INV_ BL ON
13 11 12 14
0 .1 u_ 5 0V _Y 5V _0 6 0 .1 u_ 5 0V _Y 5V _0 6 0. 1u _ 50 V_ Y5 V_ 0 6
LVD S-L CL KN 15 13 14 16 LVD S-L 2N
17 LVD S-L CL KN LVD S-L CL KP 17 15 16 18 LVD S-L 2P LVD S-L 2N 1 7
17 L VDS-L CL KP 19 17 18 20 LVD S-L 2P 17
LVD S-L 1 N 21 19 20 22
17 L VDS-L 1 N 23 21 22 24
LVD S-L 1 P 3.3 VS
17 L VD S-L 1P 25 23 24 26
LVD S-L 0 N 27 25 26 28
CLOSE TO LVDS CONN. 17 L VDS-L 0 N LVD S-L 0 P 29 27 28 30

B 
17 L VD S-L 0P 29 30
PIN 87 2 1 6-3 0 0 6 C 2 91

PLVD D
C4 C6
0 .1 u _1 6 V_ Y5 V _ 04
.
 S 
4.7 u _ 6.3 V_ X5R _ 06 0 .1 u _1 6 V_ Y5 V_ 04
 c 
Sheet 12 of 42 h 
 e
LVDS, Inverter  m
PANEL POWER 
3 .3V S
 a
2A  t  
i  
 c 
R 16 *1 5 m li _ s ho rt_ 0 6

C1 5

D
C1 7
0 .1 u_ 1 6 V_Y 5 V_0 4
*0 .01 u _ 50 V_ X7R _ 04 3 .3V

4
U1
1 2A
PL VDD

BRIG HT NESS AC
D1 5
C i  
 a
 g
C2 9 0
5 VIN VO UT A *0 .1 u_ 1 6 V_Y 5 V_0 4
VIN

r 
*BAV9 9 REC TIF IER
3 2

 a
1 7 NB_ ENAV DD EN GN D

m
R1 3 APL 3 51 2 A

10 0 K_ 1% _ 0 4
G5243A 6- 02- 05243- 9C0
APL3512A 6- 02-03512-9C0
 s 

INVERTER CONNECTOR 
R6 8 * 1 0 m il _ s ho r t _ 0 4 BKL _ EN_ R
28 BKL _E N

R 67 C90

*1 0 0 K_ 1% _ 04 * 0 .47 u _ 10 V_ Y5 V_ 0 4
3.3 V 3.3 V 3. 3V

   4 U3 A
   1
7 4L VC 08 PW    4 U 3B
1    1
7 4 LVC 0 8PW C8 9
3 Z 1 2 01 4
BL ON 2 6 *0 .1 u _1 6 V_ Y5 V_ 04
1 7 BL ON 5
   7
R 69
   7

1 0 0K_ 1 % _0 4    4 U 3C
   1
7 4 LVC 0 8PW
19 SB_B LO N Z 1 2 02 9
3.3 V 8 IN V_BL O N
R7 0 1 0 0K _ 1 % _ 0 4 Z 1 2 03 1 0
   4 U 3D
   1
7 4 LVC 0 8PW    7
R71 C9 3
12
2 8,3 0 L ID_ SW # 11 1 M _0 4 0 .1u _ 1 6V_ Y 5V_ 0 4
13
1 6,2 8 AL L _SY S_ PW RG D

   7
3 0, 31 ,3 2 ,33 ,3 4 ,35 ,3 6 ,37 VIN
3 ,4 ,1 4,1 5 ,1 6,1 8 , 1 9,2 0 ,2 1, 23 ,2 4, 25 ,2 9 ,30 ,3 1 , 33 ,3 4 ,35 3 .3 V
2 ,1 0,1 1 ,1 3,1 4 ,1 5,1 6 , 1 7,1 8 ,1 9,2 0 ,2 1,2 3 ,2 4, 25 ,2 6, 27 ,2 8 ,29 ,3 0 ,31 ,3 5 ,36 3 .3 VS
3 1 ,32 SY S15 V

LVDS, Invert er B - 13
 Schematic Diagrams

HDMI, CRT
L 27
For ESD 1 _0 4 5 VS
5VS

HDMI PORT RD2 RD3

BAV99RECT IF IER BAV99 RECT IFIER

R210
FOR I NTEL GRAPHI C RD1
    C    A     C    A     C    A
1_0 4
J_ HDMI1
U2 BAV99 RECT IFIER
    C     C     C
   A    A    A C319 C31 7
17 HDMIB_ D2BP 39 22 HDMIB_DATA2P
17 HDMIB_ D2BN 3 8 IN_ D1+ OUT _D1 + 23 HDMIB _DATA2 N 10u _6 .3V_X5R_ 06 22 u_6 .3V_X5R_ 08
IN_ D1- OUT _D1- 5VS 19 HDMIB _EXT 1_ HPD
42 19 HDMIB_DATA1P RN2 18 HOTPLUG DET ECT
17 HDMIB_ D1BP 4 1 IN_ D2+ OUT _D2 + 20 +5 V 17
17 HDMIB_ D1BN HDMIB_DATA1N 2 .2K_4 P2 R_0 4
IN_ D2- OUT _D2- HD MIB_ EXT1 _SDA 16 DDC/CEC GND
45 16 HDMIB_DATA0P 1 4 SDA 15 HDMIB _EXT 1_ SCL
17 HDMIB_ D0BP 4 4 IN_ D3+ OUT _D3 + 17 HDMIB_DATA0N 2 3 14 SCL
FOR EMI FOREMI
17 HDMIB_ D0BN IN_ D3- OUT _D3- RESERVED 13 HDMI_CEC
L5 CEC
48 13 HDMIB_CL OCKP HDMIB _CLO CKN 1 2 12
17 HDMIB_ CLKBP 4 7 IN_ D4+ OUT _D4 + 14 HDMIB_CL OCKN TMD SCL OCK- 11
17 HDMIB_ CLKBN IN_ D4- OUT _D4- HDMIB _CLO CKP 4 3 10 CLK SHI EL D
HDMI _CT RLCL K 9 28 HDMIB _EXT1_ SCL * HD MI201 2F 2 SF -90 0T 04s- ho rt TMD SCL OCK+ 9 4 3 HDMIB _D AT A0 N
1 7 HDMI_CT RLCL K    F
17 HDMI_CT RLDATA HDMI_CT RLDATA 8 SCL SCL_ SINK 29 HDMIB _EXT1_ SDA    F
   L
  -
   L
  - 8 T MDSDAT A0 -
SDA SDA_ SINK    P    P SHIEL D0 7 1 2 HDMIB_ DATA0P
7 30    2    5    5 6 TMDS DATA0+
M_PORTB_ HPD# _R HDMIB _EXT1_ HPD    4    1
   0    4    0
HPD HPD_ SINK    R TMD SDATA1 - 5    3 L6
   R    R    R    F    4
   4    F

  s
   0    0    4    L
Z 4 304 25 2    E 4 SHIELD1   -    L
  -
R 56 * 4. 7K _ 0 4    E    R    R *HDMI2 01 2F 2SF -90 0T 04-s ho rt
3 .3VS OE# VCC[1] 3 .3VS    0    0 TMD SDATA1 +    P    P
11    4    4 3    5    5
R 47 * 0_ 04 VCC[2] R4 8    2
  -
   2
  - T MDSDAT A2 -    0    0
DCC_ EN# 32 15 C1 C4 0 C3 2    2
   2
   0
2    R
   0
   R
1 0 DC C_EN# VCC[3] 21 2 0K_1 %_ 04    0
   4    4
SHIEL D2 1    E
   0
   E

  m
RT _EN# VCC[4]    0 TMDS DATA2+    0
26 0.1 u_ 16 V_ Y5V_0 4 *0 .1u _16 V_Y5 V_ 0 4 0 .1u _16 V_Y 5 V_ 04    0    0
   R    R    4
   2    4
PC0 3 VCC[5] 33    A
   A   -    2
  -
   V    V    2    2

  a
PC1 4 PC0 VCC[6] 40 L7    L
    *
   L
    *
   0
   4    0
   4
R2 9 4 99 _ 1% _0 4 Z 4 305 6 PC1 VCC[7] 46 HDMIB_DATA1N 1 2    0    0

  r
REXT VCC[8]    R    R
   A
   V    A
1 HDMIB_DATA1P 4 3    L
   V
   L

Sheet 13 of 42 34 GND[1] 5     *     * 4 3 HDMIB _D AT A2 N

  g
3.3 VS R 49 * 4. 7 K_ 0 4 Z 4 306 C27 C65 * HDMI20 12F 2 SF -90 0T 04 -sho rt    F
C12 81 7-1 19A5 -L
R 58 * 4. 7 K_ 0 4 Z 4 307 3 5   OE_ 1 GND[2] 12    F
   L    L
  -
QE_ 2 GND[3] 18   -
   P 1 2 HDMIB_ DATA2P
GND[4] 0.1 u_1 6V_ Y5V_0 4 0.1 u_ 16 V_ Y5V_0 4    P

  a
24    1    5    5
   6    0
GND[5]    5    0    4

HDMI, CRT
   R

   i
27    R    R    R
   0    0    5
   F
   L
   F L8
GND[6] 31    E
   E
   5
  -    9
   5
   L
  - *HDMI2 01 2F 2SF -90 0T 04-s ho rt
GND[7]    0    0
   4    R    P    R
   5    P
36    4
   2    2    0
   5
   0
49 GND[8] 37   -   -

   D
   2    2
   0    R
   0    R
GN D GND[9] 43    0
   4    4    E    0
   E
GND[10]    0    0
   0    R    4    0
   4
   R    A    2
  -    2
PTN3 36 0BBS    A
   V    V    2   -
   2

  c
PIN 4 9= GND R2 7    L    L    0
   4    0
PORT C_HPD M_PORTB_ HPD# _R     *     *    4
   0    0

   i
17 PORT C_HPD 3 3. VS    R    R
PTN3360BBS 6-03- 03360- 030    A    A

   t
   V    V
*1 0m il_s ho rt _ 04    L
    *
   L
    *
PS8101 6- 03-08101- 032

  a
C3 10 C 59
3.3VS R 57 4. 7K _04 DCC_EN#
0 .1u _16 V_Y5 V_ 04 * 0.1u _1 6V_Y5 V_0 4
R 31 4. 7K _04 PC0

  m R 30 * 4. 7 K_ 04 PC1

  e
   h
  c
   S
 .
   B J_ CRT1
6- 19-31001- 266 10 8AH1 5F ST04 A1CC

CRT PORT 3 .3VS 5VS

L4  . FF CM1
0 0 5M F -600T01
RED 1
2
9
24
10 mil
17 DAC_ RED
L3  . F CM10 0 5M F -600T01 GRN
   4   3

RN7
   4
   3

RN1
17 DAC_ GREEN
17 DAC_ BL UE L2  . CM10 0 5MF -600T01 BLUE 3
11
   4    4    4    4 4
2 .2K_4 P2R_ 04 2.2 K_ 4P2 R_04    0    0    4
   0    0    0    4
   0
_ _ _ _ 12 DDCD ATA
    O     O _     O     O _
U15 R1 2 R11 R10     O     O 5
   P    P    P    P    P    P
   1   2    1
   2
10 9 DDCDATA    N
_    N    N    N
_    N    N 13 HSYNC
1 7 DAC_DDCADATA DDC_ IN1 DDC_OUT 1 _ _ _ _
1 50 _1% _0 4 150 _1 %_ 04 15 0_ 1%_ 04    V
   0    V    V    V
   0    V    V 6
11 12    0    0    0    0 14
DDCL K    5
_    5    5    5
_    5    5 VSYNC
1 7 DAC_DDCACL K DDC_ IN2 DDC_OUT 2    p
_
   p
_
   p    p
_
   p
_
   p 7
   0    0    0    0    0    0
13 14 CRT_ HSYNC R 15 33 _0 4 HSYNC    1    1    1    1    1    1 15 DDCL K
1 7 DAC_HSYNC SYNC_IN1 SYNC_OUT 1 8
15 16 CRT_ VSYNC VSYN C    0    2    1    4    4    4    4    4
R 14 33 _0 4    1    1    3
   1    1    1    6
   1    0    0    0
_    0
1 7 DAC_ VSYNC SYNC_IN2 SYNC_OUT 2     C     C     C     C     C     C _ _     O _
   1   2    R     O    R
1 3 BLUE    D   D    7    P    P    7
5VS VCC_SYNC VIDEO_ 1    N   N    X    N    N    X
    G
    G _
   V _ _
   V _
   V
2 4 GRN    0    V    0    0
3 .3VS VCC_VIDEO VIDEO_ 2    5    0    5    5
_    5
_ _ _
   p    p    p
7 5 RED    p
   0
   0    0    0
   2    0
   0
3.3VS VCC_DDC VIDEO_ 3    0    2
   2    2    0
8 6    1    1
BYP GND    5
   9    3    2
   9    7
   9     C
   4    4    4    2    2    2
   0    0
_    0 TPD7S0 19     C     C     C
_ _
   8    V    9    V    6    V
   5    5    9    5
IP4772CZ16 6-02-47721-B60
   9
   2    Y    9
   2    Y    2    Y
_ _ _
    C    V     C    V     C    V
TPD7S019 6-02-07019-B20
   0    0
   1    0
   1    1
_ _
   u _
   u    u
   2    2    2
   2    2
 .    2
 .  .
   0    0    0

2 ,10 ,1 1,1 2,14 ,15 ,16,1 7,1 8,19 , 20 ,2 1,2 3,24 ,25 ,26,2 7,2 8,29 , 30 ,3 1,3 5,36 3.3VS
2 ,17 ,20,2 1,2 6,27 ,30 ,3 1,3 5,36 5VS

B - 14 HDMI, CRT
 Schematic Diagrams

IBEXPEAK- M 1/9

RT CV CC
6-22- 32R76-0B2
IBEXPEAK - M (HDA,JTAG,SATA)
R T C_ X 1
1 A
6-22- 32R76-0BG
V D D3 C 40 2
   1   2
1 5p _ 5 0 V _ NP O _ 04 X8
C 3 C 36 9 2 .2 u_1 6 V_ X5R _ 0 6
1 T JS 12 5 DJ 4 A 4 2 0 P _ 32 .7 6 8 K Hz
RT C_ V B A T_ 1 2 A
   2   1    4 3
R 30 4 6-22- 32R76-0B4 R T C_ X 2 Co- layout X7, X8
2 0 K _ 1% _ 0 4 X7 R 3 02
D1 7 * MC -1 46 _ 3 2 .7 68 K H z
B A T 5 4C S 3 1 0 M_ 0 4 U2 0 A
   1    3   4
RTC CLEAR  C 39 7
R253 C3 9 9 JOPEN2 1 5p _ 5 0 V _ NP O _ 04 RT C _X 1 B13 D 33
D1 3 RT C X 1 F W H0 / LAD 0 B33 LP C_ A D 0 24 ,2 8
* OP E N_ 1 0 m li -1 MM RT C  _X 2 LP C_ A D 1 24 ,2 8
RT C X 2 F W H1 / LAD 1
1 K _ 1 % _ 04 2 .2 u_ 1 6 V _ X5 R _ 06
   2 Z o= 5 0 O ? 5 % F W H2 / LAD 2
C 32
A32 LP C_ A D 2 24 ,2 8
RT C _ V B A T 1 RT C _R S T # C1 4 F W H3 / LAD 3 LP C_ A D 3 24 ,2 8
R 30 5
J _ RT C1 2 0 K _ 1% _ 0 4 RT C RS T # C 34
D1 7 F W H 4 / LF RA M E # LP C_ F R A ME # 2 4 ,2 8
S RT C _R T C#
1 S R TC RS T# A34
J_RTC1
   C    C
   1 A16 L DR Q0 # F34
TPM CLEAR  S M_ IN T RU DE R #
2
R299 C4 0 0 JOPEN1
IN TR UD E R #
   T    P
L DR Q1 # / GP IO2 3
* OP E N_ 1 0 m li -1 MM R 29 8 330 K_04 P CH _ INT V R ME N A14    R    L AB9 S E R IRQ

B 
R T CV C C IN TV RM E N S E R IRQ S ERI RQ 2 4,28
1 2 8 5 20 5 -0 2 70 1 1 M _ 04 2 .2 u_ 1 6 V _ X5 R _ 06    2

2 7 ,2 9 HD A _ B IT CL K
A30
HD A _ B C LK AK7 S A T A R XN 0 .
 S 
BIOS ROM 
D2 9 S A T A 0 RX N AK6 S A T A R XP 0
S A TA R XN 0
S A TA R XP 0
26
26
SATA HDD
 c 
3 .3 V S 2 7 ,2 9 HD A _ S Y N C HD A _ S Y NC S A TA 0R X P AK11 S A T A T X N0
P1 S A T A 0 TX N AK9 S A T A T XN0 26
HD A _ S P K R SATATXP0
27 HD A _ S P K R SPKR SATA0TXP S A T A T XP 0 26

h 
NC 1
C 2 09 C3 0
S HO R T 0 .1 u _1 6 V _ Y 5V _0 4
32Mbit
2 7 ,2 9 HD A _ RS T # HD A _ RS T#
S A T A 1 RX N
AH6
AH5
S A T A R XN 1
S A T A R XP 1
S A TA R XN 1 2 6
Sheet 14 of 42  e
SATA ODD
G3 0 S A TA 1R X P AH9 S A TA R XP 1 26
U10 S A T A T X N1

m
S P I_ V D D 8 5 S P I_ S I 27 HD A _ S D IN0 HD A _ S D IN0 S A T A 1 TX N AH8 SATATXP1 S A T A T XN1 2 6

R1 6 3
VDD

SO
SI
2 S P I_ S O
R 38 1

R 38 2
*0 _ 0 4

*0 _ 0 4
8 51 8 _ S PI_ S I 2 8

8 51 8 _ S PI_ S O 28
29 HD A _ S D IN1
F30
HD A _ S D IN1
SATA1TXP

S A T A 2 RX N
AF11
S A T A T XP 1 2 6
IBEXPEAK - M 1/9
 a
3.3 K _ 1 % _ 0 4 E32 AF9
S P I_ W P # 3
WP# CE#
1 S P I_ CS 0 # R 38 3 *0 _ 0 4
8 51 8 _ S PI_ C S 0 # 28
HD A _ S D IN2
   A S A TA 2R X P
S A T A 2 TX N
AF7
F32
   D AF6
R1 5 6
3.3 K _ 1 % _ 0 4 S CK
6 S P I_ S CL K R 38 4 *0 _ 0 4
8 51 8 _ S PI_ S C L K 28
HD A _ S D IN3
   H
   I
SATA2TXP
AH3  t  
i  
 c 
S P I_ HO L D# 7 4 B29 S A T A 3 RX N AH1
H OL D# VSS 2 7 ,2 9 HD A _ S DO UT HD A _ S D O S A TA 3R X P AF3
S A T A 3 TX N AF1
M X 25 L 3 2 05 D M2 I-1 2 G D 18 S C D 34 0

D
C A R3 0 7 HD A _ DO C K _ E N # H3 2 SATA3TXP

6-04- 25320-A70 28 ME _W E # HD A _ DO C K _E N# / G P IO 33    A AD9 S A T A R XN 2

J30    T S A T A 4 RX N AD8 S A T A R XP 2
6-04- 02532-470 *1 0 m il _ s ho rt_ 0 4
   A
i  
HD A _ DO C K _R S T # / G P IO1 3 S A TA 4R X P
6-04- 26321-470 R 30 3 1 K _1 % _ 0 4
   S
AD6 S A T A T X N2

 a
S A T A 4 TX N AD5 SATATXP2
SATA4TXP
   1

 g
P CH _ JT A G _ T CK _ B U F M 3 AD3
J T A G_ T CK S A T A 5 RX N AD1
SPI_* = 1.5"~6.5" J OP E N3
* OP E N _ 10 m il -1 MM P CH _ JT A G _ T MS K3 S A TA 5R X P AB3
Flash Descriptor
Security Overide    2
P CH _ JT A G _ T DI K1
J T A G_ T MS

J T A G_ T DI
S A T A 5 TX N
SATA5TXP
AB1

1 .1 V S _ V T T
r 
 a
   G
m
3 .3 V P CH _ JT A G _ T DO J2 AF16 S A T A IC OM P R 89 3 7 . 4 _ 1 % _0 4
3 .3 V S P CH _ JT A G _ RS T # J4
J T A G_ T DO
   A
   T
S A TA I CO MP O
AF15
J T A G_ R S T #
   J S A T A IC OM P I
R2 9 5

*2 0 K _ 1 %_ 0 4
R 29 3

*2 0 0 _ 06
R2 9 0

*2 0 0_ 0 6
R 2 87

* 20 0 _ 0 6
R 93
R282
10 K _ 0 4 S E RIR Q
*1 K _ 1 % _0 4 H DA _S P K R
S P I_ S C LK BA2
S P I_ C LK
3 .3 V S
 s 
 NO REBOOT STRAP: HDA_SPKR High Enable
P CH _ JT A G _ TM S S P I_ CS 0# AV3 R 2 78 * 1 0K _0 4
P CH _ JT A G _ TD I S P I_ C S 0 #
P CH _ JT A G _ TD O S P I_ CS 1# AY3 T3 S A T A _ L E D#
P CH _ JT A G _ RS T # S P I_ C S 1 # S A TA LE D # S A TA _L E D # 2 9 3 .3 V S

3 .3 V S iTPM ENABLE/DISABLE S P I_ S I AY1 Y9 O DD _ DE T E C T# R 1 08 10K_4

R2 9 4 R 28 9 R2 8 8 R 2 86 S P I_ M OS I S A TA 0 G P / GP IO2 1

*1 0 K _ 1 %_ 0 4 *1 0 0_ 1 % _ 04 *1 0 0_ 1 % _ 04 * 10 0 _ 1 % _0 4
R 26 3 * 1K _ 1 % _ 04 S P I_ S I S P I  _ S O R 26 4 3 3 _0 4 S P I_ S O _R AV1
S P I_ M IS O    I
   P S A TA 1 G P / GP IO1 9
V1
O DD _ DE T E C T # 26
TPM FU
NCTI ON:SPI_SI High Enabl e
I b e x P e ak -M _ Re v 0 _ 9
   S S A T A _ DE T# 1 R 2 74 10K_04

R 28 5 * 4. 7 K _ 0 4 P C H _J T A G _T C K _ B UF

ESATA 
SATATXP2 C 16 8 * 0 . 01 u _5 0V _X 7R _ 0 4

S A T A T X N2 C 16 5 * 0 . 01 u _5 0V _X 7R _ 0 4

S A T A R XN 2 C 15 5 * 0 . 01 u _5 0V _X 7R _ 0 4

S A T A R XP 2 C 16 4 * 0 . 01 u _5 0V _X 7R _ 0 4

2 3 ,2 5 ,28 ,2 9 ,3 1 ,3 2,3 7 V D D3
21 R TC V C C
2 ,4 ,6 ,7 ,1 5 ,1 6,1 9 ,2 0 ,2 1,3 4 ,3 5 ,3 6 1.1 V S _V TT
3 ,4 ,1 2 ,1 5, 16 ,1 8 ,1 9, 20 ,2 1 ,2 3 ,24 ,2 5 ,2 9 ,30 ,3 1 ,3 3 ,3 4,3 5 3 .3 V
2 ,10 ,1 1 ,1 2 ,1 3,1 5 ,1 6 ,1 7,1 8 ,1 9 ,2 0,2 1 ,2 3 ,2 4, 25 ,2 6 ,2 7 ,28 ,2 9 ,3 0 ,31 ,3 5 ,3 6 3 .3V S

IBEXPEAK- M 1/9 B - 15
 Schematic Diagrams

IBEXPEAK - M 2/9

IBEXPEAK - M (PCI-E,SMBUS,CLK) SMB _C L K 3

RN 1 6
2 .2K _ 4P 2R _ 0 4
2
3 .3 V

SMB _D A T A 4 1

U 20 B RN 1 1
2 .2K _ 4P 2R _ 0 4
BG 3 0 B9 PC H_ BT _ EN # SML 0 _ DA T A 3 2
BJ 3 0 PER N1 S MB AL ERT # / G PI O 1 1 P CH _ BT _E N# 2 3 ,2 9 4 1
SML 0 _ CL K
BF29 PER P 1 H 14 SM B _ CL K S M B _C L K 2
BH 2 9 PET N 1 S M BC LK
RN 1 3
PET P1 C8 SM B _ DA TA 1 0K _8 P4 R _ 0 4
AW3 0 SM B DA TA SM B _ DA T A 2 1 8
PCH _ BT _ EN#
23 P CIE _ RX N 2_ N EW _ C A RD B A3 0 PER N2 U SB_ OC # 8 9 2 7
23 P CIE _ RX P2 _ NE W _ CA RD PER P 2 18 U SB_ OC # 8 9
C 1 71 0 . 1u _1 0V _ X 7R _ 04 PC IE_ T XN2 _ C BC 3 0 J14 PC H_ U PE K_ IN IT # LP D_ S PI _I NT R # 3 6
23 P CI E _ T X N 2_ N EW _ C A RD BD 3 0 PET N 2 SM L 0 AL ERT # / G PIO 6 0 PC H_ U PE K_ IN IT # 1 8 4 5
C 1 81 0 . 1u _1 0V _ X 7R _ 04 PC IE_ T XP2 _ C
23 P CIE _ T X P2 _ NE W _ CA RD PET P2 C6 SM L 0_ C L K
SML 0 C LK S ML 0 _ CLK 23
AU 3 0 RN 1 0
  s
23 P C IE _ R X N3 _ W L A N AT 3 0 PER N3 G8 SM L 0_ D AT A 2 .2K _ 4P 2R _ 0 4
  u
23 P C IE _ R X P 3 _W L A N PC IE_ T XN3 _ C AU 3 2 PER P 3 S ML 0 DA TA S M L 0 _D A T A 23 SMD _ CP U_ T HE RM 3 2
C 1 42 0 . 1u _1 0V _ X 7R _ 04
   B
23 PC IE_ T XN3 _ W L AN PC IE_ T XP3 _ C A V3 2 PET N 3 SMC _ CP U_ T HE RM 4 1
C 1 23 0. 1u _1 0 V_ X7 R_ 0 4
   M
23 PC IE _ T XP 3 _W L AN PET P3 M 14 L P D _S P I_ INT R #
   S
B A3 2 SM L 1 AL ERT # / G PIO 7 4
2 5 PCI E _ RXN 4_ G LAN PER N4

  s
B B3 2 E10 SM C_ C PU_ T H E R M
2 5 PCI E_ RXP4 _ GL A N PER P 4 SM L 1 CL K / G PIO 5 8 S MC _ CPU _ T HE RM 3 ,2 8
C 1 91 0 . 1u _1 0V _ X 7R _ 04 PC IE_ T XN4 _ C BD 3 2
2 5 P CIE_ T XN 4_ G L AN B E3 2 PET N 4 G 12
C 1 02 0 . 1u _1 0V _ X 7R _ 04 PC IE_ T XP4 _ C SM D_ C PU_ T H E R M
2 5 P CIE_ T XP4 _ GL A N PET P4 SM L1 D AT A / G PIO 7 5 S MD _ CPU _ T HE RM 3 ,2 8

  m BF33
BH 3 3 PER N5
   *
   E T13
PEG _ CL KR E Q # R 29 1 1 0K _ 04

  a  - Control ler

BG 3 2 PER P 5 CL _ C L K1 L AN _C L KR E Q# R 11 2 1 0K _ 04

  r    I
PET N 5
PCI-E x1 Usage BJ 3 2 T11
PET P5
   C Link CL _ D A T A1

  g Sheet 15 of 42 Lane 1 WLAN

B A3 4
AW34 PER N6    P C L_ R S T 1 #
T9

  a
BC 3 4 PER P 6 10Kpull -down to

IBEXPEAK - M 2/9
PET N 6
Lane 2 NEW CARD
   i
BD 3 4 GND
PET P6 H1 PE G _ CL KR EQ # 100-MHz Gen2 dif fer enti al clock to PCIe Graphics
Lane 3 3G AT 3 4 PEG _A _ CL KR Q# / G PIO 4 7 devic e.

   D
AU 3 4 PER N7
Lane 4 GLAN / CARD READER  PER P 7
AU 3 6 AD43
Lane 5 X A V3 6 PET N 7
   G CL KO UT _ PE G_ A_ N AD45

  c    E
PET P7 C LK OU T _ PEG _A _P
Lane 6 X
   i    P
BG 3 4 AN4
C LK _E XP _ N 4

   t
PER N8 C L KO UT _ D MI_ N
Lane 7 X BJ 3 4 AN2
C LK _E XP _ P 4
BG 3 6 PER P 8 CL KO U T_ D MI _P
Lane 8 X
  a
BJ 3 6 PET N 8
PET P8 AT1 PC H_ C L K _ DP _ N _ R R2 6 6 *1 0 m  _il s h o rt _ 0 4 C L K _D P _ N 4
C LK OU T _ DP _ N / C LK OU T _ BCL K1 _ N AT3 PC H_ C L K _ DP _ P_ R R2 6 7 *1 0 m  _il s h o rt _ 0 4
CL KO U T_ D P_ P / C L K O UT _ BC L K 1 _P C L K _D P _ P 4

  m
3 .3 V 3 .3 VS A K4 8
A K4 7 CL K O U T_ P C IE 0 N

  e
RN 8 CL K O U T_ P C IE 0 P A W 24 100-MHz diff erenti al clock f romPCH to Pr ocesso r.
P9 CL KI N_ D MI_ N B A2 4 C L K _ P C I E _I C H # 2 Connect t o PEG_CLK#/PEG_CLKpins of the
1 0 K_ 8P 4 R_ 0 4 PC IEC L K R Q0 #
PC IECL K RQ 0 #/ GPI O7 3
   R C L KIN_ D MI _P C L K _ P C I E _I C H 2 processo

   h
1 8 P C IE C L KRQ 1 #
2 7 P C IE C L KRQ 0 #    E
3 6 AM 4 3    F A P3

  c
P C IE C L KRQ 5 #
4 5 P E G_ B _ C LK RQ # AM 4 5 CL K O U T_ P C IE 1 N
   F C L KIN _B CL K_ N A P1 C LK _ BUF _B CL K_ N 2
CL K O U T_ P C IE 1 P
   U CL KIN _ BC LK _P C LK _ BUF _B CL K_ P 2
   B
   S
PC IEC L K R Q1 # U4

 .
PC IECL K RQ 1 #/ GPI O1 8 F18
   K C L K IN _ D O T _9 6 N E18
C LK _ BUF _D O T9 6 _N 2
AM 4 7    L CL K IN _ DO T _ 9 6P C LK _ BUF _D O T9 6 _P 2

   B    C
2 3 C L K_ P C IE _ NE W _ CAR D # AM 4 8 CL K O U T_ P C IE 2 N
2 3 C L K_ PCI E _ NE W _ CAR D CL K O U T_ P C IE 2 P
  mCC LL KIN
AH13 C 3 91 2 2p _5 0 V _ N P O _ 04
_ S AT A_ N / CK S SC D_ N C L K _ S A TA # 2
R 283 * 10 m i l _ sh or t _ 04 CL K _ SL O T2 _ O E# N4 A H 12
2 3 N EW C AR D _ C L KRE Q# PC IECL K RQ 2 #/ GPI O2 0
  o KIN _S A T A_ P / C KS SC D _P C LK _ SA T A 2
  r
2 3 CL K_ P CIE_ M IN I#
AH 4 2    F P41
C LK _ BUF _R E F 1 4 2
AH 4 1 CL K O U T_ P C IE 3 N REF CL K1 4 IN    1
R2 6 8
2 3 CL K_ P C IE _ M INI CL K O U T_ P C IE 3 P
X6 6-22- 25R00-1B4
A8 J42 1 M_ 0 4 F S X5 L _2 5 M H z
2 3 W L AN _ CL K R EQ # PC IECL K RQ 3 #/ GPI O2 5 C L K IN_ P CIL O OPB ACK C L K _ P C I _ FB 18 6-22- 25R00-1B5
   2

AM 5 1 AH51 XT AL 25 _ IN
2 5 C LK _P CIE _G L AN # AM 5 3 CL K O U T_ P C IE 4 N X TA L2 5 _ IN AH53 XT AL 25 _ O UT C 3 87 2 2p _5 0 V _ N P O _ 04
2 5 CL K_ P CIE_ G L AN CL K O U T_ P C IE 4 P XT A L 2 5 _ OU T
LA N_ C LK REQ # M9 AF38 XCL K_ R CO M P R 87 9 0 . 9 _ 1 % _ 04 9 0. 9- O ? % pu l l u p
PC IECL K RQ 4 #/ GPI O2 6 X CL K _ R CO MP 1 .1 V S_ V T T
to +VccI O
(1.05V, S0rail )
AJ 5 0 T45
AJ 5 2 CL K O U T_ P C IE 5 N   x CL K O UT F L EX0 / G PIO 6 4
CL K O U T_ P C IE 5 P   e
PC IEC LK RQ 5 # H6    l
   F
P43
PC IECL K RQ 5 #/ GPI O4 4 CL K O UT F L EX1 / G PIO 6 5

A K5 3    k T42
A K5 1 CL K O U T_ P E G_ B _N   c CL K O UT F L EX2 / G PIO 6 6
CL K O U T_ P E G_ B _ P   o
PE G _ B_ CL K R Q # P1 3    l N 50
PEG _ B_ CL KR Q# / GP I O5 6    C CL K O UT F L EX3 / G PIO 6 7

Ib e x Pe ak -M _ Re v 0 _ 9

3 .3 VS 2,1 0 ,1 1 ,1 2,1 3 ,14 ,1 6 ,1 7,1 8 ,1 9, 20,2 1 ,2 3 ,2 4 ,2 5, 26 ,2 7 ,2 8 ,2 9 ,3 0,3 1 ,3 5 ,3 6

1 .1 VS _ VT T 2 ,4 ,6 ,7 ,1 4, 16 ,1 9 ,2 0 ,2 1 ,3 4, 35 ,3 6
3 .3 V 3,4 ,1 2 ,1 4 ,1 6,1 8, 19 ,2 0 ,2 1,2 3 ,2 4, 25,2 9 ,3 0 ,3 1 ,3 3,3 4 ,3 5

B - 16 IBEXPEAK - M 2/9
 Schematic Diagrams

IBEXPEAK - M 3/9

IBEXPEAK - M (DMI,FDI,GPIO)
U2 0 C
BA18
B C 24 F DI_ R XN 0 B H1 7 F DI _T XN0 3
3 D MI_ RX N 0 D MI0 R XN F DI_ R XN 1 F DI _T XN1 3
B J 22 B D1 6
3 D MI_ RX N 1 A W 20 D MI1 R XN F DI_ R XN 2 BJ16 F DI _T XN2 3
3 D MI_ RX N 2 B J 20 D MI2 R XN F DI_ R XN 3 BA16 F DI _T XN3 3
3 D MI_ RX N 3 D MI3 R XN F DI_ R XN 4 BE14 F DI _T XN4 3
B D 24 F DI_ R XN 5 BA14 F DI _T XN5 3
3 D MI_ RX P 0 D MI0 R XP F DI_ R XN 6 F DI _T XN6 3
B G 22 B C1 2
3 D MI_ RX P 1 B A 20 D MI1 R XP F DI_ R XN 7 F DI _T XN7 3
3 D MI_ RX P 2 B G 20 D MI2 R XP B B1 8
3 D MI_ RX P 3 D MI3 R XP F D I_ RX P 0 BF17 F DI _T X P0 3
F D I_ RX P 1 F DI _T X P1 3
B E 22 B C1 6
3 DM I_ TX N 0 B F 21 D MI0 T X N F D I_ RX P 2 B G1 6 F DI _T X P2 3
3 DM I_ TX N 1 D MI1 T X N F D I_ RX P 3 F DI _T X P3 3
B D 20 AW16
3 DM I_ TX N 2 B E 18 D MI2 T X N F D I_ RX P 4 B D1 4 F DI _T X P4 3
3 DM I_ TX N 3 D MI3 T X N F D I_ RX P 5 F DI _T X P5 3
BB14
B D 22 F D I_ RX P 6 B D1 2 F DI _T X P6 3
3 DM I_ TX P 0 D MI0 T X P F D I_ RX P 7 F DI _T X P7 3

B 
B H 21
3 DM I_ TX P 1 B C 20 D MI1 T X P
3 DM I_ TX P 2 B D 18 D MI2 T X P BJ14
3 DM I_ TX P 3 F D I _I N T 3

.
D MI3 T X P F D I_IN T
   I    I
 S 
BF13
R 26 1 49 . 9 _ 1 % _0 4 DMI _C OM P _ R B H 25    M    D F DI_ F S Y NC 0 F D I _ FS Y N C 0 3
1 .1 V S _ V T T D MI_ Z C OM P
   D   F B H1 3
F D I _ FS Y N C 1 3

 c 
B F 25 F DI_ F S Y NC 1
D MI_ IR CO MP BJ12
F D I _ LS Y N C 0 3

h 
F D I_ LS Y NC 0
B G1 4

Sheet 16 of 42
F D I_ LS Y NC 1 F D I _ LS Y N C 1 3

 e
IBEXPEAK - M 3/9 m
3.3 V S
R 11 1 1 0 K _ 04 S Y S _ RE S E T # T6
S Y S _ RE S E T # WAKE#
J 12 P CIE _W A K E #
P C IE _W A K E# 2 3,2 5  a
S Y S _ P W R OK M6 Y1 P M_ C LK RUN #  t  
i  
 c 
S Y S _ P W R OK C L K RU N# / GP I O3 2 P M _C L K RU N# 2 4
   t 3 .3 V
S B _ P W RO K B 17   n
  e
D
P W RO K
  m
P CIE _ W A K E # R12 1 1 K _ 1 %_ 0 4
K5   eS US _S T AT # / GP IO6 1 P8
  g
P M_ MPW RO K S 4 _S TA T E # P M_ S L P _ L A N# R 12 7 * 10 K _ 0 4

i  
M E P W R OK S 4 _ S TA TE # 2 4
  a
  n S US C L K / GP IO6 2  a
S W I# R 13 0 1 0K _0 4
A UX P P W R OK _ R A 10 F3
  a
R 29 7 10 K _ 0 4
L A N _ RS T #
   M
 g
EXT-LAN S US _ P W R _ A CK R 28 4 1 0K _0 4

  r S LP _ S5 # / GP IO6 3
D9 E4 P W R_ B T N # R 10 9 * 10 K _ 0 4

r 
4 P M_ DR A M _P W RG D D RA M P W R OK
  e
  w
 a
A C_ P R E S E NT R 11 5 1 0K _0 4
C 16 H7
  o
RS M RS T#
28 R S MR S T# R S MR S T # SLP_S4# S US C # 2 8 ,33
   P
m
R 30 0 10 K _ 0 4
P M_ B A T L OW # R 29 6 8 . 2 K _0 4

  m
S U S _P W R_ A C K M1 P12 S US B #
28 S U S _ P W R_ A C K S US _ P W R _A CK / G P IO3 0 SLP_S3# SUS B # 2 3 , 28 , 3 1 3 .3 V S
  e
28 P W R _B T N #
P W R _B T N # P5
P W RB T N #
   t
  s
  y
S L P _M #
K8 P M _C L K RU N# R 27 1 8 . 2 K _0 4
 s 
1 8,2 8 A C _P R E S E N T
A C _P R E S E N T P7
A CP R E S E NT / G P IO 31
   S TP23
N2 A L L _ S Y S _ P W R GD R 14 3 1 0K _ 04

P M_ B A T L OW # A6 BJ10
B A TL O W # / GP IO 7 2 P M S Y N CH H_ P M _ S YN C 4

S W I# F 14 F6 P M_ S L P _ L A N#
28 S W I# RI # S L P _ LA N #
R1 3 9 *1 0 m li_ s ho rt_ 0 4 P M_ M P W RO K
2 8, 36 V C OR E _ ON
Ibe x P e a k- M_ Re v 0 _ 9

3 .3 V

3 .3 V
3.3 V 3 .3V
   4
U8 D
   4    1 S B _P W RO K
U8A    1
U 8C 7 4 LV C 0 8P W R1 4 4 *1 0 m li _ s ho rt_ 0 4
7 4 L V C0 8 P W    4 U8 B 7 4 LV C0 8 P W 12
   4    1 9 4 ,3 6 DE L A Y _ P W RG D 11 S Y S _ P W R OK
   1 74 L V C 08 P W 4 ,3 3,3 4 1 .1 V S _ V T T_ P W R GD R1 4 2 *1 0 m li _ s ho rt_ 0 4
4 8 A L L_ S Y S _ P W RG D 13
1 3 3 1.8 V S _ P W RGD 6 1 .1 V S _ V T T_ E N 10
3 3 DD R1 . 5 V _ P W R GD
3 5    7 R1 4 5
SUSB# 2
   7
10 K _ 0 4
   7 A L L _ S Y S_ P W R GD 1 2 ,28
   7 34 1 .1 V S _ V T T _E N

R 14 1 2K 1_ % _ 0 4
H_ V T T PW R GD 4

C 4 70
ON R 13 8
1 u _ 6.3 V _ X 5 R_ 0 4
1 K _ 1% _ 0 4

3 .3V S 2 ,10 ,1 1 ,1 2,1 3 ,1 4 ,15 ,1 7,1 8,1 9 ,2 0, 21 ,2 3 ,2 4,2 5,2 6, 27 ,2 8,29 ,3 0 ,3 1,3 5 ,3 6
3 .3V 3 ,4,1 2 ,1 4 ,15 ,1 8 ,1 9,2 0,2 1 ,23 ,2 4 ,2 5,2 9 ,3 0 ,31 ,3 3,3 4,3 5
1 .1V S _V TT 2 ,4 ,6 ,7, 14 ,1 5 ,19 ,2 0 ,2 1,3 4 ,3 5 ,36

IBEXPEAK - M 3/9 B - 17
 Schematic Diagrams

IBEXPEAK - M 4/9

IBEXPEAK - M (LVDS,DDI)

U20D

T48 BJ46
12 BLON L_BKLTEN SDVO_TVCLKI NN
T47 BG46
12 NB_ENAVDD L_VDD_EN SDVO_TVCLK INP
Y48 BJ48
L_BKLTCTL SDVO_STALLN BG48
 AB48 SDVO_STALLP
12 P_DDC_CLK Y45 L_DDC_CLK BF45
3.3VS
12 P_DDC_DATA L_DDC_DATA SDVO_INTN BH45
L_CTRL_CLK  AB46 SDVO_INTP
R 96 * 10 K
_04
R 97 * 10 K
_04 L_CTRL_DATA V48 L_CTRL_CLK
L_CTRL_DATA
R83 2.3
7K_
1%_04 LVD
S_IBG  AP39 T51

  s
 AP41 LVD_IBG SDVO_CTRLCLK T53
LVD_VBG SDVO_CTRLDATA
 AT43

  m
 AT42 LVD_VREFH BG44
LVD_VREFL DDPB_AUXN BJ44

  a
DDPB_AUXP  AU38

  r
 AV53 DDPB_HPD
12 LVDS-LCLKN
 AV51 LVDSA_CLK#    S BD42   B

  g Sheet 17 of 42 12 LVDS-LCLKP

BB47
LVDSA_CLK    D
   V
   L
DDPB_0N
DDPB_0P
BC42
BJ42   t
 r
  O
  V
  D

  a
12 LVDS-L0N BA52 LVDSA_DATA#0 DDPB_1N BG42   S
  e  o

   i IBEXPEAK - M 4/9 12 LVDS-L1N

12 LVDS-L2N
 AY48 LVDSA_DATA#1
 AV47 LVDSA_DATA#2
LVDSA_DATA#3
  c
  a
DDPB_1P
DDPB_2N
DDPB_2P
BB40
BA40
 AW38
RN 5
  P
 y
   f
   D
2.2K_4P2R_04
BB48 DDPB_3N BA38 3 2  a
12 LVDS-L0P BA50 LVDSA_DATA0   r DDPB_3P 4 1
3.3VS   l
12 LVDS-L1P
 AY49 LVDSA_DATA1   e  p

  c    t
12 LVDS-L2P  s
 AV48 LVDSA_DATA2 Y49
  n
   i
  i
LVDSA_DATA3 DDPC_CTRLCLK  AB49 HDMI_CTRLCLK13   D
   I
   t
DDPC_CTRLDATA HDMI_CTRLDATA 13

  y
 AP48

  a  AP47 LVDSB_CLK#

LVDSB_CLK   a
   l
BE44
DDPC_AUXN BD44
DDPC_AUXP  AV40
  p
 AY53 PCH_DDPC_HPD

  m  AT49 LVDSB_DATA#0 DDPC_HPD

EMI  AU52 LVDSB_DATA#1   s
   i
BE40 HDMIB_D2BN_C C125 0.1u_10V
_X7R
_04

  e
HDMIB_D2BN 13   C
   D
R10 5 0_ 0
4 DAC_BLUE_R  AT53 LVDSB_DATA#2 DDPC_0N BD40 HDMIB_D2BP_C C126 0.1u_10V
_X7R
_04
13 DAC_BLUE LVDSB_DATA#3 DDPC_0P BF41 HDMIB_D2BP13   t

   h
C174 HDMIB_D1BN_C C111 0.1u_10V
_X7R
_04
DDPC_1N HDMIB_D1BN 13  r
   l
*33p_50V_NPO
_04 R99 0_04 DAC_GREEN_R  AY51 BH41 HDMIB_D1BP_C C112 0.1u_10V
_X7R
_04
13 DAC_GREEN  o
 AT48 LVDSB_DATA0 DDPC_1P HDMIB_D1BP13
  a
BD38 HDMIB_D0BN_C

  c
C170 C113 0.1u_10V
_X7R
_04 HDMIB_D0BN 13   P
 AU50 LVDSB_DATA1 DDPC_2N
13 DAC_RED
*33p_50V_NPO
_04 R91 0_04 DAC_RED_R
   t BC38 HDMIB_D0BP_C C114 0.1u_10V
_X7R
_04
HDMIB_D0BP13  y
   i
C166  AT51 LVDSB_DATA2 DDPC_2P BB36 HDMIB_CLKBN_C C115 0.1u_10V
_X7R
_04

   S
LVDSB_DATA3 DDPC_3N HDMIB_CLKBN 13  a
  g
*33p_50V_NPO
_04 BA36 HDMIB_CLKBP_C C116 0.1u_10V
_X7R
_04   l

 .
DDPC_3P HDMIB_CLKBP 13
   i  p

NEAR PCH  AA52    D U50

 s

   B
R1
04 150_1%_04 DAC_BLUE_R   i
R9
8 150_1%_04 DAC_GREEN_R  AB53 CRT_BLUE DDPD_CTRLCLK U52   D
R9
2 150_1%_04 DAC_RED_R  AD53 CRT_GREEN DDPD_CTRLDATA 5VS
CRT_RED
BC46 Q7
V51 DDPD_AUXN BD46     G
MTN7002ZHS3
13 DAC_DDCACLK V53 CRT_DDC_CLK DDPD_AUXP  AT38
13 DAC_DDCADATA CRT_DDC_DATA DDPD_HPD PCH_DDPC_HPD S D
PORTC_HPD 13
BJ40   D
Y53 DDPD_0N BG40
13 DAC_HSYNC Y51 CRT_HSYNC DDPD_0P BJ38   t
R34
13 DAC_VSYNC CRT_VSYNC DDPD_1N BG38  r
DDPD_1P BF37  o
100K_1%_04   P
R8
8 1K_1%_04 DA
C_IR EF_R  AD48    T DDPD_2N BH37
 AB51 DAC_IREF
CRT_IRTN
   R
   C
DDPD_2P BE36
DDPD_3N BD36
 y
 a
DDPD_3P   l
 p
IbexPeak -M_Rev0_9  s
  i
Connect to GND   D
PC H_ D
DPC _HP D R33 *0_04 PO
R TC H
_PD

 No Connect
External Graphics (PCH I ntegrated Graphics Disable)

External Graphics (PCH Integrated Graphics Disable)

2,10,11,12,13,14,15,16,18,19,20,21,23,24,25,26,27
,28,29,30,31,35,36 3.3VS
2,13,20,21,26,27,30,31,35,36 5VS

B - 18 IBEXPEAK - M 4/9
 Schematic Diagrams

IBEXPEAK - M 6/9
IBEXPEAK - M (GPIO,VSS_NCTF,RSVD)

U20F

E DP _ CAR D _D E T # Y3 AH 4 5
0213 S_GPIO CHANGE TO EDP_CARD_DET# B MBU SY # / G PIO 0 C LK OU T _ P C IE6 N AH 4 6
S MI # C38 C L KO UT _ P C IE6 P
28 SM I# T AC H 1 / G PIO 1
3 .3 VS R 27 2 1 K _ 1 % _ 04 ED P_ C ARD _ D E T #
DG P U _ HPD _ IN TR # D37
T AC H 2 / G PIO 6
   C AF 4 8
R273
28 SC I#
S CI # J32
T AC H 3 / G PIO 7    S C LK OU T _ P C IE7 N
C L KO UT _ P C IE7 P
AF 4 7

   I
* 0 _ 04
27 P CH _ MU T E#
P CH _ M UT E# F10
G PIO 8    M R 27 6 1 0 K _0 4 3. 3V S

R 12 6 * 10 K _0 4 K9 U2
3. 3V L AN _ PH Y_ P W R _C T R L / GP IO1 2 A 2 0G AT E G A2 0 28
HO S T _ AL ER T #1 T7
BIO S_ R EC G PIO 1 5
3 .3 VS R 10 1 10K_04
R 2 70 * 1 0 K _0 4 AA2 AM 3
3 .3 VS S AT A 4 GP / G PIO 1 6 C L K O UT _ BC L K 0 _N / C LK OU T _ PC IE8 N B C L K _C P U _ N 4
GPI O1 7 F38 AM 1
BIOS RE COVERY R102 BC LK _ CPU _ P 4 R 256 * 10 K _ 0 4 1 .1 V S _ VT T

  s
T AC H 0 / G PIO 17 C L KO UT _ BC L K0 _ P / C L KO UT _ P C IE8 P
DISABLE----NO STUFF (DEFAULT) * 0 _ 04 B IO S_ RE C Y7 BG 1 0 H_ P E CI_ R R 26 0 * 1 0 m il _s ho rt _ 0 4
S CL O CK / G P IO 22    O PE CI H _ P E C I 4 , 28
ENABLE-----STUFF
   I
  m
H10 T1
/ GP IO2 4   P
R 27 7 1 0 K _0 4 3 .3 VS
M EM _ L ED RC IN#
   G
  a
KB C_ R ST # 2 8
S B_ BL O N AB1 2 BE1 0
12 SB _B L ON H _ CPUPW RG D 4

  r
G PIO 2 7 PR OC PW RG D
3 .3 VS
R 28 1 * 10 K _ 0 4 C RB _S V_ DE T
S PI_ C S # 2 V1 3    U BD 1 0 R 25 9 56_04 R 255 56 _ 0 4
   P
  g Sheet 19 of 42 CRB/SV DETECT R280 S T P_ PC I# M11
G PIO 2 8
   C
T HR M T RIP#

H _ TH R MTR IP#
1. 1V S_ VT T

  a
S TP _ PCI # / GP IO3 4

   i IBEXPEAK - M 6/9  NO STUFF [DETECT] 1 0 0 K_ 1 % _ 0 4 GPI O3 5 V6

S AT A C LK RE Q# / G P IO 3 5
Connected to PCH( THRM
Rou
TRIP#)
t i ng guideli nes avail able in

   D
R 27 9 * 1K_1% _04 AB7 BA2 2
3 .3 VS Calp ell a Desi gn Guide.
S AT A 2 GP / G PIO 3 6 T P1
DG P U _ PRS NT # AB1 3 AW 2 2 NOTE: CRB uses a 54.9 O ?%
S AT A 3 GP / G PIO 3 7 T P2

  c
R 95 10K_04 SV _S E T _ UP s e ri e s r e s i s t o r a n d 5 6 - O pu l l - u p .
3 .3 VS

   i
MF G _ M OD E V3 BB2 2
S LO A D / G P IO 3 8 T P3

   t R100 CR B _ SV_ D E T P3

S DAT A OU T 0 / G P IO 39 T P4
AY 4 5

  a * 0 _ 04 H3
P CIE CL KR Q 6# / GP IO4 5 T P5
AY 4 6

  m
DR A M RS T_C T RL F1 AV4 3
4 ,9 D RA MR ST _ C TR L P CIE CL KR Q 7# / GP IO4 6 T P6

  e
S V_ SET _ U P AB6 AV4 5
S DAT A OU T 1 / G P IO 48 T P7

   h
R 26 9 * 0_ 0 4 CR IT _ T EMP _R E P #_ R AA4 AF 1 3
3. 3V 3 C RI T_ T EM P _ R EP# S AT A 5 GP / G PIO 4 9 T P8

  c
R 12 8 1 0 K _0 4 P CH _ GPI O5 7 F8 M1 8
G PIO 5 7 T P9

   S
R 10 7 1 K _0 4 H OS T_ AL E RT # 1 N1 8
TP 10

 . RN 9
1 0 K_ 8 P 4 R _0 4
A4
A4 9 V SS_ N CT F _ 1
   D
TP 11
AJ 2 4

   B 1 8 A5 V SS_ N CT F _ 2 AK4 1

   V
P CH _ MU T E#
V SS_ N CT F _ 3 TP 12
   S
2 7 S P I_ CS #2 A5 0
3 6 D R A MR S T _ C TR L A5 2 V SS_ N CT F _ 4 AK4 2
4 5 A5 3 V SS_ N CT F _ 5    R TP 13
B2 V SS_ N CT F _ 6 M3 2
B4 V SS_ N CT F _ 7 TP 14
B5 2 V SS_ N CT F _ 8 N3 2
B5 3 V SS_ N CT F _ 9 TP 15
BE1 V SS_ N CT F _ 1 0 M3 0
3 .3 VS BE5 3 V SS_ N CT F _ 1 1 TP 16
BF1 V SS_ N CT F _ 1 2 N3 0
BF 5 3 V SS_ N CT F _ 1 3 TP 17
BH1 V SS_ N CT F _ 1 4 H1 2
R 1 14 * 1 0 K _0 4 G P IO 1 7
BH2 V SS_ N CT F _ 1 5 TP 18
BH 5 2 V SS_ N CT F _ 1 6    F AA2 3
R N2 1
1 0 K_ 8 P 4 R _0 4 BH 5 3 V SS_ N CT F _ 1 7    T TP 19
1 8 SC I# BJ 1 V SS_ N CT F _ 1 8    C AB4 5
2 7 SM I# BJ 2 V SS_ N CT F _ 1 9    N N C _1
3 6 MF G_ M OD E BJ 4 V SS_ N CT F _ 2 0 AB3 8
4 5 ST P_ PC I# BJ 4 9 V SS_ N CT F _ 2 1 N C _2
BJ 5 V SS_ N CT F _ 2 2 AB4 2
BJ 5 0 V SS_ N CT F _ 2 3 N C _3
RN 4
BJ 5 2 V SS_ N CT F _ 2 4 AB4 1
1 0 K_ 8 P 4 R _0 4
1 8 DG PU _ HP D_ IN TR# BJ 5 3 V SS_ N CT F _ 2 5 N C _4
2 7 CR IT _ T EM P_ RE P# _ R D1 V SS_ N CT F _ 2 6 T39
3 6 DG PU _ PR SNT # D2 V SS_ N CT F _ 2 7 N C _5
4 5 GP IO3 5 D53 V SS_ N CT F _ 2 8
E1 V SS_ N CT F _ 2 9 P6
E5 3 V SS_ N CT F _ 3 0 IN IT 3 _3 V#
V SS_ N CT F _ 3 1 C1 0
TP 24
I be x Pe a k -M _ Re v 0 _ 9
R 10 3 * 10 K _ 0 4 DG P U _ PR SN T #

LOW: DGPU PRESENT 2 ,4 ,6 ,7 ,1 4 ,1 5 , 1 6 ,2 0 ,2 1, 34 ,3 5 ,3 6 1 .1 VS _V T T

3 ,4 ,1 2 ,1 4 ,1 5 ,1 6 ,1 8, 20 ,2 1 ,2 3 ,2 4 ,2 5 ,2 9 ,3 0 ,3 1, 33 ,3 4 ,3 5 3 .3 V
2 ,1 0 ,1 1 ,1 2 ,1 3, 14 ,1 5 ,1 6 ,1 7 ,1 8 ,2 0 ,2 1, 23 ,2 4 ,2 5 ,2 6 ,2 7 ,2 8 ,2 9 ,3 0, 31 ,3 5 ,3 63 .3 VS

B - 20 IBEXPEAK - M 6/9
 Schematic Diagrams

IBEXPEAK - M 7/9
IBEXPEAK - M (POWER)
R90 3 .3 VS
H C B1 6 0 8K F -1 2 1 T2 5
.

1 .1 V S_ VT T VCC A_ D A C _ 3. 3V S L12 5 VS
U20G POWER  H CB1 6 0 8 KF - 12 1 T 2 5 U5
AB2 4
AB2 6 VC C CO R E[1 ] VC CA DAC [1 ]
AE5 0 . 5
OU T IN
1

C 17 6 C 1 51 AB2 8 VC C CO R E[2 ] AE5 2 C 3 93 C392 C1 3 2 C145 C 13 3 C1 4 6 R8 0 C 15 0

AD 2 6 VC C CO R E[3 ] VC CA DAC [2 ] 3    4
   0
VC C CO R E[4 ]    8 SHD N # _
   T
1 0 u _6 .3 V _X5 R _ 0 6 1u _ 6 .3 V_ X5 R _0 4 AD 2 8 AF 5 3 0 .0 1 u _ 50 V _X7 R _ 04    4    8
   0 1 0 u _ 6 .3 V_ X5R _ 0 6    4    0 *2 3 .7 K_ 1 % _ 0 4
VC C CO R E[5 ] VSSA _ DAC [1 ]    0    0    R
AF 2 6 _ _ 4 2
   R
_ _    5
AF 2 8 VC C CO R E[6 ] AF 5 1    V    R    V    R
   5 SET GN D    X

   E    C
   5    5    5 _
VC C CO R E[7 ] VSSA _ DAC [2 ]    Y    X    X    V

   R
AF 3 0 _ _
   Y
_ R8 1 * APL 5 6 0 3 -33 B    3
VC C CO R E[8 ] _  .
   V    V    V
   O
AF 3 1    6    3
   V
   3
   6
VC C CO R E[9 ]  .    6  . _
   1
   C
AH 2 6 _
   6    1
_
   6 *1 0 K_ 1 % _ 0 4    u
   1
AH 2 8 VC C CO R E[1 0 ] 3 .3 V S _ V C C A_ L VD    u _ 3 .3 VS    u _
   u     *
   u
VC C CO R E[1 1 ]    1    1    2
 .    2  .
   C
AH 3 0    2    2
VC C CO R E[1 2 ]
   0    0
APL5603-33B 6- 02-56033- 4C0
   C
AH 3 1 AH3 8 R 86 *1 5 m i _l s h o rt_ 0 6
VC C CO R E[1 3 ] V CC AL VD S G9091-330T11UF 6- 02-90913-4C0
   V
AJ 3 0
AJ 3 1 VC C CO R E[1 4 ] AH3 9

B 
C1 5 6
1 .1 V S_ VT T VC C CO R E[1 5 ] V SSA_ L VD S

1 0 u_ 6 .3 V_ X5 R _0 6

VC CT X_ L VD S[1 ]
VC CT X_ L VD S[2 ]
AP4 3
AP4 5
AT 4 6
1 .8 VS _V CC T X_ LV D
L 11
HC B1 6 0 8 KF -1 2 1 T 2 5
1 .8 VS
.
 S 
   S .
 c 
1. 1V S_ VC C AP L L_ E XP AK2 4 VC CT X_ L VD S[3 ] AT 4 5
L29 VC C IO[ 24 ]
   D VC CT X_ L VD S[4 ]

   V
h 
* BKP1 0 0 5 HS 12 1 _ 0 4 C1 4 0 C1 3 9 C135 C1 3 4
 . BJ 2 4
   L
C3 7 2
VC C APL L EXP
VC C3 _ 3 [2 ]
AB3 4 0. 01 u _ 5 0 V_ X7 R_ 0 4 0 .0 1u _ 5 0 V_ X7 R_ 0 4 1 0 u _ 6 .3 V_ X5 R_ 0 6 10 u _ 6 .3 V_ X5 R_ 0 6 Sheet 20 of 42  e
m
AN 2 0 AB3 5
*1 0 u _ 6 .3 V_ X5 R_ 0 6 AN 2 2
AN 2 3
VC C IO[
VC C IO[
25 ]
26 ]
   S
VC C3 _ 3 [3 ]
AD3 5 3 .3 VS IBEXPEAK - M 7/9
AN 2 4 VC C IO[ 27 ]
   O VC C3 _ 3 [4 ]
AN 2 6 VC C IO[
VC C IO[
28 ]
29 ]    M
   C  a
 t  
AN 2 8
VC C IO[ 30 ]
   V
i  
1 .1 VS_ VT T BJ 2 6 C1 5 9
BJ 2 8 VC C IO[ 31 ]
   H
AT 2 6
AT 2 8
VC C IO[
VC C IO[
VC C IO[
32 ]
33 ]
34 ]
0. 1u _ 1 6 V_ Y 5V _ 04
 c 
D
C3 7 5 C160 C 1 61 C1 3 6 C141 AU 2 6
AU 2 8 VC C IO[ 35 ] 1 .5 VS _ 1. 8V S
AV2 6 VC C IO[ 36 ]
1 0 u_ 6 .3 V_ X5 R _ 06 1 u _ 6 .3 V_ X5 R_ 0 4 1 u _ 6 .3 V_ X5R _ 0 4 1 u_ 6 .3 V_ X5 R _ 04 1 u _ 6 .3 V_ X 5 R_ 0 4

i  
AV2 8 VC C IO[ 37 ] AT 2 4

 a
AW26 VC C IO[ 38 ] VC C VRM [2 ]
AW28 VC C IO[ 39 ]

 g
VC C IO[ 40 ]
   I
BA2 6 AT 1 6 1 .1 VS _ VT T
VC C IO[ 41 ] VC C DM I[1 ]
   M
BA2 8

r 
VC C IO[ 42 ]
   D
BB2 6 AU1 6

 a
BB2 8 VC C IO[ 43 ] VC C DM I[2 ]
BC 2 6 VC C IO[ 44 ]
C1 2 7

m
VC C IO[ 45 ]
   *
BC 2 8
VC C IO[ 46 ]
   E
BD 2 6 1 u _ 6 .3 V_ X5 R_ 0 4
BD 2 8 VC C IO[ 47 ]
VC C IO[ 48 ]
   I
 s 
BE2 6 AM1 6
VC C IO[ 49 ] VC C PN AND [1 ]
   C
BE2 8 AK1 6
BG 2 6 VC C IO[ 50 ] VC C PN AND [2 ] AK2 0 V_ NV RAM _ VC CQ 1 .8 VS 3 .3 V S
BG 2 8 VC C IO[
VC C IO[
51 ]
52 ]
   P VC
VC
C
C
PN
PN
AND
AND
[3
[4
]
]
AK1 9
BH 2 7 AK1 5 R7 5 *0 _ 0 4
VC C IO[ 53 ] VC C PN AND [5 ] AK1 3
AN 3 0 VC C PN AND [6 ] AM1 2 C1 5 2 R76 * 1 5m i l _ s ho r t _0 6
VC C IO[ 54 ] VC C PN AND [7 ]
   I
AN 3 1 AM1 3
VC C IO[ 55 ] VC C PN AND [8 ]
   P
1 . 5 V S _1 . 8 V S 3 . 3V S AM1 5 0. 1u _ 1 6 V_ Y 5V _ 04
VC C PN AND [9 ]
AN 3 5
VC C 3 _3 [1 ]
   S
   /
1 .1 VS_ VT T 1. 1V S_ VC CAP L L_ F DI

   D
L 28 AT 2 2

   N
* HC B1 0 0 5 KF -1 2 1 T 2 0 VC C VR M[1 ] 3. 3V S 3 .3 V

   A
BJ 1 8 AM8 VC CM E3 .3 V
VC C F D IPL L VC C ME3 _ 3 [1 ]
   N
AM9 R 79 * 1 5 m il_ s h o rt_ 06
VC C ME3 _ 3 [2 ]
   I
C3 7 0 AM 2 3 AP1 1

   D
VC C IO[ 1] VC C ME3 _ 3 [3 ] AP9 R 82 * 0_ 0 4
VC C ME3 _ 3 [4 ]
*1 0 u _ 6. 3V _ X5 R _ 0 6
   F C1 3 8

Ib e x Pe a k -M _ Re v 0 _ 9 0 .1 u_ 1 6 V_ Y 5 V_ 0 4

1 .1 VS_ V TT 1 .1 VS_ VC CD PL L _ F D I

R25 7 * 1 5 mi l _ s ho rt _ 0 6

3 ,4 ,1 2 ,1 4 ,1 5 ,1 6, 18 ,1 9 ,2 1 , 2 3 ,2 4 ,2 5 ,2 9, 30 ,3 1 ,3 3 ,3 4 ,3 5 3 .3 V
2 3 ,3 1 ,3 6 1 .5 VS
2 ,1 3 ,1 7 ,2 1 ,2 6, 27 ,3 0 ,3 1 ,3 5 ,3 6 5 VS
21 1 .5 VS_ 1 .8 VS
7 ,3 3 1 .8 VS
2 ,1 0 ,1 1 ,1 2, 13 ,1 4 ,1 5 ,1 6 ,1 7 , 1 8 ,1 9, 21 ,2 3 ,2 4 ,2 5 ,2 6 ,2 7 ,2 8, 29 ,3 0 ,3 1 , 3 5 ,3 6 3 .3 VS
2 ,4 ,6 ,7 ,1 4 ,1 5 , 1 6, 19 ,2 1 ,3 4 ,3 5 ,3 6 1 .1 VS_ VT T

1 .5 VS 1 . 8 VS 1 .5 V S _ 1.8 V S

R 2 58 * 15 m il_ s h o rt_ 0 6
R 2 54 * 0 _0 4

IBEXPEAK - M 7/9 B - 21
 Schematic Diagrams

IBEXPEAK - M 8/9
 Volt age Rai l Volta ge S0 Iccm ax Curr ent (A )
IBEXPEAK - M (POWER)  V_CP U_IO 1.1/1. 05 < 1 (mA)
 V5RE F 5 < 1 (mA )
 V5RE F_Sus 5 < 1 (mA )
L3 2 1 .1 VS_ VCCA _C LK U2 0 J POWER  1 .1 V S_ VT T
 Vcc3 _3 3.3 0.357
*H C B 1 0 05 K F -1 2 1T 2 0 52mA  AP5 1 V2 4
 VccA Clk 1.05 0.052
1 .1 VS _ V TT VCC ACL K[1 ] VC CIO [5 ] V2 6
C3 8 3 C3 8 4 AP5 3 VC CIO [6 ] Y2 4 C1 4 7  VccA DAC 3.3 0.069
VCC ACL K[2 ] VC CIO [7 ] Y2 6
VC CIO [8 ]  VccA DPLLA 1.05 0.068
*1 0 u _6 .3 V_ X5 R _0 6 *0 .1 u_ 1 6 V_Y 5 V _0 4 1 u_ 6 .3 V_X5 R_ 0 4
AF 2 3 V2 8  VccA DPLLB 1.05 0.069
VCC LAN [1 ] VCC SUS 3_ 3 [1 ] U2 8 3 .3V
320mA  VCC SUS 3_ 3 [2 ]  Vcca pllEXP 1.05 0.040
1 .1VS _VT T
AF 2 4
VCC LAN [2 ] VCC SUS 3_ 3 [3 ]
U2 6
U2 4
142.6mA 
VCC SUS 3_ 3 [4 ]
 VccC ore 1.05 1.432
C1 4 3 P2 8
T P_ PCH _ VCC DSW Y2 0 VCC SUS 3_ 3 [5 ] P2 6 C1 8 1
 VccD MI 1.05 0.058
1 u_ 6 .3 V_X5 R_ 0 4 DCP SUSBY P VCC SUS 3_ 3 [6 ] N2 8
VCC SUS 3_ 3 [7 ] N2 6  VccD MI 1.1 0.061
C1 7 2 0 .1u _ 1 6V_ Y 5V_ 0 4
A D3 8 VCC SUS 3_ 3 [8 ] M2 8
VCC ME[1 ] VCC SUS 3_ 3 [9 ]  VccF DIPLL 1.05 0.037
0.1 u _ 16 V_ Y5 V_ 0 4 M2 6
A D3 9 VC CSU S3 _3 [1 0 ] L2 8
 VccI O 1.05 3.062
VCC ME[2 ] VC CSU S3 _3 [1 1 ] L2 6
1849mA     B VC CSU S3 _3 [1 2 ]
 VccL AN 1.05 0.320
A D4 1 J2 8
1 .1VS _VT T VCC ME[3 ]    S VC CSU S3 _3 [1 3 ] J2 6 3 .3 V_ VCC PUSB  VccM E 1.05 1.849

  s    U
C3 7 3 C1 4 8 AF 4 3 VC CSU S3 _3 [1 4 ] H2 8
VCC ME[4 ] VC CSU S3 _3 [1 5 ] H2 6
 VccM E3_3 3.3 0.085
R1 0 6 * 1 5 mi l _ sh or t _ 60
2 2u _ 6 .3V_ X 5 R_ 0 8 1u _ 6 .3V_ X5 R_ 0 4 AF 4 1 VC CSU S3 _3 [1 6 ] G2 8  Vccp NAND 1.8 0.156

  m
VCC ME[5 ] VC CSU S3 _3 [1 7 ] G2 6 C1 7 8
AF 4 2 VC CSU S3 _3 [1 8 ] F28  VccR TC 3.3 2 (mA)

  a
VCC ME[6 ] VC CSU S3 _3 [1 9 ] F26
V3 9 VC CSU S3 _3 [2 0 ] E2 8
0 .1u _ 1 6V_ Y 5V_ 0 4  VccS ATAPLL 1.05 0.031

  r
VCC ME[7 ] VC CSU S3 _3 [2 1 ] E2 6  VccS us3_3 3.3 0.163
V4 1   s VC CSU S3 _3 [2 2 ] C2 8

Sheet 21 of 42
C3 7 4 C1 4 2
  u  VccS usHDA 3.3 0.006

  g
VCC ME[8 ] VC CSU S3 _3 [2 3 ] C2 6
2 2u _ 6 .3V_ X 5 R_ 0 8 1u _ 6 .3V_ X5 R_ 0 4 V4 2   o VC CSU S3 _3 [2 4 ] B2 7 1.1 VS_ V T T
 VccV RM 1.8/1. 5 0.196
  e
  a
VCC ME[9 ] VC CSU S3 _3 [2 5 ] A2 8
  n  VccV RM 1.05 < 1 (mA )

   i IBEXPEAK - M 8/9 Y3 9

Y4 1
VCC ME[1 0 ]   a
   l
VC CSU S3 _3 [2 6 ]
VC CSU S3 _3 [2 7 ]
A2 6

U2 3
5 V_PC H_ VC C5 REF SU S
D 11
C
S C D 34 0
A
 VccA LVDS 3.3 < 1 (mA )
   l 3.3 V

   D
VCC ME[1 1 ] VC CSU S3 _3 [2 8 ]  VccT X_LVDS 1.8 0.059
Y4 2   e V2 3 R 12 3
1 .1 VS_ VT T C 1 77 0 . 1 u _1 6V _Y 5 V _ 0 4 VCC ME[1 2 ]   c VCC IO[5 6 ] 10 0 _ 1% _ 0 4
5V
  s
  c
L3 1 1.1 VS_ V C CA_ A _ DP L F24 C1 8 2
   i V 5 REF _ SUS

   i
HC B 10 0 5 KF -1 21 T 2 0
VCC RT CEXT V9    M 1 u_ 6 .3 V_X 5 R_ 0 4 D 10 S C D 34 0

   t
DCP RT C VCC 5 REF C A
C 3 86 C 38 1 1 .5 VS_ 1 .8VS    d 3 .3 VS

  a
R 2 62   n K4 9 R 11 6 1 0 0 _1 % _0 4
A U2 4   a V5 REF 5V S
2 2 u _6 .3 V _ X5 R _0 8 1 u _6 .3 V_ X5 R _0 4
* 0 _0 4
68mA  VCC VRM [3] C 1 83
   k    C
  m
L3 0 J3 8
1.1 VS _ VC CA_ B_ DPL BB5 1   c    P VCC 3_ 3 [8 ] 3. 3VS
HC B 10 0 5 KF -1 21 T 2 0 69mA  BB5 3 VCC ADPL L A[1 ]   o    L L3 8
1 u _ 6.3 V _ X 5R _ 04

  e
C1 6 9
VCC ADPL L A[2 ]    l    / VCC 3_ 3 [9 ]
C 3 85 C 37 8
   C    O M3 6 0 .1u _ 1 6V_ Y 5V_ 0 4

   h
+ C3 82 B D5 1    I VCC 3 _3 [1 0 ]
2 2 u _6 .3 V _ X5 R _0 8 1 u _6 .3 V_ X5 R _0 4 B D5 3 VCC ADPL L B[1 ]    P N3 6

  c
*2 20 u _ 4V_ V_ B VCC ADPL L B[2 ]    G VCC 3 _3 [1 1 ]
C 154 1 u_ 6. 3 V _X 5 R _0 4 A H2 3    / P3 6
AJ 3 5 VCC IO[2 1 ]    I VCC 3 _3 [1 2 ] 3. 3VS

   S    C
A H3 5 VCC IO[2 2 ] U3 5 C1 8 0

 .
VCC IO[2 3 ]    P VCC 3 _3 [1 3 ]
C 131 1 u_ 6. 3 V _X 5 R _0 4 AF 3 4 0 .1u _ 1 6V_ Y 5V_ 0 4
VCC IO[2 ] AD1 3

   B
 VCCIO 3062mA  A H3 4 VCC 3 _3 [1 4 ]
1 .1 VS_ VT T VCC IO[3 ] L3 3
C 157 1 u_ 6. 3 V _X 5 R _0 4 AF 3 2 1.1 VS_ V CC AP L L *HC B 1 00 5 KF -1 2 1T 2 0
VCC IO[4 ] AK3
VC CSAT AP L L [1 ] 1 .1VS_ VT T
V1 2 AK1
DCP SST VC CSAT AP L L [2 ]
C3 8 8 C3 8 9
C 1 75 0 . 1 u _1 6V _Y 5 V _ 0 4 VCC SST
*1 u _ 6.3 V_ X5R _ 04 *1 0 u_ 6 .3 V_X5 R_ 0 6
C 1 73 0 . 1 u _1 6V _Y 5 V _ 0 4 1 .1V_ IN T_ VC CSU S Y2 2
DCP SUS AH2 2
VC CIO [9 ]

20.4mA  P1 8 AT 20
3 .3 V VCC SUS3 _ 3[2 9 ] VCC VRM [4 ] 1 .5 VS_ 1 .8VS
C1 8 8 U1 9
VCC SUS3 _ 3[3 0 ] AH1 9
   C    A
   T
0.1 u _ 16 V_ Y5 V_ 0 4 U2 0 VCC IO[1 0 ]
VCC SUS3 _ 3[3 1 ]    P AD2 0
   L    A
   S
U2 2 VCC IO[1 1 ]
VCC SUS3 _ 3[3 2 ]    / AF 2 2 1 .1 V S_ VT T
   O VCC IO[1 2 ]
   I AD1 9
357mA  V1 5    P VCC IO[1 3 ] AF 2 0
3 .3 VS VCC 3_ 3 [5 ]    G VCC IO[1 4 ] AF 1 9 C1 6 7
C1 7 9 V1 6    / VCC IO[1 5 ] AH2 0
VCC 3_ 3 [6 ]    I VCC IO[1 6 ] 1 u_ 6 .3 V_X5 R_ 0 4
0.1 u _ 16 V_ Y5 V_ 0 4 Y1 6    C AB1 9 1 4 RT C V CC
VCC 3_ 3 [7 ]    P VCC IO[1 7 ] AB2 0 2 ,1 0,1 1 ,1 2,1 3 ,1 4,1 5 ,1 6, 17 ,1 8 , 19 ,2 0 ,23 ,2 4 ,25 ,2 6 ,27 ,2 8 ,29 ,3 0 ,31 ,3 5 ,3 63 . 3 V S
VCC IO[1 8 ] AB2 2 2 0 1 .5 VS_ 1 .8V S
V C C I O [ 1 9 ]   A D2 2 ,13 ,1 7 ,20 ,2 6 ,27 ,3 0 ,31 ,3 5 ,3 6 5 VS
<1mA  AT 1 8 VCC IO[2 0 ]
2
4,9 ,1 0 ,11 ,2 3 ,27 ,2 9 ,31 ,3 3 ,3 6 1 .5 V
1 .1VS_ VT T V_C PU_ IO [1] 24 ,3 0 ,31 ,3 3 ,3 4 5 V
AA3 4
VCCM E[1 3 ] 1.1 VS_ VT T 3 ,4 ,1 2, 14 ,1 5 ,16 ,1 8 ,19 ,2 0 ,23 ,2 4 ,25 ,2 9 ,30 ,3 1 ,33 ,3 4 ,3 53 .3 V
C1 4 4 C1 3 7 C1 6 2    U VCCM E[1 4 ]
Y3 4
2 ,4 ,6,7 ,1 4 ,15 ,1 6 ,19 ,2 0 ,34 ,3 5 ,3 6 1 .1 VS_ VT T
A U1 8
V_C PU_ IO [2]    P VCCM E[1 5 ]
Y3 5
1u _ 6 .3V_ X5 R_ 0 4 0 .1u _ 1 6V_ Y 5V_ 0 4 0.1 u _ 16 V_ Y5 V_ 0 4    C VCCM E[1 6 ]
AA3 5
1.5 V_ VCC SUSH DA 1 .5 V 3 .3V
2mA  A1 2 L3 0 R 1 29 * 1 5 mi l _ sh o r t _0 6
RT CVC C VCC RT C    C VC CSU SHDA
C1 8 6 C1 8 7    T HDA C1 8 9 R 13 1 * 0_ 0 4
   R
Ib ex Pe a k-M _ Re v 0 _9
0 .1u _ 1 6V_ Y 5V_ 0 4 0.1 u _ 16 V_ Y5 V_ 0 4 1 u _6 .3 V _ X5 R _0 4

B - 22 IBEXPEAK - M 8/9
 Schematic Diagrams

IBEXPEAK - M 9/9
U20I

IBEXPEAK - M (GND)  AY7

B11
B15
VSS[159]
VSS[160]
VSS[259]
VSS[260]
H49
H5
J24
B19 VSS[161] VSS[261] K11
B23 VSS[162] VSS[262] K43
B31 VSS[163] VSS[263] K47
B35 VSS[164] VSS[264] K7
B39 VSS[165] VSS[265] L14
B43 VSS[166] VSS[266] L18
B47 VSS[167] VSS[267] L2
B7 VSS[168] VSS[268] L22
BG12 VSS[169] VSS[269] L32
U20H
 AB16 BB12 VSS[170] VSS[270] L36
VSS[0] BB16 VSS[171] VSS[271] L40
 AA19  AK30 BB20 VSS[172] VSS[272] L52
 AA20 VSS[1] VSS[80]  AK31 BB24 VSS[173] VSS[273] M12
 AA22 VSS[2] VSS[81]  AK32 BB30 VSS[174] VSS[274] M16
 AM1 9 VSS[3] VSS[82]  AK34 BB34 VSS[175] VSS[275] M20
 AA24 VSS[4] VSS[83]  AK35 BB38 VSS[176] VSS[276] N38
 AA26 VSS[5] VSS[84]  AK38 BB42 VSS[177] VSS[277] M34
 AA28 VSS[6] VSS[85]  AK43 BB49 VSS[178] VSS[278] M38
 AA30 VSS[7] VSS[86]  AK46 BB5 VSS[179] VSS[279] M42
 AA31 VSS[8] VSS[87]  AK49 BC10 VSS[180] VSS[280] M46

B 
 AA32 VSS[9] VSS[88]  AK5 BC14 VSS[181] VSS[281] M49
 AB11 VSS[10] VSS[89]  AK8 BC18 VSS[182] VSS[282] M5
 AB15 VSS[11] VSS[90]  AL 2 BC2 VSS[183] VSS[283] M8
 AB23
 AB30
 AB31
VSS[12]
VSS[13]
VSS[14]
VSS[91]
VSS[92]
VSS[93]
 AL 52
 AM1 1
BB44
BC22
BC32
BC36
VSS[184]
VSS[185]
VSS[186]
VSS[284]
VSS[285]
VSS[286]
N24
P11
 AD15
.
 S 
 c 
 AB32 VSS[15] VSS[94]  AD 24 BC40 VSS[187] VSS[287] P22
 AB39 VSS[16] VSS[95]  AM2 0 BC44 VSS[188] VSS[288] P30

h 
 AB43 VSS[17] VSS[96]  AM2 2 BC52 VSS[189] VSS[289] P32
 AB47 VSS[18] VSS[97]  AM2 4 BH9 VSS[190] VSS[290] P34
 AB5
 AB8
VSS[19]
VSS[20]
VSS[98]
VSS[99]
 AM2 6
 AM2 8
BD48
BD49
VSS[191]
VSS[192]
VSS[291]
VSS[292]
P42
P45
Sheet 22 of 42  e
m
 AC 2 VSS[21] VSS[100] BA42 BD5 VSS[193] VSS[293] P47
 AC 52
 AD 11
 AD 12
VSS[22]
VSS[23]
VSS[24]
VSS[101]
VSS[102]
VSS[103]
 AM3 0
 AM3 1
 AM3 2
BE12
BE16
BE20
VSS[194]
VSS[195]
VSS[196]
VSS[294]
VSS[295]
VSS[296]
R2
R52
T12
IBEXPEAK - M 9/9
 AD 16
 AD 23
VSS[25]
VSS[26]
VSS[104]
VSS[105]
 AM3 4
 AM3 5
BE24
BE30
VSS[197]
VSS[198]
VSS[297]
VSS[298]
T41
T46  a
 AD 30
 AD 31
VSS[27]
VSS[28]
VSS[106]
VSS[107]
 AM3 8
 AM3 9
BE34
BE38
VSS[199]
VSS[200]
VSS[299]
VSS[300]
T49
T5  t  
i  
 c 
 AD 32 VSS[29] VSS[108]  AM4 2 BE42 VSS[201] VSS[301] T8
 AD 34 VSS[30] VSS[109]  AU 20 BE46 VSS[202] VSS[302] U30
 AU 22 VSS[31] VSS[110]  AM4 6 BE48 VSS[203] VSS[303] U31

D
 AD 42 VSS[32] VSS[111]  AV22 BE50 VSS[204] VSS[304] U32
 AD 46 VSS[33] VSS[112]  AM4 9 BE6 VSS[205] VSS[305] U34
VSS[34] VSS[113] VSS[206] VSS[306]

i  
 AD 49  AM7 BE8 P38
VSS[35] VSS[114] VSS[207] VSS[307]

 a
 AD 7  AA50 BF3 V11
 AE2 VSS[36] VSS[115] BB10 BF49 VSS[208] VSS[308] P16
 AE4 VSS[37] VSS[116]  AN 32 BF51 VSS[209] VSS[309] V19
 AF 12
Y13
VSS[38]
VSS[39]
VSS[117]
VSS[118]
 AN 50
 AN 52
BG18
BG24
VSS[210]
VSS[211]
VSS[310]
VSS[311]
V20
V22  g
r 
 AH 49 VSS[40] VSS[119]  AP12 BG4 VSS[212] VSS[312] V30

 a
 AU 4 VSS[41] VSS[120]  AP42 BG50 VSS[213] VSS[313] V31
 AF 35 VSS[42] VSS[121]  AP46 BH11 VSS[214] VSS[314] V32

m
 AP13 VSS[43] VSS[122]  AP49 BH15 VSS[215] VSS[315] V34
 AN 34 VSS[44] VSS[123]  AP5 BH19 VSS[216] VSS[316] V35
 AF 45 VSS[45] VSS[124]  AP8 BH23 VSS[217] VSS[317] V38
VSS[46] VSS[125] VSS[218] VSS[318]

 s 
 AF 46  AR 2 BH31 V43
 AF 49 VSS[47] VSS[126]  AR 52 BH35 VSS[219] VSS[319] V45
 AF 5 VSS[48] VSS[127]  AT11 BH39 VSS[220] VSS[320] V46
 AF 8 VSS[49] VSS[128] BA12 BH43 VSS[221] VSS[321] V47
 AG 2 VSS[50] VSS[129]  AH 48 BH47 VSS[222] VSS[322] V49
 AG 52 VSS[51] VSS[130]  AT32 BH7 VSS[223] VSS[323] V5
 AH 11 VSS[52] VSS[131]  AT36 C12 VSS[224] VSS[324] V7
 AH 15 VSS[53] VSS[132]  AT41 C50 VSS[225] VSS[325] V8
 AH 16 VSS[54] VSS[133]  AT47 D51 VSS[226] VSS[326] W2
 AH 24 VSS[55] VSS[134]  AT7 E12 VSS[227] VSS[327] W5 2
 AH 32 VSS[56] VSS[135]  AV12 E16 VSS[228] VSS[328] Y1 1
 AV18 VSS[57] VSS[136]  AV16 E20 VSS[229] VSS[329] Y1 2
 AH 43 VSS[58] VSS[137]  AV20 E24 VSS[230] VSS[330] Y1 5
 AH 47 VSS[59] VSS[138]  AV24 E30 VSS[231] VSS[331] Y1 9
 AH 7 VSS[60] VSS[139]  AV30 E34 VSS[232] VSS[332] Y2 3
 AJ 19 VSS[61] VSS[140]  AV34 E38 VSS[233] VSS[333] Y2 8
 AJ 2 VSS[62] VSS[141]  AV38 E42 VSS[234] VSS[334] Y3 0
 AJ 20 VSS[63] VSS[142]  AV42 E46 VSS[235] VSS[335] Y3 1
 AJ 22 VSS[64] VSS[143]  AV46 E48 VSS[236] VSS[336] Y3 2
 AJ 23 VSS[65] VSS[144]  AV49 E6 VSS[237] VSS[337] Y3 8
 AJ 26 VSS[66] VSS[145]  AV5 E8 VSS[238] VSS[338] Y4 3
 AJ 28 VSS[67] VSS[146]  AV8 F49 VSS[239] VSS[339] Y4 6
 AJ 32 VSS[68] VSS[147]  AW 14 F5 VSS[240] VSS[340] P49
 AJ 34 VSS[69] VSS[148]  AW 18 G10 VSS[241] VSS[341] Y5
 AT5 VSS[70] VSS[149]  AW 2 G14 VSS[242] VSS[342] Y6
 AJ 4 VSS[71] VSS[150] BF9 G18 VSS[243] VSS[343] Y8
 AK12 VSS[72] VSS[151]  AW 32 G2 VSS[244] VSS[344] P24
 AM4 1 VSS[73] VSS[152]  AW 36 G22 VSS[245] VSS[345] T43
 AN 19 VSS[74] VSS[153]  AW 40 G32 VSS[246] VSS[346]  AD51
 AK26 VSS[75] VSS[154]  AW 52 G36 VSS[247] VSS[347]  AT8
 AK22 VSS[76] VSS[155]  AY 11 G40 VSS[248] VSS[348]  AD47
 AK23 VSS[77] VSS[156]  AY 43 G44 VSS[249] VSS[349] Y4 7
 AK28 VSS[78] VSS[157]  AY 47 G52 VSS[250] VSS[350]  AT12
VSS[79] VSS[158]  AF3 9 VSS[251] VSS[351]  AM6
IbexPeak-M _Rev0_9 H16 VSS[252] VSS[352]  AT13
H20 VSS[253] VSS[353]  AM5
H30 VSS[254] VSS[354]  AK45
H34 VSS[255] VSS[355]  AK39
H38 VSS[256] VSS[356]  AV14
H42 VSS[257] VSS[366]
VSS[258]

IbexPeak-M_Rev 0_9

IBEXPEAK - M 9/9 B - 23
 Schematic Diagrams

New Card, Mini PCIE

3 .3 V

C 4 59 * 0 . 1u _1 6V _ Y 5 V _0 4 3 .3 V

 NEW CARD(Port 8) BUF _ PL T _R ST # 1

   5

4
U2 6
*M C7 4V HC1 G 08 D F T1 G
2 R 3 36 R 33 8 C2 1 0 C 2 24 C2 2 0

   3
* 1 00 K_ 1 %_ 0 4 * 10 0 K_ 1% _ 0 4 *0 .1 u_ 1 0 V_X7 R_ 0 4 * 0 .1u _ 1 0V_ X7 R_ 0 4 *0 .1 u_ 1 0 V_X7 R_ 0 4
1 .5 VS 3.3 VS 3 .3 V

U 25 J _ NEW 1
17 8 N C_ RST # N C_ PERST # 13
AU XIN PER ST # PER ST#
15 N C_ 3 .3VA UX 36mils 12
AUXOU T + 3.3 VAU X
2 3 N C_ 3 .3V 48mils 14
3 .3 VIN 3 .3 VOU T 15 + 3.3 V
+ 3.3 V

1 .5 VOU T
11 N C_ 1 .5V 48mils 10
+ 1.5 V
9
12 + 1.5 V
1 .5 VIN 10 NC _C PPE# 17
CPP E# 9 NC _C PUSB# 4 CPP E#

  s
CPUS B# PCIE_ W AKE# 11 CPU SB#
6 1 6 ,25 P C I E _ W A K E # 16 W AKE#
4 ,1 8 ,25 ,2 8 BUF _ PL T _R ST # 19 SY SRST # 1 5 NEW CAR D_ CL KRE Q# CL KR EQ#
1 8 U SB_ OC# 2 3 3 .3 VS R 1 70 1 0 K _0 4
OC # 19

  m 1 1 5 CL K_ PCIE _N EW _ CAR D 18 REF CL K+

1 6 ,2 8,3 1 SUS B# ST BY# 1 5 CL K_ PCIE_ N EW _ CAR D# REF CL K-

  a
R 34 7 1 0 K _0 4
3.3 V

  r
4 18 N C_ RC L KEN R 33 9 * 10 K _ 0 4 22
5 NC R CL KEN 20 N C_ SHD N# R 35 5 * 10 K _ 0 4 3 .3V 15 P CIE_ RXP2 _ NEW _ CA RD 21 PET p 0

Sheet 23 of 42 13 NC SH DN # 15 P CIE_ RXN2 _ NEW _C ARD 25 PET n 0 5

  g 14 NC 7 15 PCIE_ T XP2_ N EW _ CAR D 24 PER p0 R ESER VED 6

3 .3 VS 3 .3V 16 NC G ND 21 15 PCIE_ T XN2 _ NEW _ CAR D PER n0 R ESER VED
1 .5 VS

  a
NC G ND 3

New Card, Mini PCIE Port 3

   i
1 8 U SB_ PP3 2 USB _D +
* W 8 3L 3 5 1Y G
1 8 U SB_ PN3 USB _D - 1
GN D 20
6- 02-83351-9Q0
   D
C4 4 3 C4 6 4 C 45 1
GN D 23
8 GN D 26
*0 .1 u _1 6 V_ Y5 V _ 04 *0 .1 u_ 1 6 V_ Y5 V _ 04 *0 .1 u _1 6 V_ Y5 V_ 0 4
1 5 SM L0 _ DAT A 7 SMB _D AT A GN D G ND 1
ENE P2231 pin3,4,15,22

  c
1 5 SM L0 _ CL K SMB _C LK G ND1 G ND 2

   i
has internally G ND2

   t
* 13 0 8 01 -0 2
 pul led hig h (170K ohm)

  a
  m
  e  MINI CARD (WLAN,Port 5)
   h
  c
   S
Layout Show "WLAN(Wimax, 802.11N)" Note
20 mil
 .
3 .3 V

J _ MIN I1 W LAN 1 .5V 1.5 V

   B
PC IE_ W AKE# 1 2
3 W AKE# 3 .3VA UX_0 6 20 mil R3 2 5 * 1 5 mil _ s h o rt _ 06
R 31 2 1 0K _0 4 5 CO EX1 1 .5 V_0 8
3 .3V S CO EX2 UIM _ PW R 10 PC H_ BT _ EN#
R 39 7 0_ 0 4 C4 3 8
7 U IM_ DAT A 12
1 5 W L AN _C L KREQ # 11 CL KR EQ# U IM_ CL K 14
1 5 C L K_PC IE_ MIN I# *0 .1 u _1 6 V_ Y5 V _ 04
13 REF CL K- U IM_ RESET 16
1 5 C L K_P CIE_ MIN I 9 REF CL K+ U IM_ VPP
15 GN D0 4
GN D1 G ND5

KEY
21 18
27 GN D2 G ND6 26
29 GN D3 G ND7 34 R 32 6
GN D4 G ND8 40 3. 3VS
* 10 K_ 0 4
35 G ND9 50
28 W L AN_ DE T# 23 GN D1 1 G ND 10
15 PC IE_ RXN3 _ W L AN 25 PET n 0 20
1 5 PCIE _R XP 3_ WL AN 31 PET p 0 W _ DISA BLE# 22 W L AN _EN 2 8,29
BU F _P LT _ RST #
1 5 PCIE _T XN3 _ W L AN 33 PER n0 PER SET# 30
1 5 PCIE_ T XP 3_ W L AN PER p0 SMB_ CL K 32
17 SMB_ DAT A 36 BT _ DET # 2 8, 2 9

28 3 IN1
R 36 2 * 0 _ 0 4
28 8 0 DET # 19
37
Re s e rv e d0
Re s e rv e d1
U SB_ D-
USB_ D+
38
20 mil
U SB_P N2 1 8
U SB_P P2 1 8 Port 2
39 GN D1 2 24
3.3 V 3 .3 VAUX_ 1 R 32 9 * 15 m li_ s ho rt_ 0 6
R 35 9 0 _ 04 41 3 .3V AUX_ 3 3 .3VA UX_1 28 3 .3 V
2 8 ,29 BT_ EN 43 3 .3V AUX_ 4 1 .5 V_1 48
GN D1 3 1 .5 V_2
40 mil W LA N1 .5 V
M INI_ CL K1 45 52
M INI_ DAT A1 47 Re s e rv e d2 3 .3VA UX_2 42 3 .3V
M INI_ RST # 1 49 Re s e rv e d3 LE D_ W W AN# 44
20 mil
51 Re s e rv e d4 L ED_ W L AN# 46 W L AN_ L ED# 2 8 ,29
R 31 5 * 0_ 0 4
VD D3 Re s e rv e d5 LE D_ W PAN# 8 0 CLK 28
8 8 91 0 -5 20 4 M-0 1
R 39 6 0 _ 04
15 ,2 9 PCH _BT _ EN#

4 ,9,1 0 ,1 1,2 1 , 2 7,2 9 ,3 1, 33 ,3 6 1.5 V

2 0, 31 ,3 6 1.5 VS
3 ,4 ,12 ,1 4 ,15 , 1 6 ,18 ,1 9 ,20 ,2 1 ,2 4,2 5 , 2 9,3 0 ,3 1,3 3 ,3 4,3 5 3 .3 V
2,1 0 ,1 1,1 2 ,1 3, 14 ,1 5 , 16 ,1 7 ,18 ,1 9 ,20 ,2 1 ,24 ,2 5 , 2 6,2 7 ,2 8,2 9 ,3 0,3 1 ,3 5, 3 63 . 3 V S
1 4 ,2 5,2 8 ,2 9,3 1 ,3 2,3 7 V D D 3

B - 24 New Card, Mini PCIE

 Schematic Diagrams

3G, CCD, TPM

 MINI CARD 3G(Port 6) 3G POWER 
G5243A 6- 02- 05243- 9C0
Layout Show " 3.5G(HSDPA)" Note
3 G_ 3.3 V 3 .3V
APL3512A 6-02- 03512-9C0 3 G_ 3 .3V
3A 120mils U 12 3A 120mils
J _ 3G 1 5 1
60mils VIN VOU T
1 2
3 W AKE# 3.3 VAU X_ 0 6 2
5 CO EX1 1. 5V_ 0 8 U IM_ PW R G ND
CO EX2 UIM_ PW R 10 U IM_ DAT A 4 3
C1 90 R 1 76 * 1 5m li _ s ho rt_ 0 6 R1 7 3 C2 3 1
7 UIM _D AT A 12 U IM_ CL K C1 93 + C2 34 C2 4 1 SS EN
11 CL KR EQ# UIM _ CL K 14 U IM_ RST A P L3 5 12 A *1 0 0K _1 % _0 4 0 .1u _ 1 6V_ Y 5V_ 0 4
13 REF CL K- UIM _R ESET 16 U IM_ VPP 0.1 u _ 16 V_ Y5 V_ 04 0.1 u _1 6 V_ Y5 V_ 04 22 0 u_ 4 V_ V_B 1 0u _ 6.3 V_ X 5R _0 6 C2 30
9 REF CL K+ UIM _ VPP
15 GN D0 4 *0 .01 u _ 50 V_ X7 R _0 4
GN D1 GN D5

KEY
21 18
27 GN D2 GN D6 26
29 GN D3 GN D7 34 2 8 3 G _PO W ER
GN D4 GN D8 40
35 GN D9 50
28 3 G_ D ET# GN D1 1 GN D1 0 From SB GPIO Pin default HI
23
25 PET n 0 20 Power P lane: Suspend
31 PET p 0 W _ DISABL E# 22 3 G _E N 28

B 
L19
33 PER n0 PERSET # 30 S3: Defined
*W C M2 0 12 F 2 S-1 61 T 0 3-s h o rt
PER p0 SM B_ CL K 32 3 4
USB_ PN9 1 8

.
3 G_ 3 .3V 17 SM B_D AT A 36

 S 
19 Re s e rv ed 0 US B_D - 38 2 1
Re s e rv ed 1 U SB_ D+ U S B _P P 9 1 8
37
39 GN D1 2 24

Sheet 24 of 42
R 1 60 * 1 5 mi l _ sh o rt _ 06

 c 
41 3 .3V AUX_3 3.3 VAU X_ 1 28 3 G_ 3 .3V
C2 13 C4 14 43 3 .3V AUX_4 1. 5V_ 1 48
60mils SIM CONN
h 
45 GN D1 3 1. 5V_ 2 52

3G, CCD, TPM

47 Re s e rv ed 2 3.3 VAU X_ 2 42 3 G_ 3 .3 V
0.1 u _ 16 V_ Y5 V_ 04 10 u _6 .3 V_ X5 R _0 6

 e
49 Re s e rv ed 3 L ED _W W AN# 44 R 14 0 4 .7 K _ 0 4
51 Re s e rv ed 4 L ED_ W L AN# 46 C4 1 5

m
Re s e rv ed 5 L ED _W P AN# +C 19 8
8 8 91 0 -5 20 4 M-0 1 *0 .1 u _1 6 V_Y 5 V_0 4
2 2 0u _ 4 V_V_ B J_ SIM 1

R 32 2
* 10 m il _ s ho rt_ 0 4
LOCK
(TOP VIEW)
R 31 0
* 10 m il _ s ho rt_ 0 4  a
U IM_ CL K
U IM_ RST
C3
C2 U IM_ CL K U IM_ DAT A
C7
C6
U IM_ DAT A
U IM_ VPP  t  
i  
 c 
U IM_ PW R C1 U I M _R S T U IM_ VPP C5
C 42 4 U IM_ PW R U IM_ GN D
C 4 04 C 40 3 C4 0 5

D
2 2 p_ 5 0 V_N PO_ 0 4 OPEN
C1 77 0 6 61 -1 2 2 p _5 0 V_N PO_ 0 4 2 2 p _5 0 V_N PO_ 0 4 22 p _ 50V_ NP O _0 4
SIML OC K

i  
 a
TPM 1.2
3 .3 VS
 g
 Asserted before enteringS3    4
   0
_
   V
   4
   0
_
   4
   0
_
r 
 a
CCD
   V    V

m
   5
LPC reset timing:    Y
   5
   Y
   5
   Y
_ _ _

LPCPD# inactive to LRST# in active 3 2~96us

[PVT-1]    V
   6
   1
   V
   6
   V
   6
   1    1

 s 
_ _ _
   u    u 5V 5 V_ CC D
U14    u Q4
   1
 .    1
 .    1
 .
26 10    0
   0    0 C 27 2 MT P3 4 03 N3
1 4,2 8 L PC_ AD 0 23 L AD0 V DD1 19
    *     *     *
S D 48 mil
L1 * 15 m li _ s ho rt_ 0 6
1 4,2 8 L PC_ AD 1 20 L AD1 V DD2 24    7    6    0 *1 u _ 6.3 V_ X5R _0 4
1 4,2 8 L PC_ AD 2    7    5    8
17 L AD2 V DD3    2
   2    2
1 4,2 8 L PC_ AD 3 L AD3     C     C     C  MJ_CCD1
C3 C2 R9 C5 C8 C9
21     G
TPM  1
18 PC LK _T PM L CL K 3 .3 VS 1 u _6 .3 V_ X5 R_ 0 4 1 00 K_ 1 %_ 0 4 1 u _6 .3 V_X5 R_ 0 4 0 .1u _ 1 6V_ Y 5V_ 0 4 1 u_ 6 .3 V_X5 R_ 0 4
22 5 0 .1 u _1 6 V_ Y5 V _0 4
1 4 ,28 L PC_ F R AME# 16 L F RAM E# VSB R8 5
18 PL T _R ST # 27 L RESE T#
1 4 ,28 S E R I R Q C 25 5
15 SER IRQ 1 00 K_ 1% _ 0 4
16 PM _C L KRUN # C LKR UN #
* 0.1 u _1 6 V_ Y5 V_ 04 J _C CD1
R 19 9 * 0_ 0 4 T PM_ L PCPD # 28 6 T PM 30 0 4 R7 3 3 0K _ 0 4
1 6 S4 _ ST ATE# L PCPD # G PIO 2 T PM 30 0 5 1
9 G PIO2    D 18 USB_ PN5 2
T PM_ BAD D 18 USB _PP5
T EST BI/BADD 13 XTALI Q5 CCD _D ET # 3
TPM _ PP 7 XTAL I CCD _ EN G 2 8 C CD _D ET # 4
28 CC D_ EN MT N7 0 02 Z H S3
PP X4 5
14 XTALO 4 1     S
* MC - 14 6 _ 32.7 68 KH z 8 52 0 5-0 5 0 01
HI: A CCESS TPM 30 0 1 1 XT AL O 3 2
6- 22-32R76- 0B4 From H8 default HI
TPM 30 0 2 3 N C_ 1 4
TPM_PP C2 4 4 C 2 50
LOW: NORMAL( Internal PD) TPM 30 0 3 12 N C_ 2 G ND _1 11
N C_ 3 G ND _2 18 *1 8p _ 5 0V_ NPO _ 04 * 1 8p _ 50 V_ NPO _ 04
HI: 4E/ 4FH
8 G ND _3 25
TPM _BADD LOW: 2E/ 2F H T EST I G ND _4

* SL B96 3 5 TT
3 ,4 ,12 ,1 4 ,15 ,1 6 , 18 ,1 9,2 0 ,2 1,2 3 ,2 5,2 9 ,3 0,3 1 , 3 3,3 4 ,35 3 .3 V
XTAL O
PC LK_ T PM 2 ,1 0,1 1 ,12 ,1 3 ,14 ,1 5 , 16 ,1 7 ,18 ,1 9 ,20 ,2 1,2 3 ,2 5,2 6 ,2 7,2 8 , 2 9,3 0 ,3 1,3 5 ,36 3 . 3 V S
R 18 6 * 33 _0 4 C 266 * 10p _50 V_ NPO _06 2 1,3 0 ,3 1,3 3 ,34 5 V
XTAL I Co-l ayout X4, X9
3 .3V S
1 4 X9
T PM _L PC PD# R 20 0 * 10 K _0 4 2 3
*1 T J S12 5 DJ 4 A4 20 P_ 32 .7 6 8KH z
T PM _PP R 19 0 * 10 K _0 4
6-22- 32R76-0B2
T PM _BAD D R18 8 * 1 0 K _ 1% _ 0 4 6-22- 32R76-0BG
R18 5 * 1 0 K _ 1% _ 0 4

3G, CCD, TPM B - 25

 Schematic Diagrams

Card Reader/LAN JMB251C

SD _C L K

JMC251C C2 7 0 near Pi n#
41
Switching R egulator
close to PIN33
3 .3 V_ L AN

*1 0 p _5 0 V_ NPO _ 06 D VDD R 31 7 * 4 . 7K _0 4
3 .3 VS SD_ CL K R 18 7 2 2 _ 1 %_ 0 4 L3 5 U2 1
 . D V D D
(>20mil)
R EGL X L AN _SC L R 31 8 * 4 . 7K _0 4 8 7
R 31 4 * 4 . 7K _0 4 SD _ CD # VC C WP
(>20mil)
SD XC_ POW ER SW F 2 5 20 C F -4 R7 M-M C4 5 0 C 45 7 6
VC C_ C ARD L AN _SD A 5 SC L 1
   R
C2 7 1    0    1    E 10 u _ 6. 3V_ X5 R_ 0 6 0 .1 u_ 1 6 V_ Y5 V _ 0 4 SD A A0 2
   D   D    N   W
For JMC251/261 only A1
C276    1 Pi n#
33 Pi n#33 4 3
   1   E
   L    E    A
    O     S   3   2    1    X G ND A2
R 31 1 1 0K _0 4 S D_ W P 0 .1u _ 1 6 V_Y 5 V_ 04    L    L    0 VDD 3 3 .3 V
2 .2 u _ 6.3 V_ X5 R_ 0 6     O _ _ _   P    B   D    D   D   D    D    L
   I    N _ _ _ _    D     G
R 31 3 * 10 K _0 4 M S_ INS#    D   N   N    V _   D _   V    E * AT 24 C 02 BN
   A   A    O    3
    C    D   D    D   D
    S  .   X V DD3 3 .3 V
   M   L    L   I    3     S    S
    S    S    S   D    R
   D
Card Reader Pull High/Low     S
R 3 48 R 3 58
Resistors    4
   7    5   4   3    2   1    0    8    6    4    3
   8   4    4
   6   4   4   4    4   4    4   3
   9   3    3
   7   3   3
   5   3    3 * 1 5m il _s h o rt_ 06 * 0 _0 6
U 13 U27
   1   0
   1   N   D    5    4   3   2   1   0   2   D
R 1 77 R 3 54 DV DD 5 1 3.3 VS VD D3
   1
   D   D
    O    O
   I     O     O     O    1   N   L    X O UT IN
    O
   I    E   E
    O   N    I     O
   D   D    I
   I    O
   I
   I    O
   I    B
* 1 5m il_s h o rt _ 06 * 0_ 0 6
    S    G     G R 2 01 C 4 69
   L    L   I    D
   D   D    D   D    D   D   F
   D _ _    D   V
   V    M   M    M   M    M   M 3
   M   N   N
   A
(>20mil) S HD N#    4
M DIO 1 0 49    A
   L    L
32 * 2 K_ 1% _ 0 4    0
M PD R 3 20 1 00 K _1 %_ 04
50 MD IO1 0 VDD RE G 31 4 2 _
M DIO 9 (>20mil)    R
M DIO 8 51 MD IO9 VC C3 V 30 3 .3 VS SET G ND    5
VC C_ CAR D    X
R32 1 * 4. 7 K _ 04
R 35 1 * 15 m il_ s ho rt_ 0 6 A VDD 12 _ 5 2 52 MD IO8 PW RC R 29 R 1 98 *G 91 4 1 _
DVD D 53 VDD T EST 28 MPD    V
2 6 L AN_ M DIP0    3
VIP_ 1 MP D  .
   6
54 27 * 1 0K _1 % _ 04 C 2 39 0 . 1u _1 6V _ Y 5V _ 04

  s
2 6 L AN_ M DIN 0 VIN _1 W AKE N L AN_ PC IE_ W AKE# 2 8 _
R 35 0 * 15 m il_ s ho rt_ 0 6 A VDD 12 _ 5 5 5 5 26 LA N_ SCL    u
DVD D AVD D1 2 LA N_ L ED2    1
56 25 LA N_ SDA G9141
26 L AN_ M DIP1 57 VIP_ 2
JMC251 C CR _ LE D 24
APL5603- 12B(no R201,R198)
  m
26 L AN_ M DIN 1 58 VIN _2 R ST N 23 BUF _PL T _ RST # 4 ,1 8,2 3 ,2 8
59 GN D CPPE N 22

  a Sheet 25 of 42 3 .3 V_ LAN

2 6 L AN_ M DIP2
L AN _ MD IP2 6 0
L AN _ MD IN2 6 1
AVD D3 3
VIP_ 3 (LQFP 64)
GN D
V DDI O
21
20 SD_ W P
3 .3 V_L AN
(>20mil)
VD D3
(>20mil)
3.3 VS

  r
2 6 L AN_ M DIN 2 A VDD 12 _ 6 2 6 2 VIN _3 MD IO6 19 M DIO 12
DVD D R 34 9 * 15 m il_ s ho rt_ 0 6

Card Reader/LAN L AN _ MD IP3 6 3 AVD D1 2 MD IO1 2 18 MD IO1 4

  g
26 L AN_ M DIP3 VIP_ 4 MD IO1 4
L AN _ MD IN3 6 4 17 SD_ C D# C4 5 3 C 2 33 C 42 5 C2 3 7
26 L AN_ M DIN 3 VIN _4    N C R_ CD 0 N
   1

  a
   3
   3    2    2
   1   3

JMB251C
   1    1    D 1 0u _ 6 .3 V_X5 R_ 0 6 0 .1 u _1 6 V_ Y5 V _ 0 4 1 0 u _6 .3 V_ X5R _ 06 0. 1u _ 1 6V _Y 5 V_0 4

   i
   T   D    T    D    D    7
    C
   N   P     O    O Pi n#3
2 Pi n#
32 Pin#31 Pin#31
   X   D    U    N   D
   K   K   D   P    N   P   D   I    I _
   V   N    L    X
   E    I     O    L   V   X    N    X   X
   V   D    R
   D
3 .3V _L AN 3.3 V
   R   A   X   X
    C    C
   A   R
   R    G
   T   T   A   M   M     C

   D J MC 25 1 _ C
   1   2   3    4   5   6   7    8   9    0   1   2    3   4   5   6
   6
   1   1   1    1   1   1   1
PCIe Differential
Pairs = 100 Ohm  VDD 3
R 35 7 * 0_ 0 6

  c
   0
   3
_    1
   T    7   r
   t

   i
_
_     # ISON 3. 3V_ L AN
   N   U    2   o    2   3     S
28 ISON R 3 44 1 0 K _1 %_ 04

   t
   I     O    1   h    1    7
   X    s    D   1    N
   X    D _     O
    O   I
   N   N    l
   D   i    D   I   I _
   D R 1 92 * 1 0 0K _ 1% _0 4

  a
   A   A    V   m    V   D     S
R 20 2    L    L    A   5    A   M    M   M R31 9 1 0K _ 0 4
   1
    *
1 2 K_ 1% _ 0 4 D1 9
A C

  m
PC IE_ W AKE# LA N _ PCIE _W A KE#
   7    8   6
   2   0
1 6, 2 3 PC IE_ W AKE# LA N _ P C I E _W A K E # 2 8
   3
AVDD 1 2_ 7 AVD D1 2 _ 13    3    3

  e
_
   R    R   t
   r SCD 3 4 0
3 .3 V_ LAN    o
   h
   s

   h
   D    D _
   D   l
   i
   D
   V    V   m
C 44 9 C4 4 4    D    D   5
4 IN 1 SOCKET SD/MMC/MS/MS Pro
  c
   1
    *
0 .1 u_ 1 6 V_ Y5 V_ 0 4 0.1 u _ 16 V_ Y 5V _0 4 C 2 35 0 . 1u _ 1 0V _ X 7R _ 04
PC IE_ RXP4 _ GL AN 15

   S
Pi n#7 Pin#13 C 2 36 0 . 1u _ 1 0V _ X 7R _ 04
P CIE_ R XN 4 _G L AN 1 5

 .
J _C ARD -RE V1
SD _C D# P1
SD _D 2 P2 CD_SD

   B
AVDD 1 2_ 5 2 AVD D1 2 _ 55 AVDD 1 2_ 6 2 A VDD 12 _7 SD _D 3 P3 DAT 2 _S D
P CIE_ T XN4 _GL AN 15 Card Reader SD _BS P4 CD/ DAT 3 _S D
PC IE_ TXP4 _GL AN 1 5 P5 CMD _ SD
C L K_ PCIE_ G LA N 1 5 Power P6 VSS_ SD
C 28 6 C2 8 7 C 28 9 C4 4 7 C LK_ PC IE_ GL AN # 15 VC C_ CA RD VC C_ C ARD SD _C L K P7 VDD _S D
C4 2 0 P8 CL K_ SD
SD _D 0 P9 VSS_ SD
0 .1 u_ 1 6 V_ Y5 V_ 0 4 0.1 u _ 16 V_ Y 5V _0 4 0 .1 u_ 1 6 V_ Y5 V_ 0 4 *1 0 u _6 .3 V_ X5 R_ 0 6
Pi n#52 Pin#55 Pi n#62 Pi n#7 0 .1u _ 1 6V _Y 5 V_ 04 SD _D 1 P10 DAT 0 _S D
SD _W P P11 DAT 1 _S D
Reserved
L ANXO UT R 31 6 P12 W P_ SD
P13 VSS_ MS
For JMC251 C 7 5 _1 % _ 0 4
VC C_ C ARD SD _C L K P14 VCC _M S
3 .3 V_L AN P15 SCL K_ MS
R 18 4 * 1M _0 4 LAN XIN C4 1 3 SD _D 3
MS _IN S# P16 DAT 3 _M S
3 .3 V_ LA N P17 INS_ MS
X5 0 .1u _ 1 6V _Y 5 V_ 04 SD _D 2
2 1 SD _D 0 P18 DAT 2 _M S
C 28 8 C4 6 3 C 26 8 C 42 2 SD _D 1 P19 SDIO /DA T 0 _ MS
SD _BS P20 DAT 1 _M S P2 2
F SX5L _ 2 5 MH z
0 .1 u_ 1 6 V_ Y5 V_ 0 4 *0 .1 u_ 1 6 V_ Y5 V_ 0 4 C2 4 8 0 .1 u _ 16 V_ Y5 V_ 0 4 1 0u _ 6 .3 V_X5 R_ 0 6 P21 BS_ MS GN D P2 3
C2 6 1 VSS_ MS GN D
Pi n#43 Pin#43
2 2p _ 5 0 V_N PO _0 4 Pin#2 Pi n#
2 MD R0 1 9 -C0 -1 04 2
22 p _ 5 0V_ N PO_ 0 4

3 .3 V_L AN
6-22-25R00-1B4
6-22-25R00-1B5 VC C_ CAR D V CC _C ARD
C 28 5 C4 6 0 C 46 1 C2 4 0

*1 0 u _ 6.3 V_ X5 R_ 0 6 0.1 u _ 16 V_ Y 5V _0 4 0 .1 u_ 1 6 V_ Y5 V_ 0 4 0 .1 u_ 1 6 V_ Y5 V_ 0 4
Pi n#59 Pin#59 Pi n#2 Pi n#21 C4 2 3 C4 1 0 C 2 38 C4 1 9
Reserv ed
0 .1u _ 1 6V _Y 5 V_ 04 4. 7u _ 6 .3V _X5 R_ 0 6 0 .1 u _1 6 V_ Y5 V_ 0 4 0 .1u _ 1 6V _Y 5 V_ 04

Placeallcapacitors closedto chip.

The subscriptin each CAP incicates the pin  Near Cardreader CONN
numberofJMC251/JMC261that s hould be 1 4,2 3 ,2 8 ,29 ,3 1 ,3 2, 37 V D D 3
26 D VD D
closedto. 2, 10 ,1 1 ,1 2,1 3 ,1 4 ,15 ,1 6 ,1 7,1 8 ,1 9 ,20 ,2 1 ,2 3, 24 ,2 6 ,2 7,2 8 ,2 9 ,30 ,3 1 ,3 5,3 6 3 .3 VS
3,4 ,1 2 ,1 4,1 5 ,1 6 ,18 ,1 9 ,2 0, 21 ,2 3 ,2 4,2 9 ,3 0 ,31 ,3 3 , 3 4,3 5 3 .3 V

B - 26 Card Reader/LAN JMB251C

 Schematic Diagrams

LAN (JMC251C), SATA HDD, ODD

GIGA LAN (JMC251C)

L2 6 LP 2
* SB 0 40 2 TL -0 4 -0 sh o rt J _ RJ 1
L AN_ MD IP0 12 13 L MX1 + 1 8 D LM X1 + 1 G ND1
25 L AN_ M DIP0 11 T D4+ M X4+ 14 2 7 2 DA + sh iel d G ND2
L AN_ MD IN0 L MX1 - D LM X1 -
25 L AN_ M DIN 0 L AN_ MD IP1 9 T D4 - M X4- 16 L MX2 + 3 6 D LM X2 + 3 DA - sh iel d
25 L AN_ M DIP1 8 T D3+ M X3+ 17 4 5 6 DB +
L AN_ MD IN1 L MX2 - D LM X2 -
25 L AN_ M DIN 1 T D3 - M X3 - DB - GN  D

L AN_ MD IP2 6 19 L MX3 + R 36 7 0 _ 04 D LM X3 + 4

25 L AN_ M DIP2 5 T D2+ MX2 + 20 5 DC +
L AN_ MD IN2 L MX3 - R 36 8 0 _ 04 D LM X3 -
25 L AN_ M DIN 2 L AN_ MD IP3 3 T D2 - M X2- 22 L MX4 + R 36 9 0 _ 04 D LM X4 + 7 DC -
25 L AN_ M DIP3 L AN_ MD IN3 2 T D1+ MX1 + 23 L MX 4 - D LM X4 - 8 DD +
T D1 - MX1 - R 37 0 0 _ 04
25 L AN_ M DIN 3 DD -
DVD D 10 15 PJ S-0 8 SO1 B
7 T CT 4 MC T4 18
4 T CT 3 MC T3 21 D LM X3 + R 36 5 D LM X3-
1 T CT 2
T CT 1
MC
MC
T2
T1
24 D LM X4 + R 36 6
* 0_ 0 4
* 0_ 0 4 D LM X4- E4120 PJ S-08SL3B
R 28
P10 1 2
E5120Q PJ S-08S01B
* 0_ 0 4
GST5009 L F 6- 21-B4010-008
B 
N MC T_ 1 R 24 7 5 _1 % _ 04 N MCT _ R R 36 3 * 57 _ 1 % _0 4 D LM X3-
40mil N MC T_ 2 R 25 7 5 1_ %_ 40 R 36 4 * 57 _ 1 % _0 4 D LM X4-
N MC T_ 3 R 26 7 5 _1 % _ 04

.
   4    4    4    4 N MC T_ 4

 S 
   0
_    0    0    0 L6 2 R 32 7 5 _1 % _ 04
_ _ _
   R    R    R    R
   7    7    7    7 L AN_ MD IN0 7 10 L MX1 - C3 2 2

Sheet 26 of 42
   X    X    X    X

 c 
_ _ _ _ L AN_ MD IP0 8 T D+ T X+ 9 L MX1 +
   V
   0    V
   0    V
   0    V T D- T X-
   5    5    5
   0
   5
1 00 0 p _2KV _ X7R _ 12
4 12

h 
_ _ _ _
   u
   1    u
   1    u
   1    u
   1 5 NC NC 13
   0
 .    0
 .    0
 .    0
 . NC NC
LAN (JMC251C),
 e
   0    0    0    0
L AN_ MD IN1 1 16 L MX2 -
L AN_ MD IP1 2 R D+ RX+ 15 L MX2 +

SATA HDD, ODD m

R D- RX -
   1    8    6    4 3 14 NM CT _ 2
   3    2
   2    2 R D_ CT RX_C T NOTICE:
    C     C     C     C 6 11 NM CT _ 1

 a
T D_ C T T X_C T

FORJ MB251C GI GA LAN PARTS FORJ MB261C 10M/ 100M LAN PARTS
 t  
*P3 0 12

L26, L62 CO- LAYOUT

L26,LP1
C31,C28,C26,C24,C322
L62,L P2
C26,C24
i  
 c 
D
R24,R25,R26,R32,R367,R368,R369,R370 R24,R25,R363,R364

i  
 a
 g
r 
 a
m
SATA HDD
SATA ODD  s 
J _ HD D1
S1
S2 S ATA_ T XP0 C 42 1 0 .0 1 u_5 0 V_ X7 R_ 0 4 J _ OD D1
S3 S ATA_ T XN0 C 41 8 0 .0 1 u _50 V_ X7 R_ 04 SATA TXP0 1 4 S1
S4 SATA TXN0 1 4 S2 SAT A_ T XP 1 C3 8 0 0 . 0 1u _5 0 V _X 7 R _ 04 SAT AT XP1 14
S5 S ATA_ R XN 0 C 41 7 0 .0 1 u_5 0 V_ X7 R_ 0 4 S3 SAT A_ T XN 1 C3 7 9 0 . 0 1u _5 0 V _X 7 R _ 04
S6 S ATA_ R XP0 SATA RXN0 1 4 S4 SAT AT XN1 1 4
C 41 6 0 .0 1 u_5 0 V_ X7 R_ 0 4 SATA RXP0 14
S7 S5 SAT A_ RXN 1 C3 7 7 0 . 0 1u _5 0 V _X 7 R _ 04
S6 SAT A_ RXP1 SAT AR XN1 1 4
3 .3V S C3 7 6 0 . 0 1u _5 0 V _X 7 R _ 04 SAT AR XP1 1 4
S7
P1
P2
P3 C 41 2 C4 1 1
P4 P1 5 VS
P5 P2 OD D_ DET EC T# 1 4
*0 .0 1 u_ 5 0 V _ X7 R_ 0 4 *1 0 u _6 .3 V _ X5 R _0 6
P6 P3
P7 5VS P4
P8 P5 C3 6 1 C3 6 3 C 35 8 C 3 68 C3 6 6 C 36 5 C3 6 7
P9 P6 +
P1 0 *0 .1 u _1 6 V_ Y5 V_ 04 0. 1u _ 1 6V_ Y 5V_ 0 4 0 .1 u_ 1 6 V_Y 5 V_0 4 1 u _ 6.3 V_ X5R _ 04 1 0u _ 6. 3V_ X5 R_ 06 1 0 0u _ 6 .3V_ B_ A *0 .1 u _1 6 V_ Y5 V_ 04
P1 1 H DD _N C0    4    4    4    4    8    8
   0    0    0    0
_    0    0 C 1 8 55 3 -1 13 0 5 -L
P1 2 _ _ _ _ _ PIN GN D1 ~ 2 = G ND
   V    V    V    R    R    R
P1 3 H DD _N C1    5
   5    5    5    5    5
P1 4    Y    Y    Y    X    X    X
H DD _N C2 _ _ _ _ _ _
   V    V    V
P1 5 H DD _N C3    V    V    V
   6    6    6    3    3
   1    1    1
 .
   6
 .
   6
   3
 .
   6
+C2 0 3
_
   u _
   u _ _ _ _
   u    u
1 - 16 2 -1 00 5 6 1    1
 .    1
 .    1
 .    1    u
   2    u
   2
P IN G N D1 ~ 2 = G N D    0    0    0    2    2 *1 00 u _ 6. 3V_ B_ A

   9    8    6    7    2    1

5VS 2 ,1 3 ,17,2 0 ,21 ,2 7,30 ,31 ,35,3 6
6-20- 43740- 022    0
   4
    C
   0
   4
    C
   0
   4
    C
   0
   4
    C
   9
   1
    C
   9
   1
    C
5 VS D VD D
3.3 V
25
3 ,4 ,1 2,1 4,1 5,1 6 ,1 ,81 9 ,2 0, 21,2 3 ,24 ,2 5,29 ,3 0 ,31 ,3 3 ,34,3 5
1.5 V 4 ,9 ,1 0,1 1 ,2 ,12 3 ,2 ,72 9 ,3 1, 33 ,3 6
3.3 VS 2 ,1 0 ,11 ,1 2 ,13 ,1 4 ,15 ,1 6 ,17 ,1 8 ,1 9,2 0 ,2 1,2 3 ,2 4,2 5 ,2 7,2 8 ,2 9, 30 ,3 1 ,35 ,3 6

C 2 74 C 74 C 4 32

0 .0 1 u_ 5 0 V_X7 R_ 0 4 0 .0 1u _ 5 0V_ X7 R_ 0 4 0 .0 1 u_ 5 0 V_X7 R_ 0 4

LA N (JMC251C), SATA HDD, ODD B - 27