High Level Verification with SystemVerilog SV Datatype

SV Datatype Lab Exercise

Lab 10: Type Conversion and Streaming Exercise
Abhishek Kumar Singh | EVD18I031

Problem Statement
1. Create a user defined type, nibble_t , of 4 bits
2. Create a real variable, r , and initialize it to 4.33
3. Create a short int variable, i_pack
4. Create an unpacked array, k , containing 4 elements of your user defined type
nibble and initialize it to 4’h0, 4’hF, 4’hE, and 4’hD
5. Print out k
6. Stream k into i_pack right to left on a bit basis and print out i_pack
7. Stream k into i_pack right to left on a nibble basis and print out i_pack
8. Type convert real r into a nibble, assign it to k[0] 0], and print out k

Goal: Write SV code, simulate and verify manually. Submit your SV code and log

Solution
‘typedef ’ was used to create a user-defined datatype ‘nibble_t’. real and short int variables were
also created according to syntax rules. Unpacked array declaration was used to create a 4
element array k and initialized with given values.
Then array k is streamed into the i_pack variable. In bit-wise it’s 1011_0111_1111_0000. So
reading it from right to left, we have 0, 15, 14 and 13. In nibble-wise it’s 1101_1110_1111_0000.
So reading it from right to left, with 4 bits at a time, we have 0, 15, 14 and 13.
Finally r is converted from real type to nibble type and it’s assigned value k[0].

Simulation
module userdata();

typedef logic [3:0] nibble_t;

real r = 4.33;
shortint i_pack;

1
High Level Verification with SystemVerilog SV Datatype

nibble_t k[4] = '{4'h0, 4'hF, 4'hE, 4'hD};

initial begin

$display("---Array: k---");
foreach(k[i])
$display("%b", k[i]);

$display("---i_pack(bit basis)---");
i_pack = { <<{k}};
$display("%b", i_pack);

$display("---i_pack(nibble basis)---");
i_pack = { << nibble_t {k}};
$display("%b", i_pack);

$display("---Type conversion: r---");

r = nibble_t'(k[0]);
$display("%p", r);

$display("---Array: k---");
foreach(k[i])
$display("%b", k[i]);

end

endmodule

Log:
[2022-03-31 05:59:36 UTC] xrun -Q -unbuffered '-timescale' '1ns/1ns' '-sysv' '-access'
'+rw' design.sv testbench.sv
TOOL: xrun 20.09-s003: Started on Mar 31, 2022 at 01:59:37 EDT
xrun: 20.09-s003: (c) Copyright 1995-2020 Cadence Design Systems, Inc.
Top level design units:
userdata
xmelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009
SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV
2009 simulation semantics.
Loading snapshot worklib.userdata:sv .................... Done

2
High Level Verification with SystemVerilog SV Datatype

xmsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009

SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV
2009 simulation semantics.
xcelium> source /xcelium20.09/tools/xcelium/files/xmsimrc
xcelium> run
---Array: k---
0000
1111
1110
1101
---i_pack(bit basis)---
1011011111110000
---i_pack(nibble basis)---
1101111011110000
---Type conversion: r---
0
---Array: k---
0000
1111
1110
1101
xmsim: *W,RNQUIE: Simulation is complete.
xcelium> exit
TOOL: xrun 20.09-s003: Exiting on Mar 31, 2022 at 01:59:38 EDT (total: 00:00:01)
Done
★★★