SHESHADRI RAO

GUDLAVALLERU ENGINEERING COLLEGE

(An Autonomous Institute with Permanent Affiliation to JNTUK, Kakinada)
Seshadri Rao Knowledge Village, Gudlavalleru – 521 356, Krishna District
Department of Electronics and Communication Engineering

Registration for B. Tech Main Project Work

Academic Year: 2022

Date: 12-02-2022
Batch No: A16
Name of the Students:
1. B.ROOPA SREE – 18481A0412
2 B.YOGI – 18481A0422
3 CH.VAMSI KRISHNA – 18481A0427
4 D. BHAVANI SHANKAR – 18481A0445

Broad area of proposed project work: VLSI

Title of the proposed project work: Design of Power and Area Efficient
Approximate Multipliers

Abstract:

Approximate computing can decrease the design complexity with an increase in

performance and power efficiency for error resilient applications. This brief
deals with a new design approach for approximation of multipliers. The partial
products of the multiplier are altered to introduce varying probability terms.
Logic complexity of approximation is varied for the accumulation of altered
partial products based on their probability. The proposed approximation is
utilized in two variants of 16-bit multipliers. Synthesis results reveal that two
proposed multipliers achieve power savings of 72% and 38%, respectively,
compared to an exact multiplier. They have better precision when compared to
existing approximate multipliers. Mean relative error figures are as low for the
proposed approximate multipliers, which are better than the previous works.
Performance of the proposed multipliers is evaluated with an image processing
application, where one of the proposed models achieves the highest peak signal
to noise ratio.

Implementation tools required:

Software :Xilinx and MATLAB
Source code : verilog HDL

References:
1. V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, “Low-power digital
signal processing using approximate adders,” IEEE Trans. Comput.-
Aided Design Integr. Circuits Syst., vol. 32, no. 1, pp. 124–137,
Jan. 2013.
2 . E. J. King and E. E. Swartzlander, Jr., “Data-dependent truncation
scheme for parallel multipliers,” in Proc. 31st Asilomar Conf. Signals,
Circuits Syst., Nov. 1998, pp. 1178–1182.
3. J. Liang, J. Han, and F. Lombardi, “New metrics for the reliability of
approximate and probabilistic adders,” IEEE Trans. Comput., vol. 63,
no. 9, pp. 1760–1771, Sep. 2013.
4 . S. Suman et al., “Image enhancement using geometric mean filter and
gamma correction for WCE iamges,” in Proc. 21st Int. Conf., Neural
Inf. Process. (ICONIP), 2014, pp. 276–283.

Signature of the students

Remarks by the Guide:

Signature & Name of the guide with date

Signature of B. Tech. with Project Coordinator date

Signature of HoD with date