Need for Low power VLSI

1.Power dissipation of VLSI chips is traditionally a neglected subject. In

the past, the device density and operating frequency were low . As the
scale of integration improves, more transistors, faster and smaller than
their predecessors, are being packed into a chip. This leads to the steady
growth of the operating frequency and processing capacity per chip,
resulting in increased power dissipation.
2. There are various interpretations of the Moore s Law that predicts the
growth rate of integrated circuits. One estimate places the rate at 2X for
every eighteen months. A need for low power VLSI chips arises from
such evolution forces of integration circuits
3. Battery life is becoming a product differentiator in many portable
electronic markets. The craving for smaller, lighter and more durable
electronic products indirectly translates to low power requirements.
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4. High performance computing system characterized by large
power dissipation also drives the low power needs.
5. The power dissipation of high performance microprocessors
is now approaching several dozen Watts, comparable to that of
a hand-held soldering iron.
6. Power dissipation has a direct impact on the packaging cost
of the chip and the cooling cost of the system
7. A chip that operates at 3.3V consuming lOW means that the
average current is 3A. The transient current could be several
times larger than the average current. This creates problems in
the design of power supply rails and poses big challenges in the
analysis of digital noise immunity
8. Another major demand for low power chips and
systems comes from environmental concerns.
Computers are the fastest-growing electricity loads in the
commercial sector. Since electricity generation is a major
source of air pollution, inefficient energy usage in
computing equipment indirectly contributes to
environmental pollution.
The problem has prompted The US Environmental
Protection Agency and The US Department of Energy to
promote the Energy Star program
It’s the guidelines for the energy usage of computing
equipment.
There are three sourses of power dissipation in CMOS Circuits
● Logic Transitions : The nodes in the CMOS circuits changes
back and forth between two logic level, leading to the
charging and discharging og the Parasitic capacitance. This
leads to power consumption
● Its Proportional to the supply Voltage , Node voltage swing
,and the average switched capacitance / cycle
● A layer of Insulator of Width “d” is sandwiched between metal Plate
and the semiconductor material.
● Assume the semiconductor of P type
● Voltage V is applied between Metal plate and substrate
● First consider V= 0,
● The energy difference between metal work function
and the semiconductor work function is Zero.
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Body Effect
Body effect refers to the change in the transistor threshold voltage (VT) resulting
from a voltage difference between the transistor source and body.
Short Channel Effect
• MOSFET Device is considered to be short when the
channel length is the same order of magnitude as the
depletion layer width of the source and drain junction .

• As the Channel length ( L) is reduced to increase both

operation and speed , and no. of components per chip,
the so called short channel effect arise.
Drain-induced barrier lowering (DIBL)

The electrons (carriers) in the channel face a potential

barrier that blocks their flows

The potential barrier, in small-geometry MOSFETs, is

controlled by a two-dimensional electric field vector (in
other words by both VGS and VDS)

If the drain voltage is increased the potential barrier in

the channel decreases, leading to
Drain-Induced Barrier Lowering (DIBL)
Drain-induced barrier lowering (DIBL) and Punchthrough

Under DIBL condiction electrons can flow between the

source and drain even if VGS < VT

The channel current that flows in this case is called

subthreshold current

Punchthrough

The DIBL phenomenon can be accompanied by the

so-called punchthrough, that occurs when the depletion
region surrounding the drain extends to the source

Punchthrough minimized with thinner oxide, larger

substrate doping (and longer channel!)
Punch through. Punch through in
a MOSFET is an extreme case of channel
length modulation where the depletion layers
around the drain and source regions merge
into a single depletion region. The field
underneath the gate then becomes strongly
dependent on the drain-source voltage, as is
the drain current.
 Surface Scattering

• The velocity of the charge carriers is defined by the mobility of that

carrier times the electric field along the channel. When the carriers
travel along the channel, they are attracted to the surface by the
electric field created by the gate voltage.
• As a result, they keep crashing and bouncing against the surface,
during their travel, following a zig-zagging path. This effectively
reduces the surface mobility of the carriers, in comparison with their
bulk mobility.

• The change in carrier mobility impacts the current-voltage

relationship of the transistor.
 Velocity-Saturation

• From the physics of semiconductors it is proved that the velocity of

charge carriers is linearly proportional to the electric field and the
proportionality constant is called as mobility of carrier.

• But when we increase the electric field beyond certain velocity called
as the thermal velocity or saturated velocity the velocity of the
charge carrier does not change with electric field as shown in Figure
below.