ES - 626 Research Presentation

Floating Gate Flash Memories

Presented By:
Rutu Patel
Instructor: Kailash Prasad
Prof. Nihar R Mohapatra PhD Electrical Engineering
IIT Gandhinagar

nanoDC Lab 25th Nov 2019

Outline :
● Why Flash Memories?
○ History of Flash Memories
○ NOR and NAND flash memories
● NAND flash devices
○ read/ write (program) / erase operations
● Process Technology
● Multi Level Cell
● Scaling and Reliability issues in NAND flash.
● Flash Memories: Present and Future

nanoDC Lab 2/56

 Why NAND Flash Memories?

nanoDC Lab 3/56

History of Flash memory :

nanoDC Lab 4/56

Floating Gate Flash memory :

nanoDC Lab 5/56

NAND vs NOR Flash Array :

nanoDC Lab 6/56

Where Flash is being used

nanoDC Lab 7/56

Flash Memory Scaling Trends

Hwang’s Law:
Double Capacity of
Chip every Year

nanoDC Lab 8/56

Flash Memory Technology

nanoDC Lab 9/56

Flash in News

nanoDC Lab 10/60

 NAND Flash Memory
Device

nanoDC Lab 11/56

Requirement of NAND Flash Memory :

nanoDC Lab 12/56

Floating gate transistor as memory cell :

a) Floating gate transistor structure b) Energy band diagram for floating gate
transistor
nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 13/56
Erase and Program operations :

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 14/56
Energy Band Diagram for Erase and Program :

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 15/56
Read operation:

Principle of read of single cell

● Erased: +ve charge in FG. Icell “ON”.
● Programmed: -ve charge in FG. Icell “OFF”.
nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 16/56
Operations in NAND array:
Voltages applied to the NAND String :
(a) read a selected memory cell in the string
by applying VRX to WL

(b) program a selected memory cell in the

string by applying VP to WL

(c) Erase the entire nand block by applying

VSGR and VSGP are the voltages applied
to the gates of the biased select
transistors during read and program,
respectively.

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 17/56
Capacitive coupling of the floating gate:

is the voltage across

tunneling oxide when is 0.

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 18/56
Capacitive coupling of the floating gate:

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 19/56
 Process Technology

nanoDC Lab 20/56

NAND Flash memory Technology Road Map :

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 21/56
Flash Memory : The Driver of Lithography

Due to simple layout and Explosion in Demand

NAND Flash became the driver of Lithography
nanoDC Lab 22/56
Layout of NAND memory cells Array :

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 23/56
Structure scaling of NAND Flash Memory :

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 24/56
Scaling in LOCOS cell :

Issue Solution

Hatakeyama I. et al. “An advanced NAND-structure cell technology for reliable 3.3 V 64 Mb electrically erasable and programmable read only memories (EEPROMs),
nanoDC Lab Japanese Journal of Applied Physics, vol. 33, part 1, no. 1B, pp. 524–528, Jan. 1994. 25/56
Self-Aligned STI cell with FG wing (Fabrication) :

(a) Trench etching. (c) Floating gate formation by SiN spacer process.

(b) LPCVD SiO2 fill-in and planarization by CMP, second (d) ONO and the control-gate formation.
poly-Si gate deposited.

Takeuchi, Y.; Shimizu, K.; Narita, K.; Kamiya, E.; Yaegashi, T.; Amemiya, K.; Aritome, S. A self-aligned STI process integration for low cost and highly reliable 1 Gbit flash
nanoDC Lab memories, VLSI Technology, 1998. Digest of Technical Papers. 1998 Symposium on, pp. 102–103, 9–11 June 1998 26/56
Self-Aligned STI cell without FG wing (Fabrication) :
The process sequence of the SA-STI
process without FG wing.
(a) Trench etching, B+ implantation.
(b) LP-CVD SiO2 fill-in.
(c) Oxide etch-back and ONO formation.
(d) Control-gate formation.

The floating-gate and STI patterning are

carried out by the same mask, so the
number of fabrication steps for the SA-STI
process can be decreased.

Imamiya, K. et al; A 130 mm2 256 Mb NAND flash with shallow trench isolation technology, Solid-State Circuits Conference, 1999. Digest of Technical Papers. ISSCC. 1999
nanoDC Lab IEEE International, pp. 112–113, 1999. 27/56
Double patterning and Quadruple patterning :

nanoDC Lab 28/56

Dimensional Scaling of NAND Flash :

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 29/56
Planar FG cell with high k dielectric:

Ramaswamy, N.; Graettinger, T.; Puzzilli, G.; Liu H.; Prall, K.; Gowda, S.; Furnemont, A.; Changhan K.; Parat, K. Engineering a planar NAND cell scalable to 20nm and
nanoDC Lab beyond, Memory Workshop (IMW), 2013 5th IEEE International, pp. 5,8, 26–29 May 2013. 30/56
 Multi Level Cell

nanoDC Lab 31/56

Multi-level (Multi Vt) cells (MLC) :

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 32/56
Multi Level Cell - MLC

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 33/56
MLC vs SLC

nanoDC Lab 34/56

QLC

nanoDC Lab 35/56

 Scaling and Reliability Issues

nanoDC Lab 36/56

Scaling and Reliability Issues
● Floating gate capacitive coupling interference:
● Stress Induced Leakage Current (SILC)
● Endurance in MLC or TLC
● Few Electrons Limitations

nanoDC Lab 37/56

Floating gate capacitive coupling interference:

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 38/56
Floating gate capacitive coupling interference:

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 39/56
Air gap to reduce FG coupling interference:
The process flow of the air gap:
1. the gate patterning and the barrier
2. silicon dioxide deposition (150 A˚ ),
3. the barrier SiN deposition (200 A˚ )
4. thick-oxide deposition (1000 A˚ ),
5. thick oxide is removed by dry etch
6. SiN deposition (150 A˚ ),
7. the wing is formed,
8. the thick oxide inside gate to gate
space is removed by wet etch.
9. the air gap is formed.

nanoDC Lab S. Aritome. “NAND Flash Technology." 2015 IEEE Wiley Press 40/56
Stress Induced Leakage Current (SILC)

nanoDC Lab 41/56

Endurance in MLC or TLC

nanoDC Lab 42/56

ECC to Improve Endurance

nanoDC Lab 43/56

Few Electrons Limitations

nanoDC Lab 44/56

 Flash Memories: Present and Future

nanoDC Lab 45/56

3D NAND Cell

nanoDC Lab 46/56

3D NAND

nanoDC Lab 47/56

Basic Fabrication Steps

nanoDC Lab 48/56

Basic Fabrication Steps

nanoDC Lab 49/56

Flash Memory in Recent Times

nanoDC Lab 50/56

TechInsights memory technology update from IEDM’18

nanoDC Lab 51/56

Other References :
1. Masuoka, Fujio, et al. "New ultra high density EPROM and flash EEPROM with NAND structure cell." 1987 International
Electron Devices Meeting. IEEE, 1987.
2. Masuoka, Fujio, et al. "A new flash E 2 PROM cell using triple polysilicon technology." 1984 International Electron Devices
Meeting. IEEE, 1984.
3. Koh, Yohwan. "NAND flash scaling beyond 20nm." 2009 IEEE International Memory Workshop. IEEE, 2009.
4. Lai, Stefan K. "Flash memories: Successes and challenges." IBM Journal of Research and Development 52.4.5 (2008): 529-535.
5. Li, Yan, and Khandker N. Quader. "NAND flash memory: Challenges and opportunities." Computer 46.8 (2013): 23-29.
6. Compagnoni, Christian Monzio, et al. "Reviewing the evolution of the NAND Flash technology." Proceedings of the IEEE 105.9
(2017): 1609-1633.
7. Lee, Seok-Hee. "Technology scaling challenges and opportunities of memory devices." 2016 IEEE International Electron
Devices Meeting (IEDM). IEEE, 2016.

nanoDC Lab 52/56

 Thank You

nanoDC Lab