Making the move from 28nm

to 16nm FinFET - easy as POP

JC Yu
Technical Marketing Manager
Physical Design Group

ARM Tech Symposia 2016

Confidential © ARM 2016

 Agenda
 Why FinFET?
 How can 16FFC help?
 Differences in two technologies (planner versus FinFET)

 Implementation results using ARM’s latest core

 ARM Cortex-A73 using TSMC 28HPC+ and TSMC 16FFC process

 Key differences between two processes for floorplanning, power planning and
clock tree synthesis
 How we make physical design easier!

 Power, Performance and Area (PPA) differences using two processes TSMC
28HPC+ and 16FFC
2 Confidential © ARM 2016
 The new threshold for market leadership

2017
3.5+GHz
3.5GHz in 7nm

2016 7nm
3.0+GHz
3.0GHz+ in 16nm

16nm
2013
2.0+GHz
2.0GHz/28nm

28nm+

2010
1.0GHz
1.0 GHz / 40nm

Hisilicon,
40nm MediaTek,
Spreadtrum…
…have announced plans to move to 16nm
3 Confidential © ARM 2016
 What is a FinFET?
Drain
Source

Drain Gate Length (L)

Source

Gate Length (L) HFIN

WEFF , FINFET 2  H FIN  TFIN

3D Factor : 
WBULK FPITCH

Traditional bulk FinFET

4 Confidential © ARM 2016

 Standard cells and metal / fin gear ratio
 M2 pitch does not equal fin pitch
 Must consider required fin and M2 pitch
 Yields a limited number of cell heights
M2 grid  Need interger number of fins

7.5 M2 48nm Fin Pitch

 Designer wants 3 active p and n fins
grids
 Need 2 ‘dummy’ fins between active areas
 Need 1 ‘dummy’ fin at top and bottom boundary

 3p + 3n + 2 dummy + 2 boundary = 10 fins

 10 fins * 48nm fin pitch = 480nm cell height
90nm CPP  480nm height / 64nm M2 grid = 7.5 tracks
sample M2 (colinear poly pitch)
routes Note: Fin illustrations may have minor misalignments

Active (OD) Poly (PO) Fins M2 (M2x/xa) Boundary

5 Confidential © ARM 2016
 Trends for standard cell libraries
 Generational impact (node-to-smaller node)
 Performance: 12-track advantage vs 9-track has been decreasing
 Power: 12-track power disadvantage vs 9-track has been very slowly declining
 Performance and library impact
 Smaller geometries see performance SC12 Relative to SC9
gains over previous generation 1.40
 Allows larger percentages of SoC logic 1.35
to achieve target frequency with a 1.30
9-track library 1.25
 9-track high-density libraries still very useful 1.20

 7.5-track ultra-high density libraries enable area scaling 1.15

1.10

 The implication is the industry is focused 1.05

on shifting to smaller libraries 1.00

40nm 28nm 20nm 16nm

Performance Power

6 Confidential © ARM 2016

 Benchmarking FinFETs and ARM Cortex-A9
160000

 Top Frequency Comparison

sc10p5mc_ln14lpe_proto_lvt_c14
140000
 SC12/SC9: 1.08
 SC10P5/SC9: 1.07
sc12mc_ln14lpe_proto_lvt_c14
 Power Comparison at 1GHz
Total Power (uW)

120000  SC12/SC9: 1.27

sc9mc_ln14lpe_base_lvt_c14
 SC10P5/SC9: 1.11
 Power Comparison at 400MHz
100000  SC12/SC9: 1.42
 SC10P5/SC9: 1.19
 Partial finger devices not available which significantly
80000 hurts the power signature of the larger architectures
sc10p5mc
sc10p5mc_ln14lpe_proto_lv t_c14

60000 sc12mc
sc12mc_ln14lpe_proto_lv t_c14

sc9mc
sc9mc_ln14lpe_base_lvt_c14

Core Area (um^2)

40000
Minimum channel length
used for all runs
20000

0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

min(Achieved, Targeted) Clock Freq(GHz)

7 Confidential © ARM 2016

 Power and device tuning challenges
Drive Distribution FinFET versus Planar  Power tuning
35.00%  Dynamic power is tracking VDD scaling; little or
no benefit from device capacitance scaling
30.00%  Difficult to reduce power for “slow” design
FinFet  Limited choice for power-gated header/footer
25.00%
Planar devices
20.00%  Lack of body effect in FinFET

15.00%
 Device tuning
10.00%  True balanced beta ratios are not generally
possible
5.00%  Significant focus on low-power cells
 Benchmarking shows a significant reduction in the
0.00%
0.5 0.7 1 1.5 2 3 4 5 6 7 8 10 12 14 16
average drive strength usage in FinFET versus
Cell Drive Strength planar

8 Confidential © ARM 2016

 FinFET-based SRAM
Isigma/mean vs. Number of Fin
 Pros:
 Better current at same Vdd
4-5 fins needed for critical
 Low variability (as compared to planar) devices to reduce variations
 Lower leakage

Isigma/Imean
 Cons:
 Transistor width is a quantized number
 Read disturb, write tradeoff becomes
challenging
FinFET SRAM Bit PU PG PD Comments
Cell 0 5 10 15 20 25
Number of Fin
Cell 1: No. of Fins 1 1 1 High Variation; possible
READ and Write Margin
Cell 2: No. of Fins 1 2 2 concern Variation goes up with less Fin
Cell 3: No. of Fins 1 3 3 PU variation may lead to
READ Margin issue

9 Confidential © ARM 2016

 Implementation experiment details
for ARM Cortex-A73

10 Confidential © ARM 2016

 Advanced EDA flows and FinFET effects
ARM Artisan
Power Grid Simulation
Architect New Signoff
Synthesis/Test LEC Recommendations
Insertion
Power network is DRC/LVS/DFM
critical for Floorplanning
Floorplannng SBOCV
utilization Timing Analysis

Placement Signal Integrity

Complex Power
CTS Power/IR Analysis Networks
Double pattern
typical M1 to M3 Routing
Use latest tool
ATPG
versions

11 Confidential © ARM 2016

 Floorplan exploration: Cortex-A73
A73 floorplan using 28HPC+ A73 floorplan using 16FFC

12 Confidential © ARM 2016

 FinFET challenges for power grid design
 Double pattern M1, M2 and M3
 Half-track libraries
 Different rails for VDD and VSS
 Sometimes V1 needs to be inserted
post-route
 Pitch misalignment
 Complex DRCs
 Row end, top/bottom, and corner
cap boundary cells are required  Alternate power rails are supported to optimize
Default usage of PnR tool power grid network based on design power density
commands will not create correct  Upper picture: M2 totem example
grids  Lower picture: M2 totem with M3 or M5 strap

13 Confidential © ARM 2016

 ARM Artisan Power Grid Architect
 ARM Power Grid Architect (PGA)
automates critical aspects of floorplanning
 Extremely critical for FinFET and double pattern
designs
 Useful for complex power grids in 28nm
 Considers ARM recommended structures
and ARM Artisan Physical IP
 Insert power grids and power gates
 Stitch together power gate sleep signals
 Insert boundary finishing cells as needed
 Detect orphan row or placement site violations
 PGA runs on industry standard floor Example of power network
planning tools with power gating
14 Confidential © ARM 2016
 Special library cells – boundary finishing cells
 Boundary finishing cells included to  Placement options:
support design rules for block edges  By designer using code snipets in user
guide
 A = CNRCAP  By ARM Power Grid Architect
 Placed in outer corners of a block A
NWELL
D A
 B = INCNRCAP
C
Placed at inside corners of an L-shaped
NWELL
 C
block B D A
C = ENDCAP
NWELL

 A D B
 Placed at the ends of rows
NWELL C
 D = TBCAP C
 Placed above and below the top and NWELL

bottom rows of a block A D A

15 Confidential © ARM 2016
 ARM POP IP – clock tree synthesis
 Choosing the optimal clock-tree components – BUF vs INV, driving strength
 Use INV cells, not BUF cells
 Use the lowest VT and shortest channel length available
 Clock nets NDR guideline – width and spacing
 Guidelines for routing layers, shielding, max. transition
 Recommendation for buffer drive strength, VT selection
and channel length
 CTS based on MCMM analysis

16 Confidential © ARM 2016

 Routing guidelines
Do
 Use the placement and routing options contained within ARMTech
 TCL files for ICC and EDI
 Use the latest versions of the tools in most cases
 Carefully design power grid for optimal routing
 Complete placement of design including FILLer cells before routing

Do not
 Do not route on M1
Staggered pins for
 M1 outside of pin shapes can cause unfixable double-pattern violations
horizontal M2 route
 Do not route using wrong-way routing on double pattern layers access
(M2/M3)
 Okay for router to use small wrong-way jogs

17 Confidential © ARM 2016

 16FF signoff overview
ARM recommendations are consistent with TSMC recommendations
 Control over-margining; address variation
 Signoff with SBOCV derates
 No more using a single OCV value for a
design
 SBOCV* accounts for local variation
 Per cell derate values
 Based on path depth and PVT corner
 Variation decreases as path increases
 Variation increases as voltage decreases
Variations at Low Voltage
Variations at Nominal Voltage
(Vnom-20%)
18 Confidential © ARM 2016
 Standard signoff corners
 Setup+Hold: hot+cold SSGNP+SBOCV*
 Hold only: hot+cold FFGNP+SBOCV*
 Stage-based OCV (SBOCV) tables
 Derate tables go in a side file
 Four tables for each cell: early, late, rise,
fall
 Statistical Hold Constraint Margin
(SHCM)
 Includes local variation margin in hold and
recovery constraint tables in the Liberty
model
*SBOCV requires using SHCM or additional
margin for hold
 What is POP IP ?
POP Components
 Includes all ARM Artisan Physical IP products that
are required to build a processor POP
Artisan
Reference
Physical IP
 ARM POP IP assists you in rapid product Scripts
development by minimizing the Time to Market CPU Optimized RTL-GDS scripts for major
(TTM) and achieve best-in-class Physical IP EDA tool-chains
 Performance
 Power
 and Area (PPA) Artisan
POP User Architect
 ARM POP IP does not provide RTL deliverables Guide Products
Comprehensive Design utilities to
 Customer can configure the RTL and use ARM Implementation improve your implementation
POP IP deliverables during the implementation Methodology (delivered separately)
phase of design

19 Confidential © ARM 2016

19
 Summary
 Moving from TSMC 28nm to TSMC 16nm FinFET can be done easily:
 9 track or10.5 track architecture for standard cells gives similar performance vs. 12 track
 For easer power grid creation and DRC fixing, use ARM’s Power Grid Architect
 Inverter usage is recommended for clock tree synthesis
 Use ENDCAP cells to meet DRC requirement at 16nm
 Signoff with SBOCV derates

 Artisan POP IP for Cortex-A73 on TSMC 16FFLL+ achieves 3GHz frequency for
mobile applications

20 Confidential © ARM 2016

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trademarks of their respective owners.
Copyright © 2016 ARM Limited

Confidential © ARM 2016