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8ISUss about the Register 1onsfer Arithemetic MitO Dpetotots

teim
eqister ttancfer efons lo the avaliability of h01dwo1e togic CisruiIS that can peiform
e qiven micio-opeiation and t\ansfer the result of the operu tion to the some or another
eqister In qeneva the Avithmetie Micto-operations deols wih the operotion s perttimed on

numeii dota stoied in the (0qisteis.

he basnc Anthemattc Mi(tO opei ations

-

ate cla CiBied in following Co togorles.

Addition
()Subtaction.
)inaement.
(4 eement
5)
hift
seme additional Arithemehit Micn0 -oparaions en ate clatfred as
Add wt th tary
2) Su btoct with BonDw

)ransfer / Ldad etc

he
oltouinq tabie thDws the symbotic repretentation of vanout Arithmetit Micto-operahions.

Symbol 0esripnion.
0) R3+ Rii Rz ihe Contents of R plus R2 transferted to
ae R3

R3- Ri-Ra The Contents of R1 minus R2 0te transfered to R3.

3) R2RI Complement the con tents of R2 (a's Complement)

's Complement the lontents of R2 (neqate)

6) R3R1 R24
RI plus the 'S Complement of R2 subhochon)

6) R1 RI 41
nctement Conteos of RI bq one

7)RI R1-1 Oeement Contentt of R by one.

p l a n the opeotions df Stngte Bus Achilecute of CPu.

nComputer aichitectune, a bus fs a Su bsystem hot tionsfers doto betweep the

tomponents ntide a Computer, or betucen (omputers. Earty computtr butes Dere era y
parotel elechi co ws with muitiple Conneetlons, but moden Computor kyses Con use ou

Paronel and bit serial Conne chions.

h one bus or qaniaation, a sinqle bus is uted tor myttiple putpoces. A set of

Eera pupose Pqisters, progiam Counters, nstauc tion

rog1sters, mem oru ddoess s e
Emory dotdi ieqisleNS ate Connected ith Sinale bug. Memou reod/write con be done
A R and MDR, The pioqram counterpoints to the mempry toeation Atow uhere the
hext is ingtruction td be tetched.
emonshate the proces of CoOertingq ldqical addiess tnto phusical 0ddres.
t h e Concept ofa loqical addiess epoce thot is bound toa seperote physica) oddegs

space is centrol to pioper memory monagement.

*tdqical address - qeneated by CPU, TefBered as vittual 0ddress.

P'hytital address- addiess Seen by memory unit.

fdqica and physiCal addiess eg are the same fn comprle time end 100 the Gddiets
btndin4 schemes, tdqical and phyticat oddresses dlffer id ee cution tine addres
btndinq scheme
There ate 3 stops to translote togical address to physial addres

Stepi Find the index fteld rom the seqment Sectó and use the inder fhed to tocato
the seqment destripti oi soqment in glbbal detciptor toble (4o1)

Step2 1et the aces and imit the tteld of destaiptoi to make sure thot the seqmem
ig octessible and the offset is wilhin the limit of the togment.

Step 3 The base addtess of the eqment wll be obtalned tom the segment

descnpte. hen the base o ddiens oseqment be added to offset to detormioe

tinear addiecs
4nter the operohan of Cache memery boed ontheir storoqe funchoning ond mogpnq 1ethniques.

Cache meêmony 1s o Speciot veny biqh speed memon. 71 Used to speed up and

9hrop11nq wtth hrgh speed cpu 1 tostilier tHan dfsk memou o1 maio memoiy
but
eco0 omical than CrU reqisters, There ale vatous independent catches in a CPU,

thich Stbre
in cISuction ond d0ta.
Cache Mappinq
ihee aie three doftenent ypes of ma pring used toi purpose of Cothe memoy wh ae

toltows () Btecd mapping

) ASSdCiative maPpîna

3)9et Astociattve mapping.