Capital University of Science and Technology

Department of Electrical Engineering

EE4273: ASIC Design, Fall 2021

Assignment No. 2
Instructor: Dr. M.Tahir Awan Date: 23/11/2021
Total Marks: 100 Due Date: 01/12/2021

Instructions:

• Late submission is not allowed.

• This is an individual assignment.
• Submit Software Verilog Files for Programming Problems
• Submission Path for Verilog Files: Google Classroom
• Written part will be submitted in class in hand-writing
• Copied assignments will get Zero credit.

Q # 1. (20-Points)
(a). Write Verilog module in behavioral modeling for a 16-bit Random Number Generator.
Internally, module will use two 16-bit random number generators and select among them
based on output of a 4-bit Johnson counter. If output of the counter is multiple of 2, select 1st
random number, otherwise select 2nd random number. Random number generator should
use 5 XOR gates. Initialize first RNG with 16’h9090 and second RNG with 16’h0707.
(b). Write Stimulus module for testing of the 16-bit random number generator. Stimulus will
generate and give Clock and Reset signals to the random number generator and displays
generated random numbers on the screen using $monitor. Stimulus should display 10
random numbers on the screen.

Q # 2. (20-Points)
(a). Write Verilog module in Behavioral Modeling for a parameterized Clock Divider. Clock
Divider will use two parameters. One parameter will control output clock frequency and 2nd
parameter will control output Clock duty cycle.
parameter DivideFactor = X , parameter DutyCycle =Y
(b). Write a test-bench in Verilog, that will test the parameterized Clock divider for dividing
the input clock by 8 with duty cycle 25% and 20 with duty cycle 75%. It will also display
input and output clocks using $monitor.

Q # 3. (20-Points)
(a). Write Verilog module in Behavioral Modeling for a parameterized adder/subtractor.
Design can add or subtract N-bit numbers based upon an input control signal.

(b). Write an automated stimulus module in Behavioral Modeling that will exhaustively test
the parameterized module for adder/subtractor in part (a). Automated test-bench will only

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display inputs and outputs combinations on screen, when there is a mismatch between the
design module output and the simulated model results.

Q # 4. (20-Points)

(a). Convert the following no.’s from Qn.m fixed point format to decimal fractions ?

» 10011101 in Q3.5 unsigned format

» 11001011 in Q2.6 signed format

» 11011001 in Q4.4 unsigned format

(b). Convert the following decimal fractions to signed Qn.m format ?

» 4.537 to Q4.4 fixed point format

» -1.258 to Q3.5 fixed point format

» -0.6145 to Q1.15 fixed point format

(c). Find the appropriate Qn.m format for given fractional data. Chosen Qn.m format
should represent the data in minimum possible bits?
» -14.315 in signed Qn.m format ?

» 139.55 in unsigned Qn.m format ?

» 0.001265 in signed Qn.m format ?

» Data-set { -1.25, 13.125, 0.0125, -3.0125, 21.125 } in signed Qn.m format ?

Q # 5. For the two arrays X[4] and Y[4] do the following : (20-Points)

X[4] = { 0.125, -1.020, 0.721 , -0.420}

Y[4] = { -0.650, 1.53 , 1.150 , -1.613 }

(a). Convert the array X[4] into signed Q1.3 format and array Y[4] into signed Q2.2
format

(b). Compute Z in fixed point arithmetic. If there is any overflow during the
computation, saturate the result. Also evaluate, what will be the Q format of Z?
Convert Z back to decimal as well ?

Z = X[0]*Y[3] + X[1]*Y[2] + X[2]*Y[1] + X[3]*Y[0]

(c ). Compute Z in floating point arithmetic and compare it with the answer in part
(b) to find the error.

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