Finite State Machine

Computer Architecture

CS2201 - 2021I
1
PROF.: JGONZALEZ@UTEC.EDU.PE
 Executive Summary
2

• Motivation: Combinational and sequential circuits allow us to define

larger designs.
• Problem: We need to review Verilog for implementing Finite State
Machines.
• Overview:
- Review timing concepts for sequential circuits.
- Finite State Machine implementation and testing.
• Conclusion: We can implement a complex idea as a digital system using
a FSM.

COMPUTER SCIENCE DEPARTMENT

 Outline
3

Introduction

Timing for Sequential Logic

Implementing and Testing Finite State Machines

Conclusions

COMPUTER SCIENCE DEPARTMENT

 Outline
4

Introduction

Timing for Sequential Logic

Implementing and Testing Finite State Machines

Conclusions

COMPUTER SCIENCE DEPARTMENT

 Recall: Circuit Timing
5
• Delay is the time between input change
and output changing
A Y
• Main causes:
• Capacitance and resistance in a circuit
delay • Close to speed of light limitation
A
• Two main types of delay:
Y • Propagation delay tpd : max delay from
input to output
Time • Contamination delay tcd :min delay
from input to output

COMPUTER SCIENCE DEPARTMENT

 Recall: Circuit Timing
6
• Delay is the time between input change
A Y and output changing
• Main causes:
tpd • Capacitance and resistance in a circuit
• Close to speed of light limitation
A

• Two main types of delay:

Y
• Propagation delay tpd : max delay from
tcd input to output
• Contamination delay tcd :min delay
Time
from input to output

COMPUTER SCIENCE DEPARTMENT

 Recall: Critical Path
7
Can be determined with the propagation and contamination delay.
• Critical (Long) Path: tpd = 2tpd_AND + tpd_OR
• Short Path: tcd = tcd_AND

Critical Path

A n1
B
n2
C
D Y

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Short Path
 Sequential Circuits Input Timing
8
• Setup time: tsetup = time before
clock edge data must be stable
CLK
(i.e. not changing)
• Hold time: thold = time after clock
edge data must be stable
D
• Aperture time: ta = time around
tsetup thold clock edge data must be stable
(ta = tsetup + thold)
ta

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 Sequential Circuits: Output Timing
9

• Propagation delay: tpcq = time

CLK after clock edge that the output
Q is guaranteed to be stable (i.e.,
Q to stop changing)
• Contamination delay: tccq = time
tccq after clock edge that Q might be
tpcq
unstable (i.e., start changing)

COMPUTER SCIENCE DEPARTMENT

 Timing Constraints
10

• Synchronous sequential circuit inputs must be stable

during aperture (setup and hold) time around clock edge

• Specifically, inputs must be stable

• at least tsetup before the clock edge
• at least until thold after the clock edge

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 Timing Analysis
11

• Schematic representation of a synchronous sequential circuit (a).

• The delay between registers has a minimum and maximum delay,
dependent on the delays of the circuit elements (b)
CLK CLK
Q1 CL D2

R1 R2
(a)
Tc
CLK

Q1

D2
(b)
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 Timing Analysis: Setup Time
12
• Depends on the maximum delay from register R1 through combinational logic
to R2
• The input to register R2 must be stable at least tsetup before clock edge
CLK CLK
Q1 CL D2
Tc ≥
R1 R2
Tc
CLK

Q1

D2
tpcq tpd tsetup
COMPUTER SCIENCE DEPARTMENT
 Setup Time Constraints
13
• Depends on the maximum delay from register R1 through combinational logic
to R2
• The input to register R2 must be stable at least tsetup before clock edge
CLK CLK
Q1 CL D2
Tc ≥ tpcq + tpd + tsetup
R1 R2
Tc
CLK

Q1

D2
tpcq tpd tsetup
COMPUTER SCIENCE DEPARTMENT
 Setup Time Contraints
14
• Depends on the maximum delay from register R1 through combinational logic
to R2
• The input to register R2 must be stable at least tsetup before clock edge
CLK CLK
Q1 CL D2
Tc ≥ tpcq + tpd + tsetup
R1 R2
Tc tpd ≤ Tc – (tpcq + tsetup)
CLK

Q1 (tpcq + tsetup): sequencing overhead

D2
tpcq tpd tsetup
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 Timing Analysis: Hold Time
15
• Depends on the minimum delay from register R1 through the combinational
logic to R2
• The input to register R2 must be stable for at least thold after the clock edge
CLK CLK
Q1 CL D2

R1 R2
thold <

CLK

Q1

D2
tccq tcd
t
hold DEPARTMENT
COMPUTER SCIENCE
 Hold Time Constraints
16
• Depends on the minimum delay from register R1 through the combinational
logic to R2
• The input to register R2 must be stable for at least thold after the clock edge
CLK CLK
Q1 CL D2

R1 R2
thold < tccq + tcd

CLK

Q1

D2
tccq tcd
t
hold DEPARTMENT
COMPUTER SCIENCE
 Hold Time Constraints
17
• Depends on the minimum delay from register R1 through the combinational
logic to R2
• The input to register R2 must be stable for at least thold after the clock edge
CLK CLK
Q1 CL D2

R1 R2
thold < tccq + tcd
tcd > thold - tccq
CLK

Q1

D2
tccq tcd
t
hold DEPARTMENT
COMPUTER SCIENCE
 Example: Timing Analysis
18
CLK CLK Timing Characteristics
A tccq = 30 ps
tpcq = 50 ps
B tsetup = 60 ps
thold = 70 ps
X' X
C

per gate
tpd = 35 ps
Y' Y
D tcd = 25 ps

tpd = 3 x 35 ps = 105 ps
tcd = 25 ps Hold time constraint:
Setup time constraint: tccq + tcd > thold ?
Tc ≥ ?

In the Combinational Logic

Longest path: also from B to Y’
Shortest path: also from C to X’
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 Example: Timing Analysis
19
CLK CLK Timing Characteristics
A tccq = 30 ps
tpcq = 50 ps
B tsetup = 60 ps
thold = 70 ps
X' X
C

per gate
tpd = 35 ps
Y' Y
D tcd = 25 ps

tpd = 3 x 35 ps = 105 ps
tcd = 25 ps
Setup time constraint: Hold time constraint:
Tc ≥ (50 + 105 + 60) ps = 215 ps tccq + tcd > thold ?
fc = 1/Tc = 4.65 GHz
(30 + 25) ps > 70 ps ? No!

COMPUTER SCIENCE DEPARTMENT

 Example: Timing
Timing Analysis
Analysis
20
Solution: Add buffers to the short paths:
CLK CLK
A Timing Characteristics
tccq = 30 ps
tpcq = 50 ps
B
tsetup = 60 ps
X' X
thold = 70 ps
C

per gate
tpd = 35 ps
Y' Y
D tcd = 25 ps

tpd = 3 x 35 ps = 105 ps
tcd = 2 x 25 ps = 50 ps Hold time constraint:
Setup time constraint: tccq + tcd > thold ?
Tc ≥ ?

COMPUTER SCIENCE DEPARTMENT

 Example: Timing Analysis
21
Solution: Add buffers to the short paths:
CLK CLK
A Timing Characteristics
tccq = 30 ps
B tpcq = 50 ps
tsetup = 60 ps

per gate
C
X' X thold = 70 ps

Y' Y tpd = 35 ps
D
tcd = 25 ps
tpd = 3 x 35 ps = 105 ps
tcd = 2 x 25 ps = 50 ps Hold time constraint:
Setup time constraint: tccq + tcd > thold ?
Tc ≥ (50 + 105 + 60) ps = 215 ps
(30 + 50) ps > 70 ps ? Yes!
fc = 1/Tc = 4.65 GHz

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 Clock Skew
22
delay CLK
• To make things worst: The clock
doesn’t arrive at all registers at same CLK1 CLK2
time Q1 D2
C
L
• Skew: difference between two clock
edges R1 R2
• Perform worst case analysis to t
guarantee time constraints is not
skew

violated for any register – many CLK1

registers in a system!
CLK2

CLK

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 Setup Time Constraint with Skew
23

• In the worst case, CLK2 is earlier than CLK1

CLK1 CLK2
Q1 C D2
L

R1 R2
Tc
CLK1
Tc ≥ ?
CLK2

Q1

D2

tpcq tpd tsetup tskew

COMPUTER SCIENCE DEPARTMENT

 Setup Time Constraint with Skew
24

• In the worst case, CLK2 is earlier than CLK1

CLK1 CLK2
Q1 C D2
L

R1 R2
Tc
CLK1
Tc ≥ tpcq + tpd + tsetup + tskew
CLK2

Q1

D2

tpcq tpd tsetup tskew

COMPUTER SCIENCE DEPARTMENT

 Setup Time Constraint with Skew
25

• In the worst case, CLK2 is earlier than CLK1

CLK1 CLK2
Q1 C D2
L

R1 R2
Tc
CLK1
Tc ≥ tpcq + tpd + tsetup + tskew
CLK2 tpd ≤ Tc – (tpcq + tsetup + tskew)
Q1

D2

tpcq tpd tsetup tskew

COMPUTER SCIENCE DEPARTMENT

 Hold Time Constraint with Skew
26

• In the worst case, CLK2 is later than CLK1

CLK1 CLK2
Q1 CL D2

R1 R2

CLK1

CLK2

Q1

D2
tccq tcd

tskew thold

COMPUTER SCIENCE DEPARTMENT

27
Hold Time Constraint with Skew
• In the worst case, CLK2 is later than CLK1
CLK1 CLK2
Q1 CL D2

R1 R2

CLK1

CLK2 tccq + tcd > thold + tskew

Q1

D2
tccq tcd

tskew thold

COMPUTER SCIENCE DEPARTMENT

28
Hold Time Constraint with Skew
• In the worst case, CLK2 is later than CLK1
CLK1 CLK2
Q1 CL D2

R1 R2

CLK1

CLK2 tccq + tcd > thold + tskew

Q1
tcd > thold + tskew – tccq
D2
tccq tcd

tskew thold

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 Remember: if the circuit is asynchronous
t t
…
29 setup hold

Asynchronous (for example, user) CLK

inputs might violate the previous
timing analysis taperture

Case I
CLK
button

Q
D
Q
D

Case II
Q

Case III
???
Q

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 Recall: D Flip-Flop
30

• Inputs: WE, D D Flip-Flop

• Function Symbols
– Samples D on rising edge of WE
• When WE rises from 0 to 1, D passes through to Q
• Otherwise, Q holds its previous value D Q
– Q changes only on rising edge of WE
• Activated on the WE edge (edge-triggered). Q

D Flip-Flop operation is now associated with a CLK (clock) instead of a WE.

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 Recall: D Flip-Flop Internal Circuit
31

• Two back-to-back latches (L1 and L2) controlled by

complementary WE CLK
WE
• When WE = 0
– L1 is transparent
– L2 is opaque CLK
WE CLK
WE
– D passes through to N1 N1
• When WE = 1 D D Q D Q Q
– L2 is transparent L1 Q L2 Q Q
– L1 is opaque
– N1 passes through to Q
• Thus, on the edge of the WE (when WE rises from 0 1)
– D passes through to Q
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 D Flip Flop Timing
32

• Flip-flop samples D at clock edge

• D must be stable when sampled
• Similar to a photograph, D must be stable around
clock edge
• If not, metastability can occur

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 D Flip-Flop Input Timing Constraints
33

• D must be stable when sampled (i.e., at active clock edge)

CLK CLK

D
D Q
tsetup thold

ta

• Setup time (tsetup): time before the clock edge that data must be
stable (i.e. not changing)
• Hold time (thold): time after the clock edge that data must be
stable
• Aperture time (ta): time around clock edge that data must be
stable (ta = tsetup + thold)
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 Metastability
34
• Bistable devices: two stable states, and a metastable state between them
• Flip-flop: two stable states (1 and 0) and one metastable state
• If flip-flop lands in metastable state, could stay there for an undetermined
amount of time

metastable

stable stable

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 Violating Input Timing: Metastability
35
• If D is changing when sampled, metastability can occur
• Flip-flop output is stuck somewhere between ‘1’ and ‘0’
• Output eventually settles non-deterministically
Example Timing Violations (NAND RS Latch)

CLK

Q Non-deterministic
Convergence
Metastability

Source: W. J. Dally, Notes from Lecture 13: Metastability and Synchronization Failure (When
COMPUTER SCIENCE DEPARTMENT
Good Flip-Flops go Bad) 11/9/2005.
 Flip Flop Analysis
36
• Flip-flop has feedback: if Q is somewhere between 1 and 0, cross-coupled
gates drive output to either rail (1 or 0)
R
N1 Q

N2 Q
S

• Metastable signal: if it hasn’t resolved to 1 or 0

• If flip-flop input changes at random time, probability that output Q is metastable
after waiting some time, t:
P(tres > t) = (T0/Tc ) e-t/τ

tres : time to resolve to 1 or 0

T0, τ : properties of the circuit

COMPUTER SCIENCE DEPARTMENT

 Outline
37

Introduction

Timing for Sequential Logic

Implementing and Testing Finite State Machines

Conclusions

COMPUTER SCIENCE DEPARTMENT

 FSM Example 1: Divide the Clock Frequency by 3
38

The output Y is HIGH for one clock cycle out of every 3. In other
words, the output divides the frequency of the clock by 3.

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 Implementing FSM Example 1: Definitions
39
module divideby3FSM (input clk,
input reset,
output q);

reg [1:0] state, nextstate;

parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;

• We define state and nextstate as 2-bit reg

• The parameter descriptions are optional, it makes reading
easier

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 Implementing FSM Example 1: State Register
40
CLK

S’ S
Next Current
State State

// state register
always @ (posedge clk, posedge reset)
if (reset) state <= S0;
else state <= nextstate;

• This part defines the state register (memorizing process)

• Sensitive to only clk, reset
• In this example, reset is active when it is ‘1’ (active-high)

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 Implementing FSM Example 1: Next State Logic
41
CLK
M next
next k k output N
inputs state
state state
outputs
logic
logic

// next state logic

always @ (*)
case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: nextstate = S0;
default: nextstate = S0;
endcase

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 Implementing FSM Example 1: Output Logic
42
CLK
M next
next k state k output N
inputs state
state
outputs
logic
logic

// output logic
assign q = (state == S0);

• In this example Moore type FSM: output depends only on state

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 Implementation of FSM Example 1
43
module divideby3FSM (input clk, input reset, output q);
reg [1:0] state, nextstate;

parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10;

always @ (posedge clk, posedge reset) // state register

if (reset) state <= S0;
else state <= nextstate;

always @ (*) // next state logic

case (state)
S0: nextstate = S1;
S1: nextstate = S2;
S2: nextstate = S0;
default: nextstate = S0;
endcase
assign q = (state == S0); // output logic
endmodule

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 FSM Example 2: Smiling Snail
44

• Alyssa P. Hacker has a snail that crawls down a paper tape with 1’s and 0’s
on it.
• The snail smiles whenever the last four digits it has crawled over are
1101.
• Design Moore and Mealy FSMs of the snail’s brain.

Moore

Mealy
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 Implementing FSM Example 2: Definitions
45
module SmilingSnail (input clk,
input reset,
input number,
output smile);

reg [1:0] state, nextstate;

parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2’b11;

number/smile

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 Implementing FSM Example 2: State Register
46

// state register
always @ (posedge clk, posedge reset)
if (reset) state <= S0;
else state <= nextstate;

• This part defines the state register (memorizing process)

• Sensitive to only clk, reset
• In this example reset is active when ‘1’ (active-high)

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 Implementing FSM Example 2: Next State Logic
47
// next state logic
always @ (*)
case (state)
S0: if (number) nextstate = S1;
else nextstate = S0;
S1: if (number) nextstate = S2;
else nextstate = S0;
S2: if (number) nextstate = S2;
else nextstate = S3;
S3: if (number) nextstate = S1;
else nextstate = S0;
default: nextstate = S0;
endcase

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 Implementing FSM Example 2: Output Logic
48

// output logic
assign smile = (number & state == S3);

• In this example, output depends on state and input

• Mealy type FSM
• We used a simple combinational assignment

COMPUTER SCIENCE DEPARTMENT

 Implementation of FSM Example 2
49
module SmilingSnail (input clk, always @ (*) // next state logic
input reset, case (state)
input number, S0: if (number)
output smile); nextstate = S1;
else nextstate = S0;
reg [1:0] state, nextstate; S1: if (number)
nextstate = S2;
parameter S0 = 2'b00; else nextstate = S0;
parameter S1 = 2'b01; S2: if (number)
parameter S2 = 2'b10; nextstate = S2;
parameter S3 = 2'b11; else nextstate = S3;
S3: if (number)
// state register nextstate = S1;
always @ (posedge clk, posedge else nextstate = S0;
reset) default: nextstate = S0;
if (reset) state <= S0; endcase
else state <= nextstate; // output logic
assign smile = (number & state==S3);

endmodule

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 Outline
50

Introduction

Timing for Sequential Logic

Implementing and Testing Finite State Machines

Conclusions

COMPUTER SCIENCE DEPARTMENT

 Conclusions
51

• We detailed the timing operation of sequential logic

circuits.
• We explain the relation between timing and correct
operation of circuits
• We implemented Moore FSM and Mealy FSM using
Verilog.
• We conclude that FSM can be implemented using the
fundamental concepts about circuit design and timing
analysis.
COMPUTER SCIENCE DEPARTMENT
Finite State Machine
Computer Architecture

CS2201 - 2021I 5
2
PROF.: JGONZALEZ@UTEC.EDU.PE